JP2007174554A - High frequency power amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high frequency power amplifier circuit capable of highly accurately performing feedback control on output power by improving a detection sensitivity of an output power detection circuit in the area of a low output level in a radio communication system which detects the output level and performs feedback control on output power. <P>SOLUTION: An output power detection circuit (220) for detecting output power of a power amplifier circuit (210) which amplifies a high-frequency input signal is comprised of pre-stage and post-stage two detection circuits (221, 222) each capable of detecting an AC signal extracted from the power amplifier circuit. Furthermore, a first capacitive element (Ci1) provided between a coupler provided in the middle of an output line of the power amplifier and the pre-stage detection circuit and a second input capacitive element (Ci2) provided between the coupler and the post-stage detection circuit are provided, and the first input capacitive element is set so that a capacitance value thereof becomes greater than that of the second input capacitive element. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique that is effective when applied to a high-frequency power amplifier circuit that is used in a wireless communication device such as a cellular phone and amplifies a high-frequency transmission signal and outputs it, and in particular, detects an output level necessary for feedback control of output power. The present invention relates to a technique that is effective for use in a high-frequency power amplifier circuit including an output power detection circuit that performs the above.

  In general, a high-frequency power amplification circuit that amplifies a modulated signal is incorporated in a transmission-side output unit in a wireless communication device (mobile communication device) such as a mobile phone. Then, in order to control the output power of the high frequency power amplifier circuit according to the transmission level required from the control circuit such as the baseband circuit or the microprocessor, the output level of the high frequency power amplifier circuit is detected and fed back. It is. Conventionally, the output level is generally detected using a coupler, a diode detection circuit, or the like, and the detection circuit is often configured as a semiconductor integrated circuit separate from the high-frequency power amplifier circuit. Therefore, in the conventional output power detection method of the high-frequency power amplifier circuit, it is difficult to reduce the size of the module as an electronic component equipped with the high-frequency power amplifier circuit or the detector circuit.

  Further, in recent cellular phones, GSM (Global System for Mobile Communication) using a frequency of 880 to 915 MHz is performed by a phase modulation method called GMSK (Gaussian Minimum Shift Keying) that shifts the phase of a carrier wave according to transmission data. In addition to a communication method called “), a dual-band mobile phone capable of handling a signal of a communication method such as DCS (Digital Cellular System) using a frequency of 1710 to 1785 MHz band has been proposed. In the high frequency power amplifier circuit used in such a cellular phone, since an output power amplifier is provided for each band, a coupler and a diode detection circuit for detecting the output level are also required for each band. Miniaturization becomes difficult.

Accordingly, the present applicant has received an input signal of a power amplification transistor for amplifying a high-frequency transmission signal, receives an output detection transistor for passing a current proportional to the current flowing through the power amplification transistor, and a current mirror for transferring the current of the transistor A circuit is provided, and the current at the transfer destination of the current mirror circuit is converted into a voltage to obtain an output level detection signal, and the detection signal is compared with an output level instruction signal supplied from the baseband circuit in accordance with the input potential difference. An invention relating to a current detection type radio communication system that generates an output control voltage Vapc to control a bias of a power amplification transistor to control an output level has been made.
JP 2004-140518 A JP 2001-016116 A

  The inventors examined the relationship between the output level instruction signal Vramp and the output power Pout in the current detection type high frequency power amplifier circuit developed by the present applicant. As a result, when the sensitivity is set so that the control sensitivity in the region with a high output level is optimized, the control sensitivity in the region with a low output level is low and the accuracy is deteriorated. In addition, if the sensitivity is set so that the control sensitivity in the low output level region is optimal, the control sensitivity in the high output level region is too high, and the output of the detector circuit is saturated in the high output level region. It became clear that it was impossible to control.

  Therefore, an invention that solves the above problems by applying an n-th root circuit or a logarithmic conversion circuit in the subsequent stage of the current detection circuit has been filed (Patent Document 1). In addition, a method for detecting output power by putting a signal extracted from a coupler into a detection circuit having the same configuration as that of a current detection type detection circuit was examined. As a result, it was found that a relatively good detection output can be obtained.

  However, in recent years, in a GSM mobile phone, the maximum output power is 30 to 35 dBm, which is higher than the conventional maximum output power of 25 to 30 dBm, for example, from a low output of 5 dBm to a high output of 35 dBm. If the detector circuit is configured so that it can detect up to, even if an n-th root circuit is inserted after the detector circuit, the detection sensitivity in the low output level region is low and sufficient detection voltage cannot be obtained. Control is not possible. In addition, it has been clarified that there is a problem that the characteristics of the power control loop vary in a low power region.

  On the other hand, an invention has also been proposed in which a low-sensitivity detection circuit for detecting a signal from a coupler and a high-sensitivity detection circuit are provided in parallel, and a signal obtained by combining the detection outputs of the two detection circuits is used as a detection detection output. (For example, Patent Document 2). However, in the case where the low-sensitivity detection circuit and the high-sensitivity detection circuit are provided in parallel as described above, a sudden change in step or slope occurs at the switching point of the outputs of the two detection circuits, resulting in a smooth output level. There is a problem that control cannot be performed and the transmission spectrum deteriorates.

  An object of the present invention is to increase the detection sensitivity of an output power detection circuit in a region where the output level is low and to perform feedback control of the output power with high accuracy in a wireless communication device that performs output power feedback control by detecting the output level. An object of the present invention is to provide a high frequency power amplifier circuit capable of

  Another object of the present invention is to prevent a sudden change in level difference or inclination in the detection output, and to widen the dynamic range of the output power detection circuit to provide a relatively smooth output from a low output level to a high output level. An object of the present invention is to provide a high frequency power amplifier circuit capable of performing level control.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Outlines of representative ones of the inventions disclosed in the present application will be described as follows.

  In other words, each AC signal extracted from the power amplifier circuit can be detected by the output power detector circuit that is provided in the subsequent stage of the power amplifier circuit that amplifies the high-frequency input signal and detects the output level necessary for feedback control of the output power. Two upstream detection circuits are provided. Also, the first input capacitive element provided between the coupler provided in the middle of the output line of the power amplifier circuit and the detection circuit in the previous stage, and provided between the coupler and the second detection circuit in the subsequent stage. The second input capacitive element is provided, and the first input capacitive element is set to have a larger capacitance value than the second input capacitive element. Further, of the two detection circuits, the detection transistor of the preceding detection circuit is set to be smaller in size than the detection transistor of the subsequent detection circuit.

  According to the above-described means, when the output power is detected in the low power region, the AC signal can be sufficiently input to the detection circuit in the previous stage through the first input capacitive element, while the output is sufficiently high. Then, an AC signal is input to the detection circuit at the subsequent stage via the second input capacitive element. Therefore, it is possible to increase the sensitivity of the output power detection circuit in the low power region, and to avoid the sensitivity of the entire output power detection circuit from becoming too high in the high power region, thereby reducing the dynamic range of the output power detection circuit. The detection signal having the optimum output level can be output over the entire control range. Further, a square root circuit is provided between the two detection circuits, and a voltage obtained by squaring the output of the detection circuit in the previous stage is given as a bias voltage for the detection circuit in the subsequent stage. Thereby, the detection output is smoothly switched.

  Here, the optimum range of the capacitance ratio of the first input capacitive element and the second input capacitive element is 20: 1 to 5: 1, and the size of the detection transistor of the detection circuit in the previous stage and the detection transistor of the detection circuit in the subsequent stage. The optimum range of the ratio is 1: 1.5 to 1: 4. By setting the ratio of the input capacitance and the size ratio of the transistors within such a range, a detection signal having an optimum output level can be obtained from the output power detection circuit.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, in a wireless communication apparatus that detects the output level and performs feedback control of the output power, the detection sensitivity of the output power detection circuit in the region where the output level is low is increased, and the output power is feedback-controlled with high accuracy. It is possible to realize a high-frequency power amplifier circuit that can be used.

  Further, according to the present invention, it is possible to prevent a sudden change in level difference or inclination in the detection output, and to widen the dynamic range of the output power detection circuit so that the output level is relatively smooth from a low output level to a high output level. A high frequency power amplifier circuit capable of performing control can be realized.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings.

  FIG. 1 shows a schematic configuration of an embodiment of a high-frequency power amplifier circuit according to the present invention.

  The power module 200 of this embodiment includes a high frequency power amplifier 210 including an amplification FET that amplifies an input high frequency signal Pin, an output power detection circuit 220 that detects output power of the high frequency power amplifier 210, and the output power detection circuit. An error amplifying circuit (hereinafter referred to as an error amplifier) 230 that supplies a power control signal Vapc according to a potential difference between a detection output Vdet 220 and a signal Vramp indicating an output level supplied from a baseband circuit (not shown) or the like. .

  The output power detection circuit 220 includes a first detection circuit 221 that receives an AC signal extracted by a coupler 240 provided in the middle of the output line of the high-frequency power amplifier 210, and 2 outputs of the first detection circuit 221. A square root circuit 222 that takes a root, a second detection circuit 223 that amplifies an AC signal from the coupler 240 using the output of the square root circuit 222 as a bias voltage, and the like are provided.

  The AC signal extracted by the coupler 240 is input to the first detection circuit 221 via the capacitive element Ci1, and the AC signal extracted by the coupler 240 is also input to the second detection circuit 223 via the capacitive element Ci2. Entered. An element having a capacitance value (about 10 times larger) than Ci2 is used for the capacitive element Ci1. By making Ci1 larger than Ci2, the detection sensitivity in the low power region of the first detection circuit 221 can be increased. The capacitive elements Ci1 and Ci2 are on-chip elements in this embodiment, but may be external elements.

  FIG. 2 shows a specific circuit example of the output power detection circuit 220. The first detection circuit 221 includes a capacitor Ci1 having one terminal connected to the coupler 240 shown in FIG. 1, and an N-channel MOSFET (Metal-) for detection in which the other terminal of the capacitor Ci1 is connected to the gate. Oxide Semiconductor Field-Effect Transistor) Q1, P-channel MOSFET Q2 connected in series with MOSFET Q1, and capacitor C2 connected between the drain terminal of Q1 and the ground point.

  Further, the first detection circuit 221 converts a constant current Iref1 supplied from the outside into a voltage and generates a bias voltage that gives an operating point of the detection MOSFET Q1, and is connected to the gate terminal of Q3. It has the capacity | capacitance C1 connected between the points. The bias voltage Vg1 generated by the MOSFET Q3 is applied to the gate terminal of the detection MOSFET Q1 via the resistor R1. The resistor R1 and the capacitor C1 constitute a low-pass filter so that the bias voltage does not fluctuate due to an AC signal input via the capacitor Ci1.

  In the present embodiment, the value of the gate bias voltage Vg1 of the detection MOSFET Q1 of the first detection circuit 221 is a voltage value close to the threshold voltage of Q1 so that the MOSFET Q1 can be operated in class B amplification. Is set. As a result, a current that is proportional to the AC signal input through the capacitor Ci1 and half-wave rectified flows through the MOSFET Q1, and the drain current I1 of the Q1 is a DC component that is proportional to the amplitude of the input AC signal. To be included. This current I1 is supplied to the MOSFET Q2 and further supplied to the MOSFET Q20 in the square root circuit 222 that is current-mirror connected to Q2, and corresponds to the square root of the MOSFET Q30 to I1 in the final stage of the square root circuit 222. Current I2 (= √I1) to be output is input to the second detection circuit 223 at the subsequent stage.

  The second detection circuit 223 has the same configuration as the first detection circuit 221 except that the input capacitance and the size of the detection MOS transistor are different. That is, a capacitor Ci2 having one terminal connected to the coupler 240 in FIG. 1, a detection N-channel MOSFET Q31 having the other terminal connected to the gate, and a P connected in series with the MOSFET Q31. A capacitor C4 is connected between the drain terminals of the channel MOSFETs Q32 and Q31 and the ground point.

  The second detection circuit 223 converts a constant current I2 supplied from the output MOSFET Q30 of the square root circuit 222 in the previous stage into a voltage, and generates a bias voltage that gives an operating point of the detection MOSFET Q31. MOSFET Q33 and a capacitor C3 connected between the gate terminal of Q33 and the grounding point. The bias voltage Vg2 generated by the MOSFET Q33 is applied to the gate terminal of the detection MOSFET Q31 via the resistor R2.

  Further, the second detection circuit 223 includes a P-channel MOSFET Q32 through which the drain current I3 of the detection MOSFET Q31 flows, a MOSFET Q34 connected in a current mirror, and a current-voltage conversion MOSFET Q35 connected in series with the MOSFET Q34. Q35 converts the current I3 into a voltage and outputs it as an output detection voltage Vdet to the error amplifier 230 at the subsequent stage.

  The square root circuit 222 includes Q21 connected in series to the MOSFET Q20, Q11 and Q11 through which a constant current Iref2 from the outside flows, Q12 connected to a current mirror, and Q13 and Q13 connected in series to Q12 and a current. Q16, Q19, and Q22 are mirror-connected, and the drain terminal of Q19 is connected to the drain terminal of Q21. Q17, Q18 connected in series with Q16, Q15 connected with Q18, Q14 connected in series with Q15, and Q14 connected in series with Q14, the drain voltage of Q16 is applied to the gate terminal of Q14, and the drain voltage of Q17 Is applied to the gate terminal of Q21.

  Further, the square root circuit 222 is configured such that Q24 of the first detection circuit 221 is connected to Q24, Q25 connected in series with Q24, Q25 connected to Q25 and Q26 connected to the current mirror, constant current Iref2 Q23 is connected to Q11 through which current flows, and the drain terminal of Q23 is coupled to the drain terminal of Q26. The common drain of Q23 and Q26 is connected to the output MOSFET Q30 and Q27 which is current-mirror connected, and Q29 to which the drain voltage of Q27 is applied operates as a diode by coupling its gate terminal and drain terminal. Has been.

  In the output power detection circuit of the present embodiment, the input capacitance Ci1 of the first detection circuit 221 and the input capacitance Ci2 of the second detection circuit 223 are set such that Ci1> Ci2, while the sizes of the detection MOSFETs Q1, Q31 are Q1 <Q31. By reducing the input capacitance Ci2 of the second detection circuit 223, the change in the output is not sufficiently transmitted to the gate terminal of the detection MOSFET Q31. However, by increasing the size of the Q31, the drain current of the Q31 is reduced. Changes are compensated.

  The capacitance ratio between the input capacitance Ci1 of the first detection circuit 221 and the input capacitance Ci2 of the second detection circuit 223 is preferably about 20: 1 to 5: 1. Specific capacitance values are preferably about 10 pF for Ci1 and about 0.5 to 2 pF for Ci2 depending on the characteristics of the coupler used. This capacitance value is obtained when a coupler having a detection sensitivity dVdet / dVout of 0.1 V / V and a dVdet / dPout of 5 mV / dB is used. The size ratio between Q1 and Q31 is preferably about 1: 1.5 to 1: 4. Specifically, when the gate width Wg of Q1 is 100 μm, a desirable range of the gate width Wg of Q31 is 150 to 400 μm, and a more desirable range is 200 to 300 μm.

  In FIG. 3, the result of having calculated | required the output characteristic of the output power detection circuit of a present Example by simulation is shown. In FIG. 3, ♦ indicates a plot of the output voltage of the first detection circuit 221 when the output power Pout is changed from −45 dBm to 35 dBm, and Δ indicates a change when the output power Pout is changed from −45 dBm to 35 dBm. The output voltage of the 2nd detection circuit 223 which is an output of the output power circuit of a present Example is plotted. In order to make it easy to understand the single characteristic of the second detection circuit 223, the output power is applied in the state where the same bias voltage as that of the first detection circuit 221 is applied to the second detection circuit 223 instead of inputting the output of the square root circuit 222. The output voltage of the second detection circuit 223 when Pout is changed from −45 dBm to 35 dBm is indicated by □.

  Comparing the marks ♦ and □ in FIG. 3, it can be seen that the output of the first detection circuit 221 is saturated at an earlier stage than the output of the second detection circuit 223. The output of the first detection circuit 221 having such a characteristic is square-rooted by the square root circuit 222 and given as a bias voltage to the second detection circuit 223, so that the level in the low power region is indicated as indicated by Δ. And a detection voltage Vdet that does not saturate to a high power region such as 30 to 35 dBm can be output.

  For comparison, the characteristics of the detection voltage Vdet when only one stage detection circuit is used are indicated by a one-dot chain line A. This characteristic line A is obtained when the constants of the circuit elements are set so that the voltage at 35 dBm when the output of the first detection circuit 221 is saturated is approximately 2 V, and the output voltage of the first detection circuit 221 is It is similar to the line connecting the ◆ marks. When comparing this characteristic line A with a line connecting Δ marks plotting the output voltage of the second detection circuit 223 which is the output of the output power circuit of this embodiment, the detected voltage Vdet in the region where A is lower in power. It can be seen that the level of is low.

  Thus, when the level of the detection voltage Vdet in the low power region is low, the characteristics of the power control loop in the low power region are likely to vary. However, when the output power detection circuit of this embodiment is applied, one stage It is possible to increase the level of the detection voltage Vdet in a region where the power is lower than in the case of detection, thereby reducing variations in the characteristics of the power control loop in the region where the power is low.

  Further, as in the present embodiment, the relationship between the input capacitance Ci1 of the first detection circuit 221 and the input capacitance Ci2 of the second detection circuit 223 is Ci1> Ci2, and the sizes of the detection MOSFETs Q1, Q31 are Q1 <Q31. In this case, there is an advantage that the fluctuation range of the output power accompanying the temperature fluctuation becomes small.

  FIG. 4A shows the relationship between the detection voltage Vdet of the output power detection circuit and the output power Pout by simulation when the input capacitance is Ci1 = Ci2 and the size of the detection MOSFETs Q1 and Q31 is Q1 = Q31. The results of the investigation are shown. FIG. 4B shows the detection voltage of the output power detection circuit when the relationship between the input capacitances is Ci1> Ci2 and the size of the detection MOSFETs Q1, Q31 is Q1 <Q31 as in this embodiment. The result of having investigated the relationship between Vdet and output electric power Pout by simulation is shown. In FIG. 4, ♦ indicates characteristics when the temperature is 25 ° C., □ indicates characteristics when the temperature is −25 ° C., and Δ indicates characteristics when the temperature is 85 ° C. Comparing FIG. 4 (A) and FIG. 4 (B), it can be seen that the fluctuation range of the output power accompanying the temperature fluctuation is smaller in this embodiment.

  In the embodiment of FIG. 2, the detection voltage Vdet of the output power circuit is directly input to the error amplifier 230. However, the detection voltage Vdet of the output power circuit is applied to the gate terminal of the detection MOSFET Q1 of the first detection circuit 221. A subtracting circuit that subtracts the bias voltage Vg1 to be applied may be provided so that a difference voltage between Vdet and Vg1 is input to the error amplifier 230. Thereby, the voltage input to the error amplifier 230 can be a detection voltage proportional to the AC component of pure output power that does not include the DC component due to the bias voltage Vg1.

  Further, the detection voltage Vdet may be input to the high frequency power amplifier 210 instead of the power control signal Vapc without passing through the error amplifier 230.

  The square root circuit 222 shown in FIG. 2 is an example and is not limited to this. For example, a circuit as shown in FIG. 6 of Japanese Patent Application Laid-Open No. 2004-140518 may be used. good. The present invention may be any circuit type circuit as long as it is a square root circuit having good process consistency with a circuit formed on the same semiconductor chip, such as a detection circuit, and the circuit type is the gist of the invention. Therefore, detailed description of the operation is omitted.

  FIG. 5 shows a more specific configuration example when a high frequency power amplifier circuit to which the output power detection circuit of the present invention is applied is configured as a module (hereinafter referred to as a power module). In this specification, a plurality of semiconductor chips and discrete components are mounted on an insulating substrate such as a ceramic substrate with printed wiring on the surface or inside, and each component has a predetermined role in the printed wiring or bonding wire. A module that can be handled as one electronic component is called a module.

  A high frequency power amplifier 210 shown in FIG. 5 applies a bias voltage to a high frequency power amplifier 211 including an amplifying FET for amplifying an input high frequency signal Pin, and the amplifying FETs at each stage of the high frequency power amplifier 211. And a bias circuit 212 for controlling an idle current flowing through each FET.

  Although not particularly limited, the high-frequency power amplification unit 210 of this embodiment includes three power amplification FETs 11, 12, and 13, and the latter FETs 12 and 13 are the drain terminals of the preceding FETs 11 and 12, respectively. The gate terminal is connected to the first and second amplifier circuits as a whole. Further, gate bias voltages Vb1, Vb2, and Vb3 supplied from the bias circuit 212 are applied to the gate terminals of the FETs 11, 12, and 13 at each stage, and an idle current corresponding to these voltages is applied to the FETs 11, 12, and 13, respectively. It is made to be shed by each.

  The bias circuit 212 includes an operational amplifier OP1 that receives the control voltage Vapc supplied from the error amplifier 230 as an input voltage, a MOSFET Q40 that receives the output of the operational amplifier OP1 at its gate terminal, a resistor R10 connected in series with Q40, and Q40. And MOSFETs Q41, Q42, and Q43 that are connected in common to each other to form a current mirror circuit, and diode-connected MOSFETs Qb1, Qb2, and Qb3 connected in series with these MOSFETs Q41, Q42, and Q43, respectively. When the drain voltage of Q40 is fed back to the inverting input terminal of the operational amplifier OP1, a current I0 corresponding to Vapc is caused to flow through Q40, and a current proportional to the current I0 according to the size ratio of Q40 and Q41 to Q43 is also supplied. The current flows through Q41, Q42, and Q43, and the current is converted into a voltage by Qb1, Qb2, and Qb3, and this is applied as a bias voltage to the gates of the amplifying FETs 11, 12, and 13 via resistors R11, R12, and R13, respectively. The

  The MOSFETs Q40, Q41, Q42, and Q43 are set to have a predetermined size ratio according to the amplification FETs 11 to 13, respectively, whereby an idle current proportional to the control voltage Vapc from the error amplifier 230 is generated. ~ 13. The resistors R11 to R13 serve to suppress the currents of the bias MOSFETs Qb1 to Qb3 from being changed by leakage of a high frequency signal from the input terminal. A power supply voltage Vdd is applied to the drain terminals of the FETs 11, 12, and 13 at each stage. A direct current cut capacitive element C11 is provided between the gate terminal of the first stage FET 11 and the input terminal IN, and a high frequency signal Pin is input to the gate terminal of the FET 11 through these circuits and elements.

  A DC-cut capacitive element C12 is provided between the drain terminal of the first stage FET 11 and the gate terminal of the second stage FET 12, and between the drain terminal of the second stage FET 12 and the gate terminal of the final stage FET 13. Is connected to a DC-cut capacitive element C13. The drain terminal of the FET 13 at the final stage is connected to the output terminal OUT via the impedance matching circuit 241 and the capacitive element C14, and the signal Pout obtained by cutting the DC component of the high-frequency input signal Pin and amplifying the AC component is output. .

  In the power module 200 of this embodiment, each element of the power amplifying unit 211 (except for the DC cut capacitive elements C11 to C13) and each element of the bias circuit 212 and each element of the output power detection circuit 220 are simply The semiconductor integrated circuit is formed on one semiconductor chip such as crystalline silicon. The semiconductor integrated circuit, the capacitive elements C11 to C13 of the power amplifier 211, the impedance matching circuit 241, the DC-cut capacitive element C14, and the microcoupler 240 are mounted on one ceramic substrate as a power module. It is configured. The inductor constituting the impedance matching circuit 241 can be formed by a bonding wire connected between pads of a semiconductor chip or a microstrip line formed on a module substrate.

  FIG. 5 shows a bias circuit configured to apply a bias to the amplification FETs 11 to 13 by a current mirror method. However, the amplification FET 11 is obtained by dividing the control voltage Vapc from the error amplifier 230 by a predetermined resistance ratio. It may be a resistance voltage dividing circuit that generates a bias voltage of ˜13.

  In the high frequency power amplifier circuit using the output power detection circuit of the present embodiment, the temperature variation of the detection output Vdet-output power Pout characteristic is small as described above. Therefore, the deviation ΔPout of the output power Pout is set as shown in FIG. It can be kept within the target range. In FIG. 6, the solid line shows the change ΔPout from the output power Pout at the standard value (25 ° C.) when the temperature Ta is the maximum value (85 ° C.) of the fluctuation allowable range, and the broken line shows the temperature. The change ΔPout from the output power Pout at the standard value when Ta is the minimum value (−20 ° C.) of the fluctuation allowable range is obtained by actual measurement.

  In the GSM standard, the deviation ΔPout of the output power Pout is defined as ± 6 dB when the output power is in the range of 5 dBm to 11 dBm, and ± 4 dB when the output power is in the range of 11 dBm to 35 dBm. In FIG. 6, what is indicated by a one-dot chain line is a restriction line indicating a target range determined by the present inventors in consideration of the GSM standard and the user's request. From FIG. 6, it can be seen that by applying the present embodiment, the deviation ΔPout of the output power Pout can be substantially within the target range.

  For comparison, in the high frequency power amplifier circuit using the output power detection circuit having the same configuration as the embodiment of FIG. 2, only the capacitance ratio of the input capacitors Ci1 and Ci2 is optimized, and the size ratio of the detection MOSFETs Q1 and Q31 is FIG. 7 shows the result of obtaining the deviation ΔPout of the output power Pout when not optimized. On the other hand, FIG. 8 shows the result of obtaining the deviation ΔPout of the output power Pout when only the size ratio of the detection MOSFETs Q1 and Q31 is optimized and the capacity ratio of the input capacitors Ci1 and Ci2 is not optimized.

  7 and 8, in the case of FIG. 7, when the temperature Ta is the minimum value (−20 ° C.) of the fluctuation allowable range, the deviation ΔPout of the output power Pout is out of the target range in the low power region. In the case of FIG. 8, it can be seen that the deviation ΔPout of the output power Pout deviates from the target range in the high power region when the temperature Ta is the maximum value (85 ° C.) of the allowable fluctuation range.

  FIG. 9 shows a schematic configuration of a system capable of wireless communication using two communication systems, GSM and DCS, as an example of an effective wireless communication system to which the power module of the embodiment is applied.

  In FIG. 9, ANT is an antenna for transmitting / receiving signal radio waves, 110 is a modulation / demodulation circuit that performs modulation / demodulation, and I / Q signals generated from a received signal based on transmission data (baseband signal). A high-frequency signal processing circuit (hereinafter referred to as a baseband IC) formed into a semiconductor integrated circuit having a circuit to be processed. This baseband IC 110, low noise amplifiers LNA1 and LNA2 for amplifying the received signal, bandpass filters BPF1 and BPF2 for removing harmonic components from the transmitted signal, bandpass filters BPF3 and BPF4 for removing unnecessary waves from the received signal, etc. It is configured as an electronic device (hereinafter referred to as an RF device) mounted in one package. The low noise amplifiers LNA1 and LNA2 can be incorporated in the baseband IC 110.

  Baseband IC 110 includes mixers Tx-MIX1 and Tx-MIX2 for up-converting GSM and DCS transmission signals, mixers Rx-MIX1 and Rx-MIX2 for down-converting GSM and DCS reception signals, and these mixers. Are provided with oscillators VCO1 to VCO4 that generate oscillation signals mixed with transmission signals and reception signals, and variable gain amplifiers GCA1 and GAC2 for amplifying transmission signals of GSM and DCS, respectively.

  In FIG. 9, reference numeral 200 denotes the power module of the above-described embodiment that amplifies a high-frequency transmission signal supplied from the baseband IC 110, and 300 denotes filters LPF1, LPF2, and GSM that remove noise such as harmonics contained in the transmission signal. This is a front-end module including demultiplexers DPX1 and DPX2 that synthesize and separate the DCS signal and DCS signal, a transmission / reception changeover switch T / R-SW, and the like. The power module 200 is provided with a GSM power amplifier 211a and a DCS power amplifier 211b.

  As shown in FIG. 9, in this embodiment, a mode selection signal VBAND indicating GSM or DCS is supplied from the baseband IC 110 to the bias circuit 212 of the power amplifiers 211a and 211b of the high frequency power amplifier circuit. Based on the control signal VBAND, the bias circuit 212 generates a bias current corresponding to the mode and supplies it to one of the power amplifiers 211a and 211b. The bias circuit 230 in FIG. 9 is a circuit provided with a circuit composed of the current mirror circuit of the MOSFETs Q40 to Q43 and the bias MOSFETs Qb1 to Qb3 in FIG.

  In the GSM and DCS dual-band communication system as described above, the maximum levels of the output power of the GSM-side power amplifier 211a and the output power of the DCS-side power amplifier 211b are defined by different standards. . Therefore, output power detection circuit 220 and error amplifier 230 are provided as a common circuit, while bias circuits are provided for GSM and DCS, respectively, and either one is selectively operated in accordance with control signal VBAND. It is comprised so that it can be made.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above-described embodiment, MOSFETs are used for the amplifying transistors 11 to 13 of the high-frequency power amplifying unit, but other transistors such as bipolar transistors, GaAs MESFETs, heterojunction bipolar transistors (HBT), HEMTs (High Electron Mobility Transistors), It is also possible to use a transistor.

  In the above-described embodiment, the case where the number of amplification stages of the high-frequency power amplification unit is three, but the number of amplification stages may be one or two. Further, the current-voltage conversion MOSFET Q35 provided in the output section of the output power detection circuit 220 may be a resistance element.

  Further, in the above embodiment, the output of the second detection circuit 223 is input to the error amplifier 230. However, a combination of the output of the second detection circuit 223 and the output of the square root circuit 222 is converted into a voltage. It may be configured to input to the error amplifier 230. Specifically, for example, in the circuit of FIG. 2, a MOSFET that receives the same gate voltage as Q30 at the gate terminal and flows a current that is the same as or proportional to I2 is provided in parallel with MOSFET Q34, and the current is combined with the current of Q34. To Q35 for conversion to voltage. However, in that case, the optimum capacitance ratio of the input capacitors Ci1 and Ci2 and the optimum size ratio of the detection MOSFETs Q1 and Q31 may be in a range different from that of the above-described embodiment.

  Further, in the second detection circuit of the above-described embodiment, the square root circuit 222 is provided between the first detection circuit 221 and the second detection circuit 223, but an nth root circuit is used instead of the square root circuit 222. Alternatively, a logarithmic conversion circuit may be provided. Alternatively, the square root circuit may be omitted depending on the application target and conditions, and the output of the first detection circuit 221 may be provided to the second detection circuit 223.

  In the above description, the case where the invention made mainly by the present inventor is applied to a high frequency power amplifier circuit and a power module used in a mobile phone which is a field of use behind the present invention has been described, but the present invention is not limited thereto. It can be used for a high-frequency power amplifier circuit and a power module that constitute a wireless LAN.

It is a block diagram which shows schematic structure of the Example of the high frequency power amplifier circuit which concerns on this invention. It is a circuit diagram which shows one Example of an output electric power detection circuit. It is a characteristic view which shows the relationship between the output power Pout in the high frequency power amplifier circuit of an Example, and the output voltage Vdet of an output power detection circuit. 4A is a graph showing a result of actual measurement of the relationship between the detection voltage Vdet of the output power detection circuit and the output power Pout when Ci1 = Ci2 and Q1 = Q31, and FIG. It is a graph which shows the result of having investigated by simulation the relationship between the detection voltage Vdet of the output electric power detection circuit and output electric power Pout in the case of Ci1> Ci2 and Q1 <Q31 like this actual example. It is a circuit block diagram which shows the more specific structural example at the time of comprising as a module the high frequency power amplifier circuit to which the output power detection circuit of this invention is applied. It is a graph which shows the result of having calculated | required the relationship with output deviation (DELTA) Pout of the output electric power Pout in the feedback control system of the high frequency power amplifier to which the output electric power detection circuit of an Example was applied. Only the capacitance ratio of the input capacitors Ci1 and Ci2 was optimized with a high frequency power amplifier using an output power detection circuit having the same configuration as the output power detection circuit of the example, and the size ratio of the detection MOSFETs Q1 and Q31 was not optimized. It is a graph which shows the relationship with output deviation (DELTA) Pout of the output electric power Pout in the feedback control system in the case. Only the size ratio of the detection MOSFETs Q1 and Q31 was optimized with a high-frequency power amplifier using an output power detection circuit having the same configuration as the output power detection circuit of the example, and the capacitance ratio of the input capacitors Ci1 and Ci2 was not optimized. It is a graph which shows the relationship with output deviation (DELTA) Pout of the output electric power Pout in the feedback control system in the case. It is a block diagram which shows schematic structure of an example of a suitable radio | wireless communications system by applying the high frequency power amplifier circuit (power module) which concerns on this invention.

Explanation of symbols

100 RF module 110 Baseband circuit (IC)
200 Power Module 210 High Frequency Power Amplifier Circuit 211 High Frequency Power Amplifier (Power Amplifier)
212 Bias circuit 220 Output power detection circuit 221 First detection circuit 222 Square root circuit 223 Second detection circuit 230 Error amplification circuit (error amplifier)
240 Coupler 241 Impedance matching circuit 300 Front end module ANT Transmit / receive antenna LPF Low pass filter LNA Low noise amplifier GCA Variable gain amplifier

Claims (14)

A power amplifying circuit that has an amplifying element and a bias circuit that applies a bias to the amplifying element, and amplifies and outputs a high-frequency input signal according to the bias from the bias circuit;
A first detection circuit for detecting an AC signal input via a first input capacitive element having one terminal connected to a coupler provided in the middle of an output line of the power amplifier circuit; and A square root circuit that outputs a voltage proportional to the square root of the output, and an alternating current that is input via the second input capacitive element that receives the output voltage of the square root circuit and has one terminal connected to the coupler. An output power detection circuit having a second detection circuit for detecting a signal, and a high-frequency power amplification circuit comprising:
Each of the first detection circuit and the second detection circuit includes a detection transistor that receives an AC signal input via the first input capacitance element or the second input capacitance element at a control terminal,
The high frequency power amplifier circuit, wherein the first input capacitive element is set to have a capacitance value larger than that of the second input capacitive element.   2. The high frequency power amplifier circuit according to claim 1, wherein a capacitance ratio between the first input capacitive element and the second input capacitive element is set in a range of 20: 1 to 5: 1.   2. The high frequency circuit according to claim 1, wherein the power amplifier circuit further includes an error amplifier circuit that outputs a voltage corresponding to a potential difference between an output of the output power detection circuit and a signal indicating an output level. Power amplifier circuit. A power amplifying circuit that has an amplifying element and a bias circuit that applies a bias to the amplifying element, and amplifies and outputs a high-frequency input signal according to the bias from the bias circuit;
A first detection circuit for detecting an AC signal input via a first input capacitive element having one terminal connected to a coupler provided in the middle of an output line of the power amplifier circuit; and A square root circuit that outputs a voltage proportional to the square root of the output, and an alternating current that is input via the second input capacitive element that receives the output voltage of the square root circuit and has one terminal connected to the coupler. An output power detection circuit having a second detection circuit for detecting a signal, and a high-frequency power amplification circuit comprising:
Each of the first detection circuit and the second detection circuit includes a detection transistor that receives an AC signal input via the first input capacitance element or the second input capacitance element at a control terminal,
The detection transistor of the first detection circuit is set to be smaller in size than the detection transistor of the second detection circuit.   5. The size ratio of the detection transistor of the first detection circuit and the detection transistor of the second detection circuit is set in a range of 1: 1.5 to 1: 4. High frequency power amplifier circuit.   5. The high frequency circuit according to claim 4, wherein the power amplifier circuit further includes an error amplifier circuit that outputs a voltage corresponding to a potential difference between an output of the output power detection circuit and a signal indicating an output level. Power amplifier circuit. A power amplifying circuit that has an amplifying element and a bias circuit that applies a bias to the amplifying element, and amplifies and outputs a high-frequency input signal according to the bias from the bias circuit;
A first detection circuit for detecting an AC signal input via a first input capacitive element having one terminal connected to a coupler provided in the middle of the output line of the power amplifier circuit; and A square root circuit that outputs a voltage proportional to the square root of the output, and an alternating current that is input via the second input capacitive element that receives the output voltage of the square root circuit and has one terminal connected to the coupler. An output power detection circuit having a second detection circuit for detecting a signal, and a high-frequency power amplification circuit comprising:
Each of the first detection circuit and the second detection circuit includes a detection transistor that receives an AC signal input via the first input capacitance element or the second input capacitance element at a control terminal,
The first input capacitive element is set to have a capacitance value larger than that of the second input capacitive element,
The detection transistor of the first detection circuit is set to be smaller in size than the detection transistor of the second detection circuit.   The capacitance ratio of the first input capacitance element and the second input capacitance element is set in a range of 20: 1 to 5: 1, and the detection transistor of the first detection circuit and the detection transistor of the second detection circuit are sized. 8. The high frequency power amplifier circuit according to claim 7, wherein the ratio is set in a range of 1: 1.5 to 1: 4.   9. The high-frequency power amplifier circuit according to claim 7, wherein the output power detection circuit outputs a combination of the output of the square root circuit and the output of the second detection circuit as a detection output.   Each of the first detection circuit and the second detection circuit includes the detection transistor, a second transistor connected in series with the detection transistor, and a third transistor connected to the second transistor in a current mirror connection. The high frequency power amplifier circuit according to claim 7, wherein the high frequency power amplifier circuit is provided.   8. The high frequency circuit according to claim 7, wherein the power amplifier circuit further includes an error amplifier circuit that outputs a voltage corresponding to a potential difference between an output of the output power detection circuit and a signal indicating an output level. Power amplifier circuit.   A first detection circuit that detects an output of a power amplifier circuit that amplifies a high-frequency input signal and generates a voltage corresponding to the output, and outputs a voltage that is proportional to the square root of the output of the first detection circuit 2 A high-frequency power amplifier circuit comprising: an output power detection circuit having a multiplier root circuit; and a second detector circuit that receives an output voltage of the square root circuit and detects an output of the power amplifier circuit. A power amplifying circuit that has an amplifying element and a bias circuit that applies a bias to the amplifying element, and amplifies and outputs a high-frequency input signal according to the bias from the bias circuit;
A first detection circuit for detecting an AC signal input via a first input capacitive element having one terminal connected to a coupler provided in the middle of an output line of the power amplifier circuit; and A high-frequency power amplifier circuit comprising: an output power detection circuit having a second detection circuit that receives an output and detects an AC signal input through a second input capacitive element having one terminal connected to the coupler. There,
Each of the first detection circuit and the second detection circuit includes a detection transistor that receives an AC signal input via the first input capacitance element or the second input capacitance element at a control terminal,
The first input capacitive element is set to have a capacitance value larger than that of the second input capacitive element,
The detection transistor of the first detection circuit is set to be smaller in size than the detection transistor of the second detection circuit. 14. The high frequency signal according to claim 13, wherein the power amplifier circuit further comprises an error amplifier circuit that outputs a voltage corresponding to a potential difference between an output of the output power detection circuit and a signal indicating an output level. Power amplifier circuit.

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