JP2005197860A - High frequency power amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high frequency power amplifier circuit where the output power can be controlled to be a desired level by means of a control loop even when the characteristic of a detection transistor is changed due to a temperature change in a wireless communication system wherein the output power of the high frequency power amplifier circuit is detected and feedback control is carried out. <P>SOLUTION: In an output power detection circuit comprising: an output detection transistor Q1 for receiving an AC signal extracted from an output section of the high frequency power amplifier circuit via a coupling capacitance at its control terminal and flowing a current proportional to the output power; a bias generating circuit 223 for giving an operating point to the control terminal of the transistor; current mirror circuits Q2, Q3 for tranferring the current flowing through the output detection transistor; and a current-voltage conversion circuit Q4 for converting the tranferred current into a voltage, the bias generating circuit is provided with a temperature detecting element or an element D1 whose temperature dependence is comparatively conspicuous. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a high-frequency power amplifier circuit that is used in a radio communication system such as a cellular phone and amplifies a high-frequency transmission signal and outputs the same, and particularly to a technology effective when applied to an electronic component incorporating the same. The present invention relates to a technology that is effective for use in a detection circuit for output power required for the above.

In general, a transmission-side output unit in a wireless communication device (mobile communication device) such as a mobile phone is provided with a high-frequency power amplification circuit that amplifies a modulated transmission signal. In conventional wireless communication devices, the output power of a high-frequency power amplifier circuit or antenna is detected in order to control the amplification factor of the high-frequency power amplifier circuit according to the transmission request level from a control circuit such as a baseband circuit or a microprocessor Thus, a feedback is performed (see, for example, Patent Document 1). Conventionally, the detection of the output power is generally performed using a coupler, a detection circuit, or the like, and the detection circuit is often composed of a semiconductor integrated circuit or a discrete component separate from the high-frequency power amplification circuit. .
JP 2000-151310 A

  In the conventional output power detection method of a high frequency power amplifier circuit using a coupler, a diode is required to detect the detection output in addition to the size of the coupler itself. Since many semiconductor integrated circuits and electronic components are used, it has been difficult to reduce the size of the module. In addition, when a coupler is used, there is a problem that power loss is relatively large.

  Furthermore, in recent mobile phones, in addition to a method called GSM (Global System for Mobile Communication) using a frequency of 880 to 915 MHz, for example, a DCS (Digital Cellular System) using a frequency of 1710 to 1785 MHz is used. Dual-band mobile phones that can handle various types of signals have been proposed. In a high-frequency power amplification module (power module) used in such a cellular phone, an output power amplifier is provided for each band, so that a coupler and a detection circuit for detecting the output power are also required for each band. . Therefore, it becomes difficult to further downsize the module.

  Among the characteristics required for the output power detection circuit of the high frequency power amplifier circuit in the radio communication system, the following five points are particularly important characteristics. First, it is small, second is high sensitivity, third is low insertion loss, fourth is less susceptible to changes in the usage environment such as power supply voltage fluctuations and temperature changes, and fifth, This is because an abnormal current flows through the power amplifier circuit due to a mismatch between the actual output state of the power amplifier circuit and the output control by feedback control, and the power amplifier circuit is not destroyed thereby. The detection method using the conventional coupler almost satisfies the requirements for the second, fourth, and fifth characteristics, but the first miniaturization and the third low insertion loss are sufficient. Did not meet the demands.

  Therefore, the present applicant, as a detection method of the output power of the high frequency power amplifier circuit that does not use a coupler, output power through the capacitive element from the middle of the impedance matching circuit connected to the subsequent stage of the final amplifier stage of the high frequency power amplifier circuit. The present invention was filed earlier (Japanese Patent Application No. 2003-123040).

  The output power detection circuit according to the prior invention is advantageous in terms of downsizing and low insertion loss compared to a detection method using a coupler, but the characteristics of the detection transistor change depending on the temperature and are output from the output power detection circuit. The detected voltage has temperature dependency. As a result, the output level instruction signal from the baseband unit and the detected voltage are compared, and accurate power control by the feedback control loop that controls the bias voltage, that is, gain, of the high-frequency power amplifier circuit according to the potential difference cannot be performed. It has become clear that there is a problem that the output power changes in accordance with the change of.

  An object of the present invention is to prevent a detection output from changing even if a temperature changes and a characteristic of a detection transistor changes in a wireless communication system that performs feedback control by detecting output power of a high-frequency power amplifier circuit. It is an object to provide an output power detection circuit capable of

  Another object of the present invention is to provide a radio communication system that performs feedback control by detecting output power of a high frequency power amplifier circuit, and the high frequency power amplifier circuit is controlled by a control loop even when the temperature changes and the characteristics of the detection transistor change. It is an object of the present invention to provide a high frequency power amplifier circuit capable of controlling the output power of the power source to a desired level and an electronic component for high frequency power amplification using the same.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
That is, an output detection transistor that receives an AC signal taken out from an output section (from the final amplification stage to the output terminal) of the high-frequency power amplifier circuit via a coupling capacitor to a control terminal and flows a current proportional to the output power, and the transistor Output power detection circuit comprising: a bias generation circuit for giving an operating point to the control terminal of the output current; a current mirror circuit for transferring the current flowing through the output detection transistor; and a current-voltage conversion circuit for converting the transferred current into a voltage. In the bias generation circuit, a temperature detection element or a temperature-dependent element having a relatively remarkable temperature is provided, and the bias current passed through the output detection transistor is changed according to the temperature using the temperature characteristics of the element. The mutual conductance of the output detection transistor is made constant even when the temperature changes.

  According to the above-described means, since the mutual conductance of the output detection transistor is made constant even when the temperature changes, the detection voltage output from the output power detection circuit can be made almost constant regardless of the temperature. As a result, the output power of the high-frequency power amplifier circuit can be controlled to a desired level by the control loop even when the temperature changes, and a detection circuit including a coupling capacitor and an output detection transistor is used instead of the coupler. When the circuit that detects the output power is configured to avoid the situation where the characteristics of the output detection transistor change with temperature, the detection output changes, and correct output power control cannot be performed. Miniaturization can be achieved.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, according to the present invention, an output power detection circuit that detects an output power level based on an AC signal input from the output unit of the high-frequency power amplifier circuit via a coupling capacitor is provided, and the detection output of the output power detection circuit In the wireless communication system that performs feedback control of the bias voltage of the high frequency power amplifier circuit based on the detection voltage, the detection voltage becomes constant even if the temperature changes and the characteristics of the detection transistor change. A change in output power can be prevented.

Preferred embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows an embodiment of a high frequency power amplifier (hereinafter referred to as a power module) to which the output power detection circuit of the present invention is applied. In this specification, a plurality of semiconductor chips and discrete components are mounted on an insulating substrate such as a ceramic substrate with printed wiring on the surface or inside, and each component has a predetermined role in the printed wiring or bonding wire. A module that can be handled as a single electronic component is called a module.

  The power module 200 of this embodiment includes a high frequency power amplification unit 210 including a power amplification FET (field effect transistor) that amplifies an input high frequency signal Pin, and an output power detection circuit that detects output power of the high frequency power amplification unit 210. 220, a bias circuit 230 that controls the idle current that flows through each FET by applying a bias voltage to the power amplification FET in each stage of the high-frequency power amplifier 210, and an output power level instruction that is supplied from an external baseband unit It comprises an error amplifier (APC circuit) 250 that compares the signal Vramp with the detection voltage Vdet from the output power detection circuit 220 and supplies a control voltage Vapc according to the potential difference to the bias circuit 230.

  Although not particularly limited, the high-frequency power amplifying unit 210 of this embodiment includes three power amplifying FETs 211, 212, and 213, and the latter FETs 212 and 213 are the drain terminals of the preceding FETs 211 and 212, respectively. The gate terminal is connected to the first and second amplifier circuits as a whole. Further, gate bias voltages Vb1, Vb2, and Vb3 supplied from the bias circuit 230 are applied to the gate terminals of the FETs 211, 212, and 213 in each stage, and an idle current corresponding to these voltages is applied to each FET 211, 212, and 213. It is made to be shed by each.

  The power supply voltage Vdd is applied to the drain terminals of the FETs 211, 212, and 213 at each stage through inductors L1, L2, and L3, respectively. An impedance matching circuit 241 and a DC cut capacitive element C1 are provided between the gate terminal of the first stage FET 211 and the input terminal In, and a high frequency signal Pin is input to the gate terminal of the FET 211 via these circuits and elements. The

  Between the drain terminal of the first-stage FET 211 and the gate terminal of the second-stage FET 212, an impedance matching circuit 242 and a DC-cut capacitive element C2 are connected. An impedance matching circuit 243 and a DC cut capacitive element C3 are connected between the drain terminal of the second stage FET 212 and the gate terminal of the final stage FET 213. The drain terminal of the FET 213 at the final stage is connected to the output terminal OUT via the impedance matching circuit 244 and the capacitive element C4, and a signal Pout obtained by cutting the DC component of the high-frequency input signal Pin and amplifying the AC component is output to the output terminal OUT. Output from OUT.

  The output power detection circuit 220 of this embodiment includes a resistor Ri having one terminal connected to an internal node of an impedance matching circuit 244 provided between the drain terminal of the power amplification EFT 213 at the final stage and the output terminal OUT of the module. And a capacitor Ci connected in series with the resistor, an N-channel MOS transistor Q1 having the other terminal of the capacitor Ci connected to the gate, a P-channel MOS transistor Q2 connected in series with the transistor Q1, the transistor Q2 A current mirror-connected MOS transistor Q3, a current-voltage converting MOS transistor Q4 connected in series with the transistor Q3, and a voltage converted by Q4 is impedance-converted and supplied to the next stage. The buffer circuit 222 and the MOS transistor Q1 are gated. A bias generation circuit 223 that provides a bias voltage, a buffer circuit 224 that impedance-converts the bias voltage generated by the bias generation circuit 223 and supplies it to the next stage, and an output of the buffer circuit 224 is subtracted from an output of the buffer circuit 222 And a subtracting circuit 225 for outputting a voltage. A voltage follower can be used for the buffer circuits 222 and 224.

  The resistance value of the resistor Ri is preferably about 30 to 3 kΩ, and the capacitance value of the capacitor Ci is preferably about 2 to 100 pF. In addition, when taking out the voltage which monitors the output power of the high frequency power amplifier 210 from the impedance matching circuit 244, it is possible to extract only the AC component, so that it is possible to use only the capacitive element. By providing the resistor element Ri between the connection node of the matching circuit and the capacitor Ci before the resistor Ri becomes difficult to see from the power amplification transistor 213 in the final stage, the insertion loss of the coupling capacitor can be reduced. it can.

  In this embodiment, as the power amplification FETs 211 to 213, MOS transistors called LDMOS (Laterally Diffused MOSFET) in which electrodes are diffused in the horizontal direction on the chip are used, and are used for detection of the output power detection circuit 220. The MOS transistor Q1 and the voltage conversion MOS transistor Q4 are configured by LDMOS having the same structure as the power amplification FETs 211 to 213. As a result, even if the characteristics of the power amplification FETs 211 to 213 vary due to manufacturing variations, the transistors Q1 and Q4 of the detection circuit 220 vary in the same manner, thereby improving the accuracy of the detection voltage Vdet.

  In this embodiment, the bias voltage value applied from the bias generation circuit 223 to the gate of the output detection MOS transistor Q1 is close to the threshold voltage of Q1 so that the transistor Q1 can be operated in class B amplification. The voltage value is set. As a result, a current that is proportional to the AC waveform input through the capacitor Ci and half-wave rectified flows through the MOS transistor Q1, and the drain current of Q1 is a DC component proportional to the amplitude of the input AC signal. To be included.

  The drain current Id of the transistor Q1 is transferred to the Q3 side by the current mirror circuit of Q2 and Q3, and is converted into a voltage by the diode-connected transistor Q4. Here, the MOS transistors Q1 and Q4 and Q2 and Q3 are set to have a predetermined size ratio. Thus, for example, if the characteristics (particularly the threshold voltage) of the MOS transistors Q1 and Q2 vary due to manufacturing variations, the characteristics of the MOS transistors Q4 and Q3 that form a pair with the MOS transistors Q1 and Q2 also vary in the same way. As a result, the influence due to the characteristic variation is canceled out, and the output detection voltage (V5) which is not affected by the variation of the MOS transistor appears at the drain terminal of the MOS transistor Q4.

  In this embodiment, the same voltage as the bias voltage (V4) generated by the bias generation circuit 223 and applied to the gate terminal of the output detection MOS transistor Q1 is supplied to the subtraction circuit 225 via the buffer circuit 224. The voltage obtained by subtracting the bias voltage from the output detection voltage is output from the subtraction circuit 225. As a result, the output of the subtraction circuit 225 becomes a detection voltage Vdet proportional to the AC component of pure output power not including the DC component applied by the bias generation circuit 223.

  Further, the output power detection circuit 220 of the present embodiment is provided with a voltage source 227 that provides a DC offset Voff before the buffer 224 that transmits the bias voltage generated by the bias generation circuit 223 to the subtraction circuit 225. The potential of the inverting input terminal of the 225 amplifier is slightly lowered. This is because, as a characteristic of the baseband circuit that supplies the output level instruction signal Vramp, there is a case where the Vramp signal of 0 V cannot be completely output even when the output level is set to “0”. This is because if the voltage Vdet supplied from the power detection circuit 220 to the inverting input terminal of the error amplifier 250 is 0V, the output control voltage Vapc is higher than 0V and the output power Pout may be output. The position where the DC voltage source 227 is provided may be between the buffer 224 and the subtraction circuit 225.

  In the power module 200 of this embodiment, a portion surrounded by a broken line is formed as a semiconductor integrated circuit. That is, each element (excluding inductors L1 to L3 and impedance matching circuit 244) of power amplifier 210, each element of bias circuit 230, each element of output power detection circuit 220 (excluding resistor Ri and capacitor i), DC component Are formed as a semiconductor integrated circuit IC1 on a single semiconductor chip such as single crystal silicon. The semiconductor integrated circuit IC1, the inductors L1 to L3 of the power amplifier 210, and the resistor Ri and the capacitor i of the output power detection circuit 220 are mounted on one ceramic substrate to constitute a power module. . Inductors constituting the impedance matching circuits 241 to 244 can be formed by bonding wires connected between pads of a semiconductor chip or microstrip lines formed on a module substrate.

  As described above, in the power module to which the output power detection method of this embodiment is applied, the module can be reduced in size because the coupler is not used, and the output power detection circuit 220 is replaced with the power amplification unit 210 and the main part of the bias circuit 230 thereof. In addition, since it becomes easy to make a semiconductor integrated circuit, the number of parts can be reduced and the module can be downsized. Although not particularly limited, in this embodiment, the error amplifier (APC circuit) 250 is output on the same semiconductor chip as the power amplifier circuit 210 and the output power detection circuit 220. An external terminal P1 for outputting the detection voltage Vdet detected by the power detection circuit 220 to the outside of the chip is provided. The external terminal P1 can be used, for example, to measure the variation in sensitivity of the output power detection circuit 220 after manufacture or to check the open loop characteristics of the control system.

FIG. 2 shows a specific circuit example of the bias generation circuit 223 in the output power detection circuit 220.
The bias generation circuit 223 of this embodiment includes a constant voltage generation circuit CVG that generates a constant voltage V0 having no temperature dependency based on an external power supply voltage Vcc, and a desired level by dividing the generated constant voltage V0. Series resistors R1 and R2 for generating a reference voltage V2 of the current, a differential amplifier AMP0 in which the voltage V2 generated by the resistors R1 and R2 is applied to the non-inverting input terminal, and a power supply terminal and a ground point in series. A MOS transistor Q5 and a resistor R3 connected to each other, a diode D1 as a temperature detecting element, a MOS transistor Q6 that receives the same gate voltage as that of the MOS transistor Q5 at the gate and flows a current proportional to the drain current of Q5, and the transistor It comprises a MOS transistor Q7 connected in series with Q6. The transistor Q5 and the resistor R3 can be regarded as an output stage of the differential amplifier AMP0.

  The transistor Q7 is a so-called diode-connected transistor whose gate and drain are coupled. The gate of the transistor Q7 is connected to the gate of the output detection MOS transistor Q1 via a resistor R5. A mirror is formed, and a current proportional to the current flowing through Q7 is passed through the output detection MOS transistor Q1, thereby biasing Q1. A capacitor C11 is connected between the gate grounding point of the transistor Q7.

  The capacitor C11 forms a low-pass filter together with the resistor R5 between the gate terminals of the transistors Q7 and Q1, and the AC component of the AC signal ACi input through the capacitor Ci leaks to the gate side of the transistor Q7 and the bias current Ibias. Has the function of preventing fluctuations. The resistance value of the resistor R5 is desirably about 10 to 30 kΩ, and the capacitance value of the capacitor C11 is desirably about 10 to 50 pF. In the embodiment, the diode D1 is provided as the temperature detection element, but a thermistor may be used instead of the diode D1.

  In the bias generation circuit 223 of this embodiment, the potential IA of the connection node between the transistor Q5 and the resistor R3 is fed back to the inverting input terminal of the differential amplifier AMP0, so that the current IA that makes V3 coincide with V2 is MOS. Flowed through transistor Q5. By forming the gate widths of the transistors Q5 and Q6 so as to have a predetermined size ratio, a current proportional to IA flows through Q6, and this current is supplied to the transistor Q7 as a bias current Ibias. Has been.

  In the bias generation circuit 223 of this embodiment, since the diode D1 is connected in series with the resistor R3 between the drain terminal of the transistor Q5 and the ground point, the drain temperature of the transistor Q5 is reduced due to the negative temperature characteristic of the diode D1. The bias current Ibias is changed according to the temperature to the current IA and further to the transistor Q7.

Specifically, the input voltage V2 and the output voltage V3 are equal due to the imaginary short action of the differential amplifier AMP0.
And the forward voltage of the diode D1 is VF, the current IA flowing through the transistor Q5 is expressed by the following equation IA = (V3-VF) / R3
It is represented by

  Here, since V0 has no temperature dependence, as shown in FIG. 3A, V2 and V3 are constant, but the forward voltage VF of the diode D1 has a negative temperature characteristic, so that the resistor R3 and the diode The potential V1 of the connection node with D1 decreases as the temperature increases. Therefore, the differential amplifier AMP0 operates so as to increase the current IA that flows through the MOS transistor Q1 so as to increase the potential V1 of the anode of the diode D1 when the temperature increases and the anode potential V1 decreases. As a result, the bias current Ibias flowing through the transistor Q7 increases as the temperature increases, as shown in FIG. 3B, and the gate voltage Vgs1 of the output detection MOS transistor Q1 corresponding to this increases as shown in FIG. As shown in A), the temperature increases as the temperature increases.

  In this embodiment, the transistors Q5 and Q6 have the same size, so that the currents IA and Ibias have the same current value. However, the size ratio of Q5 and Q6 should be set appropriately. Thus, a bias current Ibias having an arbitrary magnitude having a positive temperature characteristic can be supplied to the transistor Q7. The constant voltage generation circuit CVG can be composed of a reference voltage circuit such as a band gap reference circuit and a voltage follower. The constant voltage generated by the constant voltage generation circuit CVG can be used as the power supply voltage of the detection circuit 221 including the output detection transistor Q1 instead of the external power supply voltage Vcc.

  In the case of the bias generation circuit 223 of the embodiment, the resistor R3 in series with the diode D1 having the negative temperature characteristic generally has a positive temperature characteristic in the case of an on-chip element, so that the bias utilizing the temperature characteristic of the diode D1 is used. The effect of current control is reduced. Therefore, an external resistor element may be used as the resistor R3 instead of the on-chip element. Since resistance elements made of discrete components are provided that have almost no temperature characteristics, it is easy to effectively exhibit the effects of the present invention by using the resistance elements. However, since the temperature characteristic of the diode D1 is generally more prominent than the temperature characteristic of the resistor, an on-chip element may be used as the resistor R3.

Next, the characteristics and operation of the detection circuit comprising the output detection MOS transistor Q1, the MOS transistors Q2 and Q3 constituting the current mirror circuit, and the current-voltage conversion MOS transistor Q4 will be described.
In the output power detection circuit 220 of this embodiment, as described above, the bias generation circuit 223 causes the gate voltage Vgs1 of the output detection MOS transistor Q1 to increase as the temperature increases, as shown in FIG. Therefore, even if the DC level of the AC signal ACi input to the gate is the same, the drain current Ids flowing through the MOS transistor Q1 increases as the temperature increases. On the other hand, the LDMOS used for the transistor Q1 generally has a higher threshold voltage as the temperature becomes higher, and the drain current decreases as the temperature becomes higher if the gate voltage is constant. That is, the mutual conductance gm (= ΔIds / ΔVgs) of the MOS transistor has a negative temperature characteristic.

  By the way, in the above-mentioned prior application (Japanese Patent Application No. 2003-123040), the differential amplifier AMP0 and the transistors Q5 and Q6 shown in FIG. 2 are not provided, and instead of Q6, a resistance element is connected to the drain terminal of the transistor Q7 and the power source. Since it is connected to the voltage terminal, the bias current Ibias and the gate voltage Vgs of the output detection MOS transistor Q1 are substantially constant even when the temperature changes. Therefore, as indicated by the broken line B in FIG. 4B, the mutual conductance gm (= ΔIds / ΔVgs) of the output detection MOS transistor Q1 decreases as the temperature increases.

  On the other hand, in the output power detection circuit 220 of the present embodiment, the gate voltage Vgs1 of the output detection MOS transistor Q1 is increased by the bias generation circuit 223 as described above, as shown in FIG. As shown in FIG. 4B, as indicated by the solid line A, the gm (= ΔIds / ΔVgs) of the MOS transistor Q1 can be made substantially constant with respect to the temperature.

  By the way, as described above, when the gm (= ΔIds / ΔVgs) of the MOS transistor Q1 is substantially constant with respect to the temperature, the drain current Ids flowing through the MOS transistor Q1 is increased as the temperature is increased. Therefore, even if the detection voltage is constant, the voltage (the drain voltage of Q4) V5 input to the subtraction circuit 225 becomes higher as the temperature becomes higher, as shown in FIG. However, in the output power detection circuit 220 of the present embodiment, the bias voltage Vbias having the same level as the voltage generated by the bias generation circuit 223 and applied to the gate of the output detection MOS transistor Q1 is supplied via the buffer 224 to the subtraction circuit 225. The bias voltage Vbias itself becomes higher as the temperature becomes higher as shown in FIG. 5B. Therefore, the difference is “0”, and even if the temperature changes, the detection voltage Vdet of the output power detection circuit 220 becomes substantially constant as shown in FIG. As a result, when the detected voltage Vdet is supplied to the error amplifier 250 to control the output power of the high-frequency power amplifier circuit 210, fluctuations in the output power with respect to temperature changes can be suppressed.

  FIG. 6 shows the relationship between the output power Pout and the output power detection voltage Vdet when the temperature changes in the power module using the above-mentioned prior invention (Japanese Patent Application No. 2003-123040) and the output power detection circuit 220 of the embodiment. The result of having been investigated by simulation is shown. 6A shows the relationship between the output power Pout and the output power detection voltage Vdet in the power module using the output power detection circuit 220 of this embodiment, and FIG. 6B shows the output power detection circuit of the prior invention. The relationship between the output power Pout and the detected voltage Vdet in the power module is shown. From FIG. 6, the power module using the output power detection circuit 220 of the present embodiment and the detected power Vdet when the temperature changes compared to the power module using the output power detection circuit of the prior invention. It can be seen that the fluctuation of the correlation with is small.

  FIG. 7 shows a schematic configuration of a system capable of wireless communication using two communication systems, GSM and DCS, as an example of an effective wireless communication system to which the power module of the embodiment is applied.

  In FIG. 7, ANT is an antenna for transmitting and receiving signal radio waves, 100 is a modulation / demodulation circuit capable of performing GMSK modulation and demodulation in GSM and DCS systems, and I and Q signals are generated based on transmission data (baseband signals). A high-frequency signal processing circuit (baseband circuit) 110 having a circuit for processing I and Q signals extracted from received signals, low noise amplifiers LNA1 and LNA2 for amplifying received signals, and the like are formed on one semiconductor chip. A high-frequency signal processing semiconductor integrated circuit (baseband IC), bandpass filters BPF1 and BPF2 for removing harmonic components from a transmission signal, bandpass filters BPF3 and BPF4 for removing unnecessary waves from a reception signal, etc. in one package A mounted electronic device (hereinafter referred to as an RF device)Tx-MIX1 and Tx-MIX2 are mixers for up-converting GSM and DCS transmission signals, and Rx-MIX1 and Rx-MIX2 are mixers for down-converting GSM and DCS reception signals.

  In FIG. 7, reference numeral 200 denotes the power module of the above-described embodiment that amplifies the high-frequency signal supplied from the baseband IC 100, and 300 denotes filters LPF 1, LPF 2, and GSM signals that remove noise such as harmonics included in the transmission signal. And a duplexer DPX1, DPX2 that synthesizes and separates DCS signals, a transmission / reception changeover switch T / R-SW, and the like.

  As shown in FIG. 7, in this embodiment, a mode selection signal VBAND indicating GSM or DCS is supplied from the baseband IC 100 to the bias circuit 230, and the bias circuit 230 is based on the control signal VBAND. A bias current corresponding to the mode is generated and supplied to one of the power amplifiers 210a and 210b. The output level instruction signal Vramp is supplied from the baseband IC 100 to the APC circuit (error amplifier) 250 in the power module 200, and the APC circuit (error amplifier) 250 detects from the output level instruction signal Vramp and the output power detection circuit 220. The voltage Vdet is compared to generate an output control signal Vapc for the bias circuit 230. The bias circuit 230 controls the gains of the power amplifiers 210a and 210b according to the output control signal Vapc, and the power amplifiers 210a and 210b according to this. The output power is controlled to change.

  Although not shown in FIG. 7, in addition to the devices and modules described above, a microprocessor (not shown) that generates an output level instruction signal that is a basis of a control signal for the RF device 100 and a power control signal PCS to control the entire system ( CPU) may be provided.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the embodiment, a series resistor Ri and a capacitor Ci are connected in the middle of the microstrip line in the impedance matching circuit 244 to transmit the AC component of the output power to the output power detection circuit 220 to detect the magnitude of the output power. In this example, the output power is detected from the drain terminal of the FET 213 in the final amplification stage, or from the output terminal OUT of the module or from both the drain terminal and the output terminal OUT of the FET 213 via a capacitor, a resistor, and the like. A modification in which an AC signal is input to the gate of the detection MOS transistor Q1 of the circuit 220 to detect the magnitude of the output power is also conceivable. Even in such a case, the output power detection circuit 220 is provided with a temperature detection element and the bias generation circuit 223 capable of changing the bias state of the output detection MOS transistor Q1 according to the temperature is applied. can do.

  Furthermore, in the high-frequency power amplifier circuit of the above embodiment, three stages of power amplifier FETs are connected, but a two-stage structure or a structure of four or more stages may be used. In the embodiment, the LDMOS is used as the power amplification elements 211 to 213. However, a MOSFET, a bipolar transistor, a GaAs MESFET, a heterojunction bipolar transistor (HBT), a HEMT ( Other transistors such as High Electron Mobility Transistor) may be used. However, in that case, it is desirable that the detection transistor Q1 and the current-voltage conversion transistor Q2 are also composed of elements having the same structure as the power amplification elements 211 to 213.

  Further, in the above embodiment, the error amplifier (APC circuit) that generates the output control voltage Vapc to the bias circuit 230 by comparing the output level instruction signal Vramp from the baseband unit and the detection voltage Vdet from the output power detection circuit 220. Although the case where 250 is formed on the same semiconductor chip as the power amplifier circuit 210 and the output power detection circuit 220 has been described, the error amplifier (APC circuit) 250 may be formed on a separate semiconductor chip.

  A variable gain amplifier that supplies the detection voltage Vdet from the output power detection circuit 220 to the baseband unit from the external terminal P1 and amplifies the transmission signal by an error amplifier (APC circuit) 250 provided on the baseband unit side. It can be used to generate a control voltage Vapc that controls the gain of. Such a method is effective when applied to a system in which, for example, the bias voltage, that is, the gain of the power amplifier circuit 210 is fixed and the amplitude of the input signal Pin is amplified according to the required output level.

  In the above description, when the invention made mainly by the present inventor is applied to a power module constituting a dual-mode wireless communication system capable of transmission / reception by two communication systems, GSM and DCS, which are the fields of use behind it. However, the present invention is not limited to this, and a multi-mode mobile phone or mobile device capable of transmission / reception by other communication methods, or three or more communication methods such as GSM, DCS, and PCS (Personal Communications System). It can be used for a power module constituting a wireless communication system such as a telephone or a high frequency power amplifier circuit and a power module for a wireless LAN.

1 is a circuit configuration diagram showing an embodiment of an output power detection circuit according to the present invention and a high-frequency power amplifier (power module) to which the output power detection circuit is applied. It is a circuit block diagram which shows the specific circuit example of an output electric power detection circuit and a bias generation circuit. (A) is a graph showing the relationship between the temperature and the internal voltages V1, V2, V3 in the bias generation circuit of the embodiment, and (B) is a graph showing the relationship between the temperature and the bias current Ibias. (A) is a graph showing the relationship between the temperature and the gate voltage Vgs of the output detection transistor in the output power detection circuit of the embodiment, and (B) shows the relationship between the temperature and gm (mutual conductance) of the output detection transistor. It is a graph. (A) and (B) are graphs showing the relationship between the temperature in the output power detection circuit of the embodiment and the input voltages V4 and V5 of the subtraction circuit, and (C) is a graph showing the relationship between the temperature and the detection voltage Vdet. . (A) is a graph showing the relationship between the output power Pout and the output power detection voltage Vdet in a power module using the output power detection circuit 220 of this embodiment, and (B) is the output power detection circuit of the prior invention. It is a graph which shows the relationship between the output electric power Pout in a power module, and the output electric power detection voltage Vdet. It is a block diagram which shows the schematic structure of the system which can perform radio | wireless communication of the two communication systems of GSM and DCS to which the power module of this invention is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 RF device 110 Baseband circuit 200 Power module 210, 210a, 210b High frequency power amplification circuit 211, 212, 213 Power amplification FET
220 Output power detection circuit 221 Detection unit 222, 224 Buffer circuit 223 Bias generation circuit 225 Subtraction circuit 227 DC voltage source 230 Bias circuit 241 to 244 Impedance matching circuit 250 Error amplifier (APC circuit)
300 Front-end module

Claims (5)

A high-frequency power amplifying circuit comprising: a power amplifier circuit that amplifies a high-frequency signal; and an output power detection circuit that detects a level of output power based on an AC signal input from the output section of the power amplifier circuit via a coupling capacitor A semiconductor integrated circuit,
The output power detection circuit includes an output detection transistor that receives an AC signal extracted via the coupling capacitor at a control terminal and supplies a current proportional to the output power, and a bias generation circuit that provides an operating point to the control terminal of the transistor And a current mirror circuit that transfers the current flowing through the output detection transistor, and a current-voltage conversion circuit that converts the transferred current into a voltage,
The bias generation circuit includes a temperature detection element, and flows to the output detection transistor so that the mutual conductance of the output detection transistor becomes constant even when the temperature changes using the temperature characteristics of the temperature detection element. A semiconductor integrated circuit for high-frequency power amplification, characterized by changing a bias current.   The bias generation circuit includes a first transistor connected to the output detection transistor in a current mirror connection, a differential amplifier having a constant voltage applied to a first input terminal, and an output voltage of the differential amplifier applied to a control terminal. A second transistor connected in series with the temperature detection element; a third transistor connected in series with the first transistor by applying a voltage equal to the control voltage of the second transistor to the control terminal; 2. The semiconductor integrated circuit for high frequency power amplification according to claim 1, wherein a drain voltage or an emitter voltage of two transistors is fed back to a second input terminal of the differential amplifier.   3. The semiconductor integrated circuit for high frequency power amplification according to claim 2, wherein a low pass filter is provided between a control terminal of the output detection transistor and a control terminal of the first transistor.   A subtraction circuit that outputs a voltage corresponding to a difference between the voltage converted by the current-voltage conversion transistor and the voltage applied to the output detection transistor by the bias generation circuit as a detection signal. The high-frequency power amplification semiconductor integrated circuit according to any one of claims 1 to 3.   5. The high frequency power amplification semiconductor integrated circuit according to claim 1, wherein the amplification transistor and the output detection transistor at the final stage of the power amplification circuit are MOS transistors having the same structure.

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