JP2006270670A - High frequency power amplifier circuit and electronic component for high frequency power amplification - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an RF power module capable of improving rising characteristics by avoiding sudden rising of output power at a low level in transmission start, and outputting sufficient power by enlarging a rate of change of the output power at high level. <P>SOLUTION: The RF power module comprises power amplification transistors (Qa1, 2, 3) and bias transistors (Qb1, 2, 3) current mirror connected with the power amplification transistors, includes a circuit for giving a bias to the power amplification transistors by causing an output power control current to flow to the bias transistors and an output power control circuit (230) for feeding a current to the bias circuit based on an output power control voltage (Vapc), and amplifies a high frequency transmission signal. For the bias circuit, a current with square characteristics is generated by receiving the output power control voltage so as to flow to the bias transistors. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for improving power start-up characteristics at the start of transmission in a high-frequency power amplification circuit and a high-frequency power amplification electronic component (RF power module) incorporating the high-frequency power amplification circuit, and for example, RF used in a GSM mobile phone The present invention relates to a technology effective when applied to a power module.

  A transmission output unit of a wireless communication device (mobile communication device) such as a cellular phone has a high frequency power amplifier circuit (PA) using a transistor such as a MOSFET (Metal Oxide Semiconductor Field-Effect-Transistor) or a GaAs-MESFET as an amplifying element. Incorporates a high frequency power amplification electronic component (hereinafter referred to as an RF power module).

  In general, a mobile phone makes a call by changing output power (transmission power) so as to adapt to the surrounding environment according to the power level instruction information sent from the base station, and causes interference with other mobile phones. The system is configured so that it does not occur. For example, in a GSM (Global System for Mobile Communication) type mobile phone, a control voltage Vapc for controlling power by comparing an output detection signal and an output level instruction signal Vramp from a baseband circuit in an APC (Automatic Power Control) circuit. And the gain control of the amplification stage of the high frequency power amplifier circuit of the transmission output unit is performed by the bias circuit so that the output power required for the call is obtained by the control voltage Vapc.

Conventionally, in a high-frequency power amplifier circuit having a multi-stage configuration in which a plurality of amplifying transistors are cascade-connected, each output power control voltage Vapc generated by an APC circuit is resistance-divided using a bias circuit composed of a resistor divider circuit. There is one configured to generate a bias voltage of an amplification transistor in an amplification stage (see, for example, Patent Document 1). In addition, a bias current proportional to the output voltage Vapc of the APC circuit is generated, and an amplifying transistor in each amplification stage and a biasing transistor connected in a current mirror are provided, and a bias current is supplied to the amplifying transistor. Some are configured to apply a bias (hereinafter referred to as a current mirror system) (see, for example, Patent Document 2).
JP 2000-151310 A JP 2003-17954 A

  In the technique of applying a bias to the amplifying transistor by the current mirror method, the technique is used to generate the bias voltage of the amplifying transistor in each amplifying stage by dividing the output power control voltage Vapc generated in the APC circuit by resistance. Compared with this, there is an advantage that a deviation in characteristics due to manufacturing variations of the amplifying transistor can be reduced.

  However, in the current mirror type bias technology, even if a current proportional to the output power control voltage Vapc is supplied to the biasing transistor, the voltage converted by the transistor does not become higher than the threshold voltage of the amplifying transistor. , Idle current does not flow. In other words, when the voltage between the gate and the source of the biasing transistor exceeds the threshold voltage, an idle current suddenly starts to flow through the amplifying transistor. This is indicated by the solid line B in FIG. As can be seen from the solid line B in FIG. 2, the idle current Iidle suddenly increases when the output power control voltage Vapc is in the vicinity of 0.8V.

  Therefore, in a GSM mobile phone using a high-frequency power amplifier to which such a bias method is applied, when the output level instruction signal Vramp supplied from the baseband circuit is raised to the transmission level at the start of transmission, the high-frequency power amplifier circuit Suddenly get up from where there is output power. As a result, the output power is caught by a predetermined time mask, and the spectrum characteristic of the output signal deviates from the range defined by the GSM standard. Further, it has been found that there is a problem that the rate of change of the output power in the region where the output power control voltage Vapc is high is small, and it is difficult to obtain a desired power at the time of high output.

  The invention disclosed in the above-mentioned Patent Document 2 is similar in that a bias current that changes nonlinearly as a whole with respect to the output power control voltage Vapc flows in a current mirror type power amplifier. Yes. However, in the invention disclosed in Patent Document 2, a bias current is generated by synthesizing two or more currents having different characteristics, and the first, second and third stage amplifying transistors have different characteristics. A bias current is allowed to flow. On the other hand, in the present invention, a bias current that changes in a square characteristic with respect to the output power control voltage Vapc is generated, and a bias current having the same characteristic is supplied to the first, second, and third stage amplifying transistors. This is clearly different from the invention of Patent Document 2.

  An object of the present invention is to provide a high-frequency power amplifier circuit and a high-frequency power amplifier electronic component (RF power module) that can avoid a sudden rise in output power at the start of transmission.

Another object of the present invention is to change the rate of change of the output power with respect to the output power control voltage, thereby reducing the rate of change of the output power in the region where the output power control voltage is low, and the region where the output power control voltage is low. The high frequency power amplifier circuit and the high frequency power amplifier electronic component (which can output the desired power by increasing the rate of change of the output power in the region where the output power control voltage is high) RF power module).
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
That is, a bias circuit that includes a power amplifying transistor and a bias transistor that is connected to the power amplifying transistor and a current mirror so as to bias the power amplifying transistor by supplying a current proportional to the output power control voltage to the biasing transistor And an output power control circuit for supplying an output power control voltage to the bias circuit based on a signal indicating the level of the output power, and an output power control in an electronic component for amplifying a high frequency transmission signal A current having a square characteristic is generated based on the voltage and is caused to flow through the biasing transistor.

  According to the above-described means, since the bias current flowing through the bias transistor changes with a square characteristic with respect to the output power control voltage, it is avoided that the output power suddenly rises at a certain level at the start of transmission. it can. Also, by changing the rate of change of the output power with respect to the output power control voltage, the rate of change of the output power in the region where the output power control voltage is low is reduced, and the output power is controlled in the region where the output power control voltage is low In addition, it is possible to increase the rate of change of the output power in a region where the output power control voltage is high and to obtain a desired power.

  Here, as a circuit that generates a current having a square characteristic, for example, a current generation including an operational amplifier circuit that receives an output power control voltage and a voltage-current conversion transistor that is driven by the output of the operational amplifier circuit. A square root circuit is provided on the feedback path from the output of the operational amplifier circuit to the input of the circuit so that a current having a square characteristic can be output by feeding back the square root of the output to the operational amplifier circuit. There is a circuit to do. Since the square root circuit can be designed by utilizing the saturation drain current characteristic of the MOSFET, the design is easier than when the square circuit is used.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, according to the present invention, it is possible to avoid a sudden rise in output power in a region where the output power control voltage is low, such as at the start of transmission, and to improve the rise characteristic of the output power. A high-frequency power amplifier circuit and a high-frequency power amplifier electronic component (RF power module) that can increase the rate of change of output power in a region where the control voltage is high and output desired power can be realized.

Preferred embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows a schematic configuration of an embodiment of a high-frequency power amplifier circuit according to the present invention. In FIG. 1, what is indicated by reference numeral 210 is a high-frequency power amplifier circuit using a transistor such as an FET (Field Effect Transistor) as an amplifier element. As shown in FIG. 1, the high-frequency power amplifier circuit 210 of this embodiment includes three amplifying transistors Qa1, Qa2, and Qa3, of which the rear-stage transistors Qa2 and Qa3 are the front-stage amplifying transistors, respectively. A gate terminal is connected to the drain terminals of Qa1 and Qa2, and the circuit is configured as a three-stage amplifier circuit as a whole. As the amplifying transistors Qa1 to Qa3, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used in this embodiment, but bipolar transistors, GaAs MESFETs, heterojunction bipolar transistors (HBTs), and HEMTs (High Electron Mobility Transistors). It is also possible to use other transistors.

  The power supply voltage Vdd is applied to the drain terminals of the amplification transistors Qa1, Qa2, and Qa3 at each stage through inductors L1, L2, and L3, respectively. A capacitive element C1 that cuts off DC voltage is provided between the gate terminal of the first stage amplification transistor Qa1 and the input terminal In, and a high-frequency input signal Pin is supplied to the gate terminal of the amplification transistor Qa1 via the capacity C1. Entered.

  A DC-cut capacitive element C2 is connected between the drain terminal of the first amplification transistor Qa1 and the gate terminal of the second amplification transistor Qa2. A DC-cut capacitive element C3 is connected between the drain terminal of the second-stage amplification transistor Qa2 and the gate terminal of the final-stage amplification transistor Qa3. The drain terminal of the amplification transistor Qa3 at the final stage is connected to the output terminal OUT through the capacitive element C4, and the signal Pout obtained by cutting the DC component of the high-frequency input signal Pin and amplifying the AC component is output.

  In addition, bias transistors Qb1, Qb2, and Qb3 that are current mirror connected to the amplifying transistors Qa1, Qa2, and Qa3 are provided, and a bias supplied from a bias circuit 230 that generates a bias current according to the output power control voltage Vapc is provided. Current Ib1, Ib2, and Ib3 are configured to flow. Bias transistors Qb1, Qb2, and Qb3 are each formed of an N-channel MOSFET.

  The bias transistors Qb1, Qb2, and Qb3 have a so-called diode connection in which the gate and drain are coupled, convert the bias current into a voltage, and the voltage is applied to the gate terminals of the amplification transistors Qa1, Qa2, and Qa3. . As a result, the idle currents Iidle1, Iidle2, and Iidle3 flow through the amplifying transistors Qa1, Qa2, and Qa3 according to the size ratio with the biasing transistors Qb1, Qb2, and Qb3. Idle currents Iidle1, Iidle2, and Iidle3 are made larger than bias currents Ib1, Ib2, and Ib3. In general, the idle current is Iidle1 <Iidle2 <Iidle3, and the largest idle current flows through the amplification transistor Qa3 in the final stage.

  The bias circuit 230 includes an operational amplifier circuit (hereinafter referred to as an operational amplifier) AMP1 to which the output power control voltage Vapc is applied to the inverting input terminal, and a P-channel MOSFET Q30 to which the output of the operational amplifier AMP1 is applied to the gate terminal. Q33, and a square root circuit 232 and a resistor R30 connected between the drain terminal of Q30 and the ground point. The square root circuit 232 receives the drain current Iout1 of the MOSFET Q30 and outputs a current Iout2 obtained by square root conversion. This current Iout2 is passed through the resistor R30 and converted into a voltage, and the voltage is fed back to the non-inverting input terminal of the operational amplifier AMP1.

Then, the operational amplifier AMP1 outputs a voltage for driving the MOSFET Q30 so that the feedback voltage matches the output power control voltage Vapc of the inverting input terminal, that is, Vapc = Iout2 × R30. Here, since Iout2 is an output of the square root circuit 232 and an input of the square root circuit 232 is Iout1, it is expressed by Iout2 = √Iout1. As a result, Iout1 = (Vapc / R30) ² , and the drain of the MOSFET Q30 and the output of the operational amplifier AMP1 applied to the gate terminal in the same manner as the MOSFET Q30 are drains proportional to the square of the output power control voltage Vapc. Current flows.

  The bias transistors Qb1, Qb2 and Qb3 are connected in series to the MOSFETs Q31 to Q33, respectively. As a result, bias currents Ib1, Ib2, and Ib3 proportional to the square of Vapc are passed through the bias transistors Qb1, Qb2, and Qb3, and the amplifying transistors Qa1, Qa2, and Qa3 connected to these transistors in a current mirror connection also have Vapc. Idle currents Iidle1, Iidle2, and Iidle3 that are proportional to the square of. Therefore, the bias circuit 230 can be regarded as a square circuit. Further, a circuit including the operational amplifier AMP1, the square root circuit 232, and the MOSFETs Q30 to Q33 can be regarded as a current generation circuit that generates a bias current.

  FIG. 2 shows the relationship between the output power control voltage Vapc and the idle current Iidle3 of the amplifying transistor Qa3 in the high-frequency power amplifier circuit to which this embodiment is applied, and Vapc without providing the square root circuit 232 in the bias circuit 230. The result of investigating the relationship with the idle current Iidle3 of the amplifying transistor Qa3 when a directly proportional bias current Ib3 is passed through the biasing transistor by simulation is shown.

  In FIG. 2, a solid line A (◯ mark) is a characteristic of a circuit to which this embodiment is applied, and a solid line B (（mark) is a characteristic of a circuit to which this embodiment is not applied. As shown in FIG. 2, in the circuit to which this embodiment is not applied, the idle current Iidle suddenly increases in the vicinity of Vapc of 0.8 V. However, in the circuit to which this embodiment is applied, the idle current increases as Vapc increases. It can be seen that Iidle gradually increases. Thereby, in the high frequency power amplifier circuit to which the present embodiment is applied, the rate of change of the idle current Iidle3 in the region where Vapc is small, that is, the power is low, and the rate of change of the idle current Iidle3 in the region where Vapc is large, that is, the power is high. growing.

  3 shows the relationship between the output power control voltage Vapc and the output power Pout in the high-frequency power amplifier circuit to which this embodiment is applied, and the bias that is directly proportional to Vapc without providing the square root circuit 232 in the bias circuit 230. The result of having investigated by simulation the relationship between Vapc and the output electric power Pout when an electric current is sent through the transistors Qb1, Qb2, and Qb3 for bias is shown.

  In FIG. 3, a solid line A (◯ mark) is a characteristic of a circuit to which this embodiment is applied, and a solid line B (（mark) is a characteristic of a circuit to which this embodiment is not applied. As shown in FIG. 3, in the case of the circuit to which the present embodiment is not applied, the output power Pout hardly increases when Vapc is 0.75 V or less and is −80 dBm or less, and the output power Pout is within the range of Vapc from 0.75 V to 1.0 V. Is rising rapidly. On the other hand, when the present embodiment is applied, the rate of change of the output power Pout in the range of Vapc from 0.75 V to 1.0 V becomes small, and Pout changes almost linearly up to 1.5 V, and the controllability of the output power is improved. It has improved. Further, it can be seen that the output power Pout in the region where Vapc is 1.5 V or higher is higher in the circuit to which the embodiment is applied, and is improved.

FIG. 4 shows a specific circuit example of the square root circuit 232.
The square root circuit 232 of this embodiment includes a first current mirror circuit 31 composed of an N-channel MOSFET for proportionally reducing the current Iout1 input from the MOSFET Q30 driven by the output of the operational amplifier AMP1, and the first current mirror. A second current mirror circuit 32 comprising an N-channel MOSFET for further proportionally reducing the current at the transfer destination of the circuit 31, and a third current mirror circuit 33 comprising a P-channel MOSFET for proportionally reducing the reference current Iref from the constant current source 38; The fourth current mirror circuit 34 composed of a P-channel MOSFET for further proportionally reducing the transfer destination current of the third current mirror circuit 33, and the square of the input current Iout1 using the current generated by these current mirror circuits. An arithmetic circuit 35 for generating a current including a term corresponding to the root; And a Ass circuit 36 and a current combining circuit 37..

  The bias circuit 36 is connected in series with the MOSFET M4 that constitutes the arithmetic circuit 35, the MOSFET M5 and M5 that are supplied with the same current as the M4, and the MOSFET M6 and M6 that are connected in series with the current mirror connection MOSFET M7. When the drain voltage of M4 is applied to the gate of the MOSFET M7, the operating points of the MOSFETs M2 and M4 constituting the arithmetic circuit 35 are given. The current synthesis circuit 37 uses the currents generated by the current mirror circuits 32 and 34 to generate an extra term other than the square root term from the current including the term corresponding to the square root generated by the arithmetic circuit 35. Are subtracted from each other to output a current proportional to the square root of the input current Iout1.

  Each of the current mirror circuits 31 to 34 generates a current that is proportionally reduced by setting a size ratio (ratio of gate widths) of the paired MOSFETs that are commonly connected to each other to a gate to a predetermined value. Specifically, the first current mirror circuit 31 is 1/10, the second current mirror circuit 32 is 1/3 and 1/12, the third current mirror circuit 33 is 1/8, and the fourth current mirror. In the circuit 34, the size ratio (gate width ratio) of the paired MOSFETs is set to a predetermined value so as to generate a current reduced to 1/4 and 1/16, respectively.

  When 1/30 of the current Iout1 input to the square root circuit 232 is Is and 1/32 of the reference current Iref from the constant current source 38 is Ir, the first current mirror circuit 31 and the third current circuit 31 Currents flowing to the transfer destination of the current mirror circuit 33 are 3Is and 4Ir, respectively, and currents flowing from the transfer destinations of the second current mirror circuit 32 and the fourth current mirror circuit 34 to the arithmetic circuit 35 are Is and Ir, respectively.

  The arithmetic circuit 35 has a MOSFET M2 in which the current Is supplied from the second current mirror circuit 32 flows between the drain and source, and the drain voltage of the MOSFET M2 is applied to the gate terminal and supplied from the fourth current mirror circuit 34. Is applied between the drain and source of the MOSFET M3, the MOSFET M3 in which the drain voltage of the MOSFET M2 is applied to the gate terminal to pass the current of the transfer source of the current synthesis circuit 37, and the source side of the MOSFET M3 It is comprised from MOSFET M1 connected in series with M3. The MOSFET M1 has a gate and a drain combined to act as a diode. The MOSFETs M1 to M4 are designed to have the same size (gate width W and gate length L), and are manufactured at the same time in the same process so as to have the same threshold voltage Vth. At the same time, the power supply voltage Vdd is set so that the MOSFETs M1 to M4 operate in the saturation region.

  Here, the gate-source voltages of the MOSFETs M1, M2, M3, and M4 are represented by VGS1, VGS2, VGS3, and VGS4, and the drain-source voltages are represented by VDS1, VDS2, VDS3, and VDS4, and attention is paid to the node N1 of the arithmetic circuit 35. Then, the potential Vn1 of the node N1 is determined by Vn1 = VGS1 + VGS3 from the MOSFETs M1 and M3, and determined by Vn1 = VGS2 + VGS4 from the MOSFETs M2 and M4.

Since the MOSFETs M1 and M3 are connected in series, the flowing currents are equal (Iout in the figure), the current Is from the current mirror circuit 32 flows to the MOSFET M2, and the current Ir flows from the current mirror circuit 34 to the MOSFET M4. Therefore, the above equation can be expressed as the following equation (1) from the equation representing the drain current characteristic in the saturation region of the MOSFET.
2 [Vth + √ {(2 / β) · (L / W) / (1 + λ · VDS)} · √Iout]
= Vth + √ {(2 / β) · (L / W) / (1 + λ · VDS)} · √Is
+ Vth + √ {(2 / β) · (L / W) / (1 + λ · VDS)} · √Ir (1)

In the above equation, the element sizes L / W of the MOSFETs M1 to M4 are equal, and λ · VDS is negligibly small for “1” due to the element characteristics of the MOSFETs. / 2 (2)
Can be organized. And when this equation is transformed,
Iout = (Is + Ir) / 4 + √ (Is · Ir) / 2 (3)
Thus, although an extra term of (Is + Ir) / 4 is included, it can be seen that the current Iout flowing through the MOSFET M3 is represented by the square root of the detection current Is.

  Further, in the circuit of the embodiment of FIG. 4, a current synthesis circuit 37 comprising current mirror MOSFETs M8 and M9 connected in common to each other is provided, and this circuit has a current flowing through the MOSFET M8 that is the transfer source of the current mirror. In addition, the sum of the Is / 4 current supplied from the second current mirror circuit 32 and the Ir / 4 current supplied from the fourth current mirror circuit 34 is output as Iout. MOSFETs M8 and M9 are designed so that the size ratio is 1:10. As a result, a current 10 times as large as a current smaller than Iout by (Is + Ir) / 4 flows through MOSFET M9 connected to MOSFET M8 in a current mirror connection.

  Here, it can be seen that the current (Is + Ir) / 4 added by the current synthesis circuit 37 corresponds to the first term of the above equation (3). Therefore, the current flowing through the MOSFET M9 is 10 times the second term of the above formula (3), that is, 10 · √ (Is · Ir) / 2 = 5 · √ (Is · Ir). In the circuit of the embodiment of FIG. 4, this current is output. Therefore, the output current of this circuit is a current proportional to the square root of Is.

  On the other hand, as described above, the current Is is 1/30 of the input current Iout1. Therefore, the output current Iout of the circuit of FIG. 4 is a current proportional to the square root of the input current Iout1. This current is passed through the resistor R30 and converted into a voltage, and the converted voltage is fed back to the operational amplifier AMP1.

  The square root circuit of this embodiment does not include a temperature coefficient in equation (3), and the output current has no temperature dependence. Therefore, if the reference current Iref is constant, the square root circuit operates even if the ambient temperature changes. The characteristics are constant and conversion with high stability is possible. As a constant current source in which the current is constant even if the temperature changes, a constant current circuit that is temperature compensated by combining an element having a positive temperature characteristic and an element having a negative temperature characteristic is known. By using such a constant current circuit having no temperature dependence as the current source 38, the reference current Iref suitable for the square root circuit of this embodiment can be easily generated and provided.

  In the square root circuit of the embodiment of FIG. 4, the first current mirror circuit 31 and the third current mirror circuit 33 each use a circuit in which MOSFET pairs that are current mirror connected are vertically stacked. However, this is to reduce the dependency of the generated current on the power supply voltage. When a highly stable voltage is supplied as the operating voltage Vdd of the square root circuit 232, each current mirror on the P-MOS side is provided. A single-stage current mirror circuit similar to the circuits 32 and 34 can be formed.

FIG. 5 shows an embodiment of a high frequency power amplifier (hereinafter referred to as a power module) to which the high frequency power amplifier circuit of the embodiment of FIG. 1 is applied.
The power module 200 of this embodiment includes a high frequency power amplifier 210 including the amplification transistors Qa1 to Qa3 for amplifying an input high frequency signal Pin, and an output power Pout of the high frequency power amplifier 210 to detect the output power control voltage Vapc. And an output power control circuit 220 that generates the signal and supplies it to the high frequency power amplifier 210. In FIG. 5, a high frequency power amplifier circuit including the amplification transistors Qa1 to Qa3 of FIG. 1, a bias transistor Qb1, Qb2, Qb3, and a circuit including the bias circuit 230 are shown as a high frequency power amplifier 210.

  The high frequency power amplifier circuit 210 shown in FIG. 1 and the output power control circuit 220 shown in FIG. 5 are configured as a module by one or a plurality of semiconductor chips (ICs) and external elements such as capacitors. In this specification, a plurality of semiconductor chips and discrete components are mounted on an insulating substrate such as a ceramic substrate with printed wiring on the surface or inside, and each component plays a predetermined role in the printed wiring or bonding wire. A module that can be handled as one electronic component is called a module.

  The output power control circuit 220 includes a detection circuit (detection circuit) 221 that detects output power using a coupler and outputs a current proportional to the output power, a current-voltage conversion circuit 222 that converts the output current into voltage, and the converted detection. An error amplifier 223 that compares the voltage Vdet with the output level instruction signal Vramp supplied from the baseband circuit and outputs a voltage corresponding to the potential difference between Vdet and Vramp as the output power control voltage Vapc is provided. A circuit including the output power detection circuit 221, the current-voltage conversion circuit 222, and the error amplifier 223 is a relatively general circuit conventionally used as an APC circuit.

  In the output power control circuit 220 of this embodiment, in addition to the circuits 221 to 223, a current detection circuit 224 that detects a current flowing through the amplification transistor at the final stage of the high-frequency power amplifier 210, and converts the output current into a voltage. A current-voltage conversion circuit 225, a differential amplifier 226 that compares the converted voltage Vmoni and a predetermined reference voltage Vpre, and an output voltage of the differential amplifier 226 is received at the gate terminal, and a source terminal is an output terminal of the error amplifier 223 And a precharge circuit 228 including a transistor Qe for supplying a current corresponding to the potential difference between Vmoni and Vpre to the error amplifier 223 is provided. The transistor Qe is a MOSFET in the embodiment, but may be a bipolar transistor.

  The precharge circuit 228 turns on the transistor Qe and supplies current to the error amplifier 223 when the voltage Vmoni input to the differential amplifier 226 is lower than the reference voltage Vpre. Here, the reference voltage Vpre is set to a level corresponding to -30 dBm to -20 dBm of output power. The reference voltage Vpre is preferably generated by a constant voltage circuit capable of generating a constant voltage having no power supply voltage dependency and temperature dependency, such as a band gap reference circuit. In the precharge circuit 228 of this embodiment, when the output level instruction signal Vramp supplied from the baseband circuit rises, the output of the error amplifier 223 rises, which is higher than the precharge level given by the precharge circuit 228. Is higher, the source voltage of the transistor Qe becomes higher than the gate voltage, so that Qe is automatically turned off.

FIG. 6B shows a change in potential of each internal node during transmission of the power module of the above embodiment.
In a GSM mobile phone using a conventional RF power module, when the output level instruction signal Vramp supplied from the baseband circuit at the start of transmission is suddenly raised to the transmission level, the rising speed of the output power of the high frequency power amplifier circuit Has become too fast, and there has been a problem that the spectrum characteristics of the output signal deviate from the range defined by the GSM standard. Therefore, as shown in FIG. 6A, during the period (t1 to t5) from when the power of the RF power module is turned on as a preparation for transmission until the output level instruction signal Vramp starts to rise, the period is 15 to 17 μs. As described above, an operation (t4 to t5) called “precharge” in which Vramp (Vapc) is raised to a level corresponding to −25 to −30 dBm of the output power for a short time is performed by software processing on the baseband IC side. I was doing.

  As apparent from the comparison of FIG. 6B showing the state of potential change in the power module of this embodiment with FIG. 6A showing the change in potential of the precharge by the conventional software processing, By applying, the output power Pout rises without raising the output level instruction signal Vramp for precharging during the period t4 to t5, and is output within the predetermined time mask defined by the GSM standard during the period t5 to t6. It can be seen that the power Pout can be raised.

  FIG. 7 shows a specific circuit example of the output power control circuit 220. FIG. 7 shows only one final-stage amplification transistor Qa3 as a representative for convenience of illustration, but the high-frequency power amplifier circuit 210 includes three amplification transistors in a multi-stage as in FIG. It is configured as a connected circuit. The drain terminal of the amplification transistor Qa3 at the final stage of the high-frequency power amplifier circuit 210 is connected to the output terminal OUT via the output line Lout. A DC cut capacitor C4 and a microcoupler 227 are provided in the middle of the output line Lout.

  The current detection circuit 224 includes a detection N-channel MOSFET Q11 in which the same voltage as the bias voltage Vb3 applied to the gate terminal of the amplification transistor Qa3 in the final stage is applied to the gate terminal via the resistor Ri, the transistor Q11 P-channel MOSFET Q12 connected in series with the transistor Q12, and the transistor Q12 and a current mirror-connected MOSFET Q13. The drain current of the transistor Q13 is caused to flow through a resistor 225 as a current-voltage converting means. Yes.

  Further, in this embodiment, the amplifying transistor Qa3 is formed by an LDMOS (Laterally Diffused MOSFET) having a relatively high source-drain breakdown voltage (about 20 V) obtained by diffusing electrodes laterally on a semiconductor chip. Accordingly, the biasing transistor Qb3 and the detecting transistor Q11 are also formed by a small LDMOS. As a result, a current proportional to the drain current of the amplifying transistor Qa3 flows through the detecting transistor Q11, and as a result, the output current can be detected. In addition, by using the gate voltage of the amplifying transistor Qa3 for current detection, the current detection circuit 224 of the embodiment can increase sensitivity at low power. Further, the detection transistor Q11 can reduce variations in detection current due to manufacturing variations by using an element formed on the same semiconductor chip as the amplification transistor Qa3.

  The output power detection circuit 221 includes a capacitor Ci having one terminal connected to a microcoupler 227 provided in the middle of the output line Lout between the drain terminal of the amplification transistor Qa3 at the final stage and the output terminal OUT of the module. , An N-channel MOSFET Q1 having the other terminal of the capacitor Ci connected to the gate, a P-channel MOSFET Q2 connected in series with the transistor Q1, a MOSFET Q3 connected in current mirror with the transistor Q2, and in series with the transistor Q3 A current detecting section 211 comprising a current-voltage conversion MOSFET Q4 connected to the output, a buffer circuit 212 for impedance-converting the voltage converted by Q4 and supplying it to the next stage, and a bias generator for applying a gate bias voltage to the MOSFET Q1 Circuit 213 and the bias generation circuit The buffer circuit 214 is configured to impedance-convert the bias voltage generated at 213 and supply it to the next stage, and the subtraction circuit 215 outputs a voltage obtained by subtracting the output of the buffer circuit 214 from the output of the buffer circuit 212. A voltage follower can be used for the buffer circuits 212 and 214.

  The bias generation circuit 213 includes a resistor R1 and a MOSFET Q5 connected in series between a power supply terminal to which an external constant voltage Vtxb is applied and a ground point, a gate terminal of the MOSFET Q5, and the output detection MOSFET Q1. A resistor R2 connected between the gate terminal of the MOSFET Q5 and a capacitor C11 connected between the gate terminal of the MOSFET Q5 and the ground point. MOSFET Q5 is configured such that its gate terminal and drain terminal are combined to act as a diode. The potential of the node N2 is determined by the resistor R1 and the current Ibias flowing through the transistor Q5, and the potential of N2 is applied as a bias voltage that gives an operating point to the gate terminal of the output detection MOSFET Q1.

  In this embodiment, as the value of the bias voltage, a voltage value close to the threshold voltage of Q1 is set so that the output detection MOSFET Q1 can perform a class B amplification operation. As a result, a current that is proportional to the AC waveform input through the capacitor Ci and half-wave rectified flows through the MOSFET Q1, and the drain current of Q1 has a DC component proportional to the amplitude of the input AC signal. To be included.

  The drain current Id of the transistor Q1 is transferred to the Q3 side by the current mirror circuit of Q2 and Q3, and is converted into a voltage by the diode-connected transistor Q4. Here, MOSFETs Q1 and Q4 and Q2 and Q3 are set to have a predetermined size ratio. Thereby, for example, if the characteristics (particularly the threshold voltage) of the MOSFETs Q1 and Q2 vary due to manufacturing variations, the characteristics of the MOSFETs Q4 and Q3 which form a pair with the MOSFETs Q1 and Q2 also vary in the same way. As a result, the influence due to the characteristic variation is offset, and an output detection voltage that is not affected by the variation of the MOSFET appears at the drain terminal of the MOSFET Q4.

  In this embodiment, the potential of the connection node N2 between the gate terminal of the MOSFET Q5 of the bias generation circuit 213 and the resistor R2 is input to the input terminal of the buffer circuit 214. The resistor R <b> 2 and the capacitor C <b> 11 function as a low-pass filter that prevents the AC component of the output power captured via the capacitor Ci from entering the input of the buffer circuit 214.

  In this embodiment, the same voltage as the bias voltage generated by the bias generation circuit 213 and applied to the gate terminal of the output detection MOSFET Q1 is supplied to the subtraction circuit 215 via the buffer circuit 214. A voltage obtained by subtracting the voltage is output from the subtraction circuit 215. As a result, the output of the subtraction circuit 215 is input to the error amplifier 223 as a detection voltage Vdet proportional to the AC component of pure output power that does not include the DC component applied by the bias generation circuit 213, and the error amplifier 223 receives the detection voltage. A voltage corresponding to the potential difference between Vdet and the output level instruction signal Vramp is output to the bias circuit 230 as the output power control voltage Vapc.

  FIG. 8 shows another embodiment of a power module to which a bias circuit 230 having a square circuit is applied. In this embodiment, the transmission signals of two systems, GSM and DCS (Digital Cellular System), are each configured to be capable of being amplified and output according to the mode.

  In FIG. 8, reference numeral 200 denotes a power module including a high frequency power amplifier circuit 210 that amplifies a high frequency transmission signal supplied from the baseband IC 110, an output power detection circuit 221, an error amplifier 223, a precharge circuit 228, a bias circuit 230, and the like. Reference numeral 300 denotes filters LPF1 and LPF2 that remove noise such as harmonics contained in the transmission signal, duplexers DPX1 and DPX2 that synthesize and separate the GSM signal and DCS signal, and a transmission / reception changeover switch T / R- It is a front-end module including SW.

  In FIG. 8, ANT is an antenna for transmitting and receiving signal radio waves, 100 is a modulation / demodulation circuit capable of performing GMSK modulation / demodulation and PSK modulation / demodulation in an EDGE mode in a GSM or DCS system, and transmission data (baseband signal). , A high frequency signal processing circuit (hereinafter referred to as a baseband IC) 110 that is a semiconductor integrated circuit having a circuit that generates a Q signal and processes an I and Q signal extracted from the received signal, and amplifies the received signal Low noise amplifiers LNA1 and LNA2, bandpass filters BPF1 and BPF2 for removing harmonic components from transmission signals, bandpass filters BPF3 and BPF4 for removing unnecessary waves from reception signals, and the like are mounted in one package (Hereinafter referred to as an RF device). The low noise amplifiers LNA1 and LNA2 can be incorporated in the baseband IC 110.

  The power module 200 of this embodiment is provided with a high frequency power amplifier circuit 210a for GSM and a high frequency power amplifier circuit 210b for DCS, and the output power control circuit is an output power detection circuit 221, an error amplifier 223, a precharge circuit 228. The circuit is provided as a circuit common to the GSM and DCS amplifier circuits except for the current detection circuit (224) for precharging. Baseband IC 110 includes mixers Tx-MIX1 and Tx-MIX2 for up-converting GSM and DCS transmission signals, mixers Rx-MIX1 and Rx-MIX2 for down-converting GSM and DCS reception signals, and these mixers. Are provided with oscillators VCO1 to VCO4 that generate oscillation signals mixed with transmission signals and reception signals, and variable gain amplifiers GCA1 and GCA2 for amplifying transmission signals of GSM and DCS, respectively.

  As shown in FIG. 8, in this embodiment, a mode control signal Vband indicating GSM or DCS, an output level instruction signal Vramp, and a power supply voltage Vtxb for the detection circuit are sent from the baseband IC 110 to the power module 200. The output power control circuit generates a bias current based on the control signal Vband and the output level instruction signal Vramp and supplies it to one of the high frequency power amplifier circuits 210a and 210b, while receiving the rising of the power supply voltage Vtxb. Then, the precharge circuit 228 operates to precharge the output power control voltage Vapc.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above-described embodiment, the bias circuit 230 including the square circuit is combined with the output power control circuit including the precharge circuit 228. However, the bias circuit 230 including the square circuit and the precharge circuit 228 are included. It is also possible to combine with no output power control circuit.

  Further, the output power control circuit 220 is not limited to the circuit as in the embodiment of FIG. 7, and the output power detection circuit 221 and the amplifier 226 and the MOSFET Qe of the precharge circuit 228 are omitted in FIG. A voltage obtained by converting the output current of 224 by the resistor 225 may be input to the error amplifier 223 as the output detection voltage Vdet. Further, a detection circuit using a diode element may be used instead of the output power detection circuit 221 formed of a MOSFET. The square root circuit is not limited to the one shown in FIG. Further, the bias current generation circuit including the differential amplifier AMP1 and the MOSFETs Q30 to Q33 is a circuit that outputs a current obtained by square-converting an input using an operational amplifier circuit or the like without having a square root circuit in the feedback path. You may make it comprise.

  In the above description, the case where the invention made mainly by the present inventor is applied to a high frequency power amplifier circuit and a power module used in a mobile phone which is a field of use behind the present invention has been described, but the present invention is not limited thereto. It can be used for a high-frequency power amplifier circuit and a power module that constitute a wireless LAN.

FIG. 1 is a circuit configuration diagram showing a schematic configuration of a high-frequency power amplifier circuit according to the present invention. It is a block diagram which shows schematic structure of the Example of the output power control circuit which has the precharge function of the high frequency power amplifier circuit which concerns on this invention. FIG. 2 shows an output power control signal Vapc and an amplifying transistor in a high frequency power amplifier circuit to which a bias circuit having a square root circuit of this embodiment is applied and a high frequency power amplifier circuit to which a bias circuit having no square root circuit is applied. It is a graph which shows the relationship with the idle current Iidle. FIG. 3 shows an output power control signal Vapc and output power Pout in the high frequency power amplifier circuit to which the bias circuit having the square root circuit of the present embodiment is applied and the high frequency power amplifier circuit to which the bias circuit having no square root circuit is applied. It is a graph which shows the relationship. FIG. 4 is a circuit diagram showing a specific circuit example of the square root circuit. FIG. 5 is a block diagram showing an embodiment of a high frequency power amplifier (power module) to which the high frequency power amplifier circuit of the embodiment is applied. FIG. 6A is a timing chart showing the state of potential change of each internal node at the time of transmission of the conventional RF power module, and FIG. 6B is a timing chart of the internal node at the time of transmission of the RF power module of the embodiment. It is a timing chart which shows the mode of potential change. FIG. 7 is a circuit diagram showing a specific circuit example of the output power control circuit. FIG. 8 is a block diagram illustrating another configuration example of the power module to which the bias circuit having the square root circuit of the embodiment is applied and the wireless communication system using the power module.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 RF device 110 Baseband circuit 200 Power module 210 High frequency power amplification circuit 220 Output power control circuit 221 Output power detection circuit (detection circuit)
223 Error amplifier 224 Current detection circuit 225 Voltage-current conversion circuit 227 Coupler 228 Precharge circuit 230 Bias circuit 231 Current generation circuit 232 Square root circuit 300 Front end module ANT Transmit / receive antenna LPF Low pass filter LNA Low noise amplifier GCA Variable Gain amplifier

Claims (10)

A power amplifying transistor, a bias transistor that is current-mirror connected to the power amplifying transistor, and a bias circuit that causes a bias current to flow through the bias transistor according to an output power control voltage are amplified, and a high-frequency transmission signal is amplified. A high frequency power amplifier circuit,
The bias circuit outputs a bias current obtained by squaring the output power control voltage, and causes the bias current to flow through the bias transistor so that an operation current corresponding to the output power control voltage is supplied to the power amplification transistor. A high-frequency power amplifier circuit configured to flow.   The bias circuit includes an operational amplifier circuit that receives the output power control voltage at one input terminal and a feedback voltage at the other input terminal, and has 2 in a feedback path from the output of the operational amplifier circuit to the other input terminal. A power root circuit is provided, and a bias current obtained by squaring the output power control voltage is output by feeding back a voltage obtained by squaring the output of the operational amplifier circuit. The high frequency power amplifier circuit according to claim 1.   A plurality of subordinately connected power amplifying transistors, and a plurality of bias transistors connected to the power amplifying transistors and current mirrors, wherein the bias circuit is a bias obtained by squaring the output power control voltage. 3. The high frequency power amplifier circuit according to claim 1, wherein a current is passed through the biasing transistor.   The bias circuit includes a voltage-current conversion transistor that receives the output voltage of the operational amplifier circuit at a control terminal, and is configured to flow a current flowing through the voltage-current conversion transistor to the bias transistor. The high-frequency power amplifier circuit according to any one of claims 1 to 3.   The high-frequency power amplifier circuit according to claim 1, wherein the bias transistor is an element having the same structure formed on the same semiconductor chip as the power amplifier transistor. A power amplifying transistor; a bias transistor connected to the power amplifying transistor in a current mirror; a bias circuit for supplying a bias current to the bias transistor according to an output power control voltage; and detecting a magnitude of the output power An output power detection circuit; and an output power control circuit that generates an output power control voltage to be supplied to the bias circuit based on a detection signal of the output power detection circuit and a signal indicating a level of output power. A high-frequency power amplification electronic component that amplifies and outputs a high-frequency transmission signal according to a signal indicating a power level,
The bias circuit outputs a bias current obtained by squaring the output power control voltage, and causes the bias current to flow through the bias transistor so that an operation current corresponding to the output power control voltage is supplied to the power amplification transistor. An electronic component for high-frequency power amplification characterized by being configured to flow.   The bias circuit includes an operational amplifier circuit that receives the output power control voltage at one input terminal and a feedback voltage at the other input terminal, and has 2 in a feedback path from the output of the operational amplifier circuit to the other input terminal. A power root circuit is provided, and a bias current obtained by squaring the output power control voltage is output by feeding back a voltage obtained by squaring the output of the operational amplifier circuit. The electronic component for high frequency power amplification according to claim 6.   A plurality of subordinately connected power amplifying transistors, and a plurality of bias transistors connected to the power amplifying transistors and current mirrors, wherein the bias circuit is a bias obtained by squaring the output power control voltage. 8. The electronic component for high frequency power amplification according to claim 6, wherein a current is passed through the biasing transistor.   A precharge circuit that raises the output power control voltage so that the output power becomes a predetermined level while detecting the current flowing through the power amplification transistor in the final stage in response to the rise of the power supply voltage at the start of transmission; 9. The output power control voltage is raised to a predetermined precharge level without raising a signal indicating the level of the output power to a predetermined level at the start of transmission. An electronic component for high frequency power amplification according to claim 1.   The precharge circuit includes a current detection circuit that detects a current flowing through the power amplification transistor in the final stage, a current-voltage conversion circuit that converts an output current of the current detection circuit into a voltage, and the current-voltage conversion circuit A differential amplifier circuit that compares the output voltage with a predetermined potential and outputs a voltage corresponding to the potential difference, and receives the output voltage of the differential amplifier circuit at a control terminal, and a source terminal or an emitter terminal of the output power control circuit The high frequency power amplification electronic component according to claim 9, further comprising a transistor connected to the output terminal.

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