JP2007201698A - High frequency power amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an output power control technology whereby the forward isolation in a standby state of a high frequency power amplifier (power module) can be improved, wherein the high frequency power amplifier controls an output power by making a bias voltage applied to a control terminal of a high frequency power amplifier element constant so as to change an operating voltage (power voltage) in response to a signal for instructing an output level. <P>SOLUTION: In the high frequency power amplifier of two-stage configuration provided with an operating voltage control circuit (220) for controlling an output power by changing an operating voltage (VLDO) of amplifier FETs in response to the signal (Vramp) for instructing the output level, a prescribed bias is given to a gate terminal of the first or second stage amplifier FET before a start signal (Vtxon) is triggered. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention is applied to a high-frequency power amplifier that amplifies and outputs a high-frequency signal, and further to a high-frequency power amplifier that controls output power by changing an operating voltage (power supply voltage) of an amplifying element in accordance with a signal indicating an output level. For example, the present invention relates to a technique effective for use in a high-frequency power amplifier used in a mobile phone.

  In general, a transmission-side output unit in a wireless communication device (mobile communication device) such as a mobile phone is provided with a high-frequency power amplification circuit (power amplifier) that amplifies a modulated transmission signal. In the conventional wireless communication apparatus, a control voltage output from a circuit called an APC (Automatic Power Control) circuit is used to control the output power amplification factor of the high-frequency power amplifier circuit according to the transmission request level supplied from the base station. Accordingly, a configuration is adopted in which a bias voltage applied to the control terminal of the high-frequency power amplifying element is generated and the gain is controlled.

  The APC circuit biases the amplifying element so as to obtain the output power necessary for the call based on the signal detected by the detection circuit or the like and the output level instruction signal from the baseband circuit or the like. Generate a signal to control. A wireless communication device of such a control method is disclosed in Patent Document 1, for example. The bias of the amplifying element means a gate bias when the amplifying element is an FET (field effect transistor), and a base bias when the amplifying element is a bipolar transistor.

On the other hand, a high frequency power amplifier circuit that linearly operates the amplifying element by controlling the operating voltage (power supply voltage) of the amplifying element based on a signal indicating the output level so that the output level changes in proportion to the signal. Has been proposed (for example, see Patent Document 2).
JP 2000-151310 A Japanese Patent Laid-Open No. 2005-020383

  In a communication system standard such as GSM (Global System for Mobile Communication), when a high-frequency signal of a predetermined level is input to the input terminal before the start-up signal of the high-frequency power amplifier circuit rises, it leaks to the output terminal It is defined that the signal is below a predetermined level. Such a standard is called forward isolation.

  The high frequency power amplifier circuit used in Patent Document 2 previously proposed by the present applicant is a three-stage amplifier circuit in which three amplifier stages are cascade-connected. In order to reduce the size and power consumption of the system, the present inventors considered the development of a two-stage circuit in which two amplification stages are cascade-connected in a high-frequency power amplifier circuit of an operating voltage control system. Was examined.

  As a result, a high-frequency power amplifier circuit having a three-stage operation voltage control system satisfies the forward isolation standard, but if the amplifier stage is simply changed to two stages without changing the circuit configuration, forward isolation is achieved. It became clear that this standard could not be met. The bias control type high frequency power amplifier circuit satisfies the forward isolation standard even if the three-stage configuration is changed to the two-stage configuration. For this reason, when the three-stage configuration is changed to the two-stage configuration in the high-frequency power amplifier circuit of the operating voltage control system, the reason why the forward isolation standard is not satisfied is as follows. This is thought to be due to

  FIG. 9A is a conceptual diagram of one amplification stage of a gate bias control type high frequency power amplifier circuit, and FIG. 9B shows a specific circuit configuration example thereof. FIG. 10A is a conceptual diagram of one amplification stage of an operating voltage control type high frequency power amplifier circuit, and FIG. 10B shows a specific circuit configuration example. In FIGS. 9B and 10B, Qa is an amplifying FET, and Qb is a biasing FET that converts a bias current Ibias into a voltage and applies a gate bias to Qa. 9B and 10B show the states of the power supply terminal voltage and the bias voltage in a state before the start-up signal rises (referred to as Tx-off or standby state).

  In the high-frequency power amplifier circuit of the gate bias control system in FIG. 9B, the gate bias voltage Vbias is 0 V at the time of Tx-off, and the power supply voltage Vdd from the battery is applied to the drain terminal of the amplifying FET Qa. . For this reason, a depletion layer is generated in the reverse bias state at the PN junction between the drain region and the well region of Qa, and the parasitic capacitance between the gate and the drain is hardly visible.

  On the other hand, in the operating voltage control type high frequency power amplifier circuit of FIG. 10B, the gate bias voltage Vbias is 0 V at the time of Tx-off, and 0 V is applied as the operating voltage Vdd to the drain terminal of the amplifying FET Qa. Is done. As a result, the drain region and the well region of Qa are at the same potential, and almost no depletion layer is formed in the PN junction, and thus the parasitic capacitance Cst between the gate and the drain can be seen from the input terminal, and the high-frequency signal input to the gate Will leak to the output side.

  In the three-stage high-frequency power amplifier circuit, three parasitic capacitances between the gate and the drain are connected in series, so that the signal is attenuated by the three series capacitances to satisfy the forward isolation standard. . However, in a two-stage high-frequency power amplifier circuit, two parasitic capacitances between the gate and the drain are connected in series, so that the amount of signal attenuation is reduced and forward isolation standards cannot be satisfied. Conceivable.

  Furthermore, in the GSM wireless communication system, as shown in FIG. 6, first, a command “Word3” for instructing the start of transmission operation is supplied from the baseband IC to the high-frequency IC having the modulation and up-conversion functions. (Timing t1). Then, the high frequency IC precharges the transmission oscillator (TxVCO), waits for the oscillation operation of the TxVCO to stabilize, and at the time (t4) when the timing offset time Toff has passed to allow more time. The start signal Vtxon for the high frequency power amplifier is raised.

  Thereafter, the output control voltage Vramp starts to rise at a timing t5 delayed by a predetermined delay time Td or more. Since the operating voltage Vdd is generated based on Vramp, it is slightly delayed from the rise of Vramp (timing t6). When transmission is completed, Vramp and Vdd fall, and then a command “Word4” for instructing an internal reset, for example, is supplied from the baseband IC to the high frequency IC. Then, a circuit such as a register in the high frequency IC is reset, and the high frequency IC and the high frequency power amplifier enter an idle mode (sleep state waiting for a command) (timing t8).

  As described above, even if the activation signal Vtxon rises and enters a standby (Tx-on) state, the operating voltage Vdd applied to the drain terminal of the amplifying FET Qa does not rise immediately but has a slight delay. is there. Therefore, in the circuit of FIG. 10B, since the drain voltage of Qa is low for a while after the rise and the depletion layer remains widened, the high-frequency signal at the input terminal is output via the parasitic capacitance between the gate and the drain. May leak to the side and sufficient forward isolation may not be obtained.

  An object of the present invention is to provide a high-frequency power for controlling the output power by changing the operating voltage (power supply voltage) in accordance with a signal indicating the output level while keeping the bias voltage applied to the control terminal of the high-frequency power amplifying element constant. An object of the present invention is to provide an output power control technique capable of improving forward isolation in a standby state in an amplifier (power module).

  Another object of the present invention is to control the output power by changing the operating voltage (power supply voltage) according to the signal indicating the output level while keeping the bias voltage applied to the control terminal of the high frequency power amplifier element constant. An object of the present invention is to provide an output power control technique capable of improving forward isolation immediately after startup in a high-frequency power amplifier (power module).

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Outlines of representative ones of the inventions disclosed in the present application will be described as follows.

  That is, before the start-up signal rises in a two-stage high-frequency power amplifier having an operating voltage control circuit that controls the output power by changing the operating voltage of the amplifying FET in accordance with a signal (Vramp) indicating the output level. Applies a predetermined bias to the gate terminal of the first or second stage amplification FET. Desirably, a predetermined bias is applied to the gate terminal of the first-stage or second-stage amplifying FET even during a period until the signal indicating the output level after the start-up signal rises to a predetermined level. To. Further, after the signal indicating the output level reaches a predetermined level, the bias is switched so as to give a gate voltage at which the first and second stage amplification FETs operate in the saturation region. To do.

  According to the above-described means, a predetermined bias is applied to the gate terminal of the amplifying FET before the start signal is raised and until the signal indicating the output level reaches a predetermined level. The parasitic capacitance can be hidden. For this reason, it is possible to prevent the high-frequency signal that has entered the input terminal from being transmitted to the subsequent stage, thereby improving forward isolation. Note that the reason why the parasitic capacitance of the amplifying FET becomes invisible by applying a predetermined bias to the gate terminal of the amplifying FET is considered to be that an inversion layer is formed on the substrate surface under the gate electrode.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, the bias voltage applied to the control terminal of the high-frequency power amplifying element is made constant, and the output voltage is controlled by changing the operating voltage (power supply voltage) according to the signal indicating the output level. In the power amplifier (power module), forward isolation in the standby state can be improved. In addition, there is an effect that forward isolation immediately after startup can be improved.

  Preferred embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows an embodiment of a high-frequency power amplifier (power module) according to the present invention comprising a high-frequency power amplifier circuit and an operating voltage control circuit that generates an operating voltage and controls output power.

  In the high-frequency power amplifier circuit 210 of the high-frequency power amplifier of this embodiment, two amplifier stages 211 and 212 each including amplifier elements Qa1 and Qa2 such as FETs and bipolar transistors are connected in series, that is, the drain terminal of the FET Qa1 in the previous stage The gate terminal of the next-stage FET Qa2 is connected via the impedance matching circuit IM1, and the signal amplified by Qa1 is further amplified by Qa2. The control terminals (gate terminals or base terminals) of the amplification elements Qa1 and Qa2 of the amplification stages 211 and 212 are connected to the control terminals of the bias transistors Qb1 and Qb2 via resistors Rb1 and Rb2, respectively.

  The bias transistors Qb1 and Qb2 have a so-called diode connection in which a gate and a drain or a base and a collector are coupled. The bias currents Ibias1 and Ibias2 supplied from the current sources CS1 and CS2 are converted into voltages, and the amplifying elements Qa1 and Qa2 Apply to control terminal. As a result, the amplifier elements Qa1 and Qa2 are supplied with currents such that the ratio between the bias currents Ibias1 and Ibias2 and the currents flowing through Qa1 and Qa2 matches the size ratio of Qb1 and Qb2 and Qa1 and Qa2. IM0 is an input impedance matching circuit provided between the input terminal Pin and the control terminal of the first stage amplifying element Qa1, and IM2 is provided between the drain terminal of the second stage amplifying element Qa2 and the output terminal Pout. Output impedance matching circuits L1 and L2 are inductance elements.

  The operating voltage control circuit 220 is supplied from a P-channel MOS transistor Mp1 connected between a power supply voltage terminal that receives a power supply voltage Vdd from a battery or the like and a power supply voltage terminal of the high-frequency power amplifier circuit 210, and a baseband circuit (not shown). A control voltage Vramp corresponding to an output level designation signal for designating an output level to be applied is applied to the inverting input terminal, and an output terminal is connected to the base terminal of the transistor Mp1 (operational amplifier (differential amplifier circuit) AMP).

  The operating voltage control circuit 220 includes a phase compensation circuit including a series resistor R0 and a capacitor C0 connected between the drain terminal of the transistor Mp1 and the internal node of the operational amplifier AMP1, and the drain terminal of the transistor Mp1. The resistor R1 is connected between the non-inverting input terminal of the operational amplifier AMP and the resistor R2 is connected between the non-inverting input terminal of the operational amplifier AMP and the ground point. Further, the operating voltage control circuit 220 converts an external constant voltage Vreg into a current, and passes the converted current Ioff through the resistor R2, thereby giving an offset to the voltage fed back to the operational amplifier AMP. Have a VIC.

The drain voltage of the transistor Mp1 is set to a voltage obtained by dividing the output control voltage Vramp according to the resistance ratio of the resistors R1 and R2 by the operation of the operational amplifier AMP. Specifically, the voltage is expressed as Vramp · (R1 + R2) / R2 + R1 · Ioff. Accordingly, by appropriately setting the resistance values of the resistors R1 and R2, a voltage VLDO proportional to the control voltage Vramp as shown in FIG. 2 can be generated and applied to the power supply voltage terminal of the high frequency power amplifier circuit 210. . Instead of the P-channel MOS transistor Mp1, a PNP bipolar transistor may be used.
The high-frequency power amplifier 200 of the present embodiment configured as described above can generate the voltage VLDO proportional to the output control voltage Vramp and apply it to the power supply voltage terminal of the high-frequency power amplifier circuit 210. The output voltage Vout of the circuit 210 can be controlled linearly according to the control voltage Vramp. In addition, even if the power supply voltage Vdd supplied from a battery or the like changes, the drain voltage of the transistor Mp1, that is, the operating voltage VLDO supplied to the high-frequency power amplifier circuit 210 is kept substantially constant.

  In mobile phones, a lithium ion battery is generally used as a power source. However, a lithium ion battery has a relatively high voltage value such as 4.7 V immediately after charging, but after that, the level gradually decreases to the minimum necessary level. When the power is consumed to a level where it can be obtained, the voltage drops to a very low voltage value such as 2.9V. Therefore, when the power supply voltage Vdd is a battery voltage from a lithium ion battery or the like, an operation that does not depend on the power supply voltage even if the power supply voltage Vdd changes greatly by applying the high frequency power amplifier circuit of the above embodiment. The voltage VLDO can be applied to the high frequency power amplifier circuit 210. As a result, even if the power supply voltage Vdd changes, the output voltage Vout of the high-frequency power amplifier circuit 210 can be linearly controlled according to the control voltage Vramp. The power supply voltage Vdd is not limited to a direct voltage from the battery, and may be a voltage stepped down or boosted by a DC-DC converter or the like.

  Further, the high-frequency power amplifier of this embodiment is provided between the gate terminal of the amplifying FET Qa and the gate terminal of the biasing FET Qb, and uses a constant voltage Vreg from the outside instead of the voltage converted by Qb. Is provided to the gate terminal of Qa. Further, a comparison circuit CMP that compares the output control voltage Vramp with a predetermined reference voltage Vref, and a NAND gate G1 that receives the output of the comparison circuit CMP and an external start signal Vtxon are provided. The NAND gate G1 The changeover switch SW1 is controlled to be switched by the output of. As a result, when the start signal Vtxon is set to the high level and the control voltage Vramp is higher than the reference voltage Vref, the changeover switch SW1 applies the voltage converted by the bias FET Qb to the gate terminal of Qa. Applies an external constant voltage Vreg to the gate terminal of Qa.

  Although not obvious from FIG. 1, the activation signal Vtxon is supplied to each part in the high-frequency power amplifier and is used as a signal for activating the whole. Although not particularly limited, in this embodiment, the constant voltage Vreg is set to a value such as 2.0V, and the reference voltage Vref is set to a value such as 0.16V. Hereinafter, the basis of these values will be described.

  In a two-stage high-frequency power amplifier in which the high-frequency power amplifier circuit has two amplification FETs, a +8 dBm signal at 824 MHz and a +8 dBm signal at 915 MHz are input to the input terminal Pin with the operating voltage Vdd being 0 V. The results of measuring the level of the signal leaking to the output terminal when the gate voltage of the amplification FET is swung from 0V to 3.5V are shown in FIGS.

  3 to 5, FIG. 3 shows the case where the gate voltage of the second stage amplifying FET Qa2 is fixed at 0 V and only the gate voltage of the first stage amplifying FET Qa1 is changed. Is the one when the gate voltage of the first stage amplifying FET Qa1 is fixed at 0V and only the gate voltage of the second stage amplifying FET Qa2 is changed. FIG. 5 shows the case where both gate voltages of the first and second stage amplification FETs Qa1 and Qa2 are changed.

  3 to 5, forward isolation is performed in the order of FIGS. 3, 4, and 5, that is, only the gate voltage of Qa 1 is changed, only the gate voltage of Qa 2 is changed, and both gate voltages of Qa 1 and Qa 2 are changed. It turns out that it improves. However, the GSM standard stipulates that when Vtxon is 0.5 V or less, the level of a signal leaking to the output terminal is −25 dBm or less. Referring to FIGS. 3 to 5, it can be seen that in any case, the standard can be satisfied if the gate voltage is 1.5 V or more.

  Therefore, in the above-described embodiment, the amplification FET for switching the gate voltage before startup is only in the first stage, and the constant voltage Vreg to be applied is set to 2.0 V with a margin. 3 to 5, it can be seen that the amplifying FET for switching the gate voltage before the start-up may be only the second stage or both, thereby obtaining higher forward isolation. However, since this makes the circuit complicated, it is desirable to use the first stage as in the embodiment. Further, it is easier to obtain desired output characteristics when the gate voltage of the second-stage amplification FET Qa2 is changed according to the output control voltage Vramp.

  Therefore, in the high-frequency power amplifier according to the present embodiment, the current source CS2 that supplies a current to the second-stage biasing FET Qb2 is configured to supply a current proportional to the output control voltage Vramp. On the other hand, the gate voltage of the amplification FET Qa1 at the first stage is set to a voltage as low as possible within a range where the Qa1 can be operated in the saturation region, so that the power efficiency is bathed without impairing the output characteristics. be able to. Therefore, the current source CS1 that supplies current to the first-stage bias FET Qb1 is configured to simply turn on and off a predetermined current (1 mA) in accordance with the activation signal Vtxon.

  What has been clarified in the above description is the reason why the gate voltage of the first-stage amplification FET Qa1 is switched in response to the activation signal Vtxon. There is no need to provide the gate G1, and the switch SW1 may be directly switched by the activation signal Vtxon. Next, the reason why the comparison circuit CMP and the NAND gate G1 are provided will be described.

  In the operating voltage control type high frequency power amplifier, as described above, the operating voltage control circuit 220 is configured to generate the operating voltage Vdd proportional to the output control voltage Vramp from the outside. When such control is performed, the output control voltage Vramp may not become 0V even though the baseband circuit outputs a signal RAMP indicating 0V as Vdd due to manufacturing variation or the like. In that case, there is a possibility that an operating voltage Vdd of 0 V or higher is generated and supplied to the high-frequency power amplifier circuit 210 to output.

  In order to avoid this, in this embodiment, the output control voltage Vramp is offset, and as shown in FIG. 2, when the output control voltage Vramp is 0.16 V or more, the operation voltage Vdd proportional to Vramp is obtained. The operating voltage control circuit 220 is configured to generate On the other hand, as shown in FIG. 6, the output control voltage Vramp starts to rise at a timing t5 that is always delayed by a delay time Td or more with respect to the activation signal Vtxon. If the switch SW1 is switched simultaneously with the rise of the start signal Vtxon, the gate voltage (1.05V) of the bias FET Qb1 that converts the current from the current source CS1 into a voltage is applied to the gate of the amplification FET Qa1. The

  However, the GSM standard stipulates that the level of a signal leaking to the output terminal is −20 dBm or less when Vtxon is at a high level such as 1.5V. Therefore, it has been found that if the switch SW1 is switched simultaneously with the rise of the start signal Vtxon as described above, the level of the signal leaking to the output terminal becomes −25 to −26 dBm and the margin is reduced.

  Therefore, in the embodiment, the comparison circuit CMP and the NAND gate G1 are provided, and the switch SW1 is not switched until the output control voltage Vramp becomes 0.16V or higher even when the start signal Vtxon rises, and Vramp becomes 0.16V or higher. After that, the switch SW1 is switched. Note that the gate voltage of the FET Qa1 after startup is 1.05V.

  As a result, even if the activation signal Vtxon rises, a voltage of 2V higher than the gate voltage of the FET Qa1 after the activation of 1.05V is applied to the gate of the Qa1 until the output control voltage Vramp becomes 0.16V or more. . Here, referring to FIGS. 3 to 5, the higher the gate voltage of Qa1, the better the forward isolation. Therefore, in the high-frequency power amplifier according to the embodiment, it is possible to prevent the forward isolation from deteriorating after the activation signal Vtxon rises and before the operating voltage Vdd rises due to the rise of the control voltage Vramp.

  FIG. 7 shows a simulation of the change in the output power Pout with respect to the change in the control voltage Vramp in the high-frequency power amplifier to which the present embodiment is applied and the high-frequency power amplifier in which the present embodiment is not applied and simply has a two-stage amplification stage. The result obtained by is shown. In FIG. 7, a solid line A relates to a high frequency power amplifier to which the present embodiment is applied, and a broken line B relates to a high frequency power amplifier to which the present embodiment is not applied. Comparing the solid line A and the broken line B, it can be seen that the solid line A, that is, the high-frequency power amplifier to which this embodiment is applied, has a lower level of output power Pout in a region where Vramp is 0.1 V or less and a higher forward isolation. .

  FIG. 8 shows a second embodiment of the high-frequency power amplifier to which the present invention is applied.

  In this embodiment, a current source CS0 and an on / off switch SW0 are provided in parallel with a current source CS1 for applying a bias current to the first-stage bias FET Qb1, and the switch SW0 is controlled by an output of the NAND gate G1. The switch SW1 between the gate terminals of Qb1 and the amplifying FET Qa1 is controlled by the start signal Vtxon. The current source CS0 has substantially the same current value as the current source CS1, for example, 1 mA.

  In this embodiment, the changeover switch SW1 is connected to the constant voltage Vreg side until the activation signal Vtxon rises, and a voltage of 2V is applied to the gate of Qa1. When the start signal Vtxon rises, the changeover switch SW1 is connected to the bias FET Qb1 side. At this time, the switch SW0 is in an ON state, and both currents (2 mA) of the current sources CS0 and CS1 are supplied to the bias FET Qb1, and the bias FET Qb1 is given a higher bias than that in the normal operation, and is isolated. Is made high.

  Thereafter, when the output control voltage Vramp becomes 0.16 V or more, the output of the NAND gate G1 changes, the switch SW0 is turned off, and the current flowing through Qb1 is only the current (1 mA) of the current source CS1, and the FET Qa1 Qa1 having a gate voltage of 1.05 V is set to a potential for operating in the saturation region. The configuration of the current source CS0 and the on / off switch SW0 in FIG. 8 is conceptually shown in the embodiment. The current source CS0 can be directly turned on / off by the output of the NAND gate G1, or the current source The current source CS1 may be configured so that the current of CS1 can be switched in two stages, and the current may be switched by the output of the NAND gate G1.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above embodiment, the bias FETs Qb1 and Qb2 connected in common to the amplifying FETs Qa1 and Qa2 are provided to bias the Qa1 and Qa2, but a predetermined bias voltage is divided by resistance division. It may be a high frequency power amplifier that applies a bias to Qa1 and Qa2.

  In the embodiment, FETs are used as the amplifying elements Qa1 and Qa2. However, in addition to normal MOSFETs, these FETs have a relatively high source-drain breakdown voltage obtained by diffusing electrodes laterally on a semiconductor chip. LDMOS (Laterally Diffused MOSFET) or GaAs MESFET having (about 20 V) may be used.

  In the above description, the case where the invention made mainly by the inventor is applied to the power module constituting the GSM wireless communication system, which is the field of use behind it, has been described. However, the present invention is not limited thereto. Not. For example, the present invention can also be used for a power module used in a CDMA mobile phone.

FIG. 1 is a circuit configuration diagram showing an embodiment of a high frequency power amplifier (power module) of the present invention comprising a high frequency power amplifier circuit and an operating voltage control circuit for generating an operating voltage and controlling output power. FIG. 2 is a graph showing the relationship between the output level instruction signal Vramp and the operating voltage VLDO output from the operating voltage control circuit in the embodiment. FIG. 3 shows a two-stage high-frequency power amplifier in which a +8 dBm signal at 824 MHz and a +8 dBm signal at 915 MHz are input to the input terminal Pin with the operating voltage Vdd being 0 V, and a second-stage amplification FET 5 is a graph showing the result of measuring the level of a signal leaking to the output terminal when the gate voltage of the first stage FET is fixed to 0 V and the gate voltage of the first stage amplification FET is swung from 0 V to 3.5 V. FIG. 4 shows a high-frequency power amplifier having a two-stage configuration, in which a +8 dBm signal at 824 MHz and a +8 dBm signal at 915 MHz are input to the input terminal Pin with the operating voltage Vdd being 0 V. This is a graph showing the result of measuring the level of a signal leaking to the output terminal when the gate voltage of the second stage FET is fixed to 0 V and the gate voltage of the second stage amplification FET is swung from 0 V to 3.5 V. FIG. 5 shows a two-stage high-frequency power amplifier in which a +8 dBm signal at 824 MHz and a +8 dBm signal at 915 MHz are input to the input terminal Pin with the operating voltage Vdd being 0 V. It is a graph which shows the result of having measured the level of the signal which leaks to an output terminal, when the gate voltage of FET for amplification of this is shaken from 0V to 3.5V. FIG. 6 is a timing chart showing the timing of changes in signals such as the start signal Vtxon and the control voltage Vramp in the GSM radio communication system to which the high frequency power amplifier of the embodiment is applied. FIG. 7 shows, by simulation, the change in the output power Pout with respect to the change in the control voltage Vramp in the high-frequency power amplifier to which the present embodiment is applied and the high-frequency power amplifier in which the present embodiment is not applied and simply has a two-stage amplification stage. It is a characteristic view which shows the calculated | required result. FIG. 8 is a circuit diagram showing a second embodiment of the high-frequency power amplifier to which the present invention is applied. FIG. 9A is a conceptual diagram of one amplification stage of a gate bias control type high-frequency power amplifier circuit, and FIG. 9B is a circuit configuration diagram showing a specific example thereof. FIG. 10A is a conceptual diagram of one amplification stage of an operating voltage control type high frequency power amplifier circuit, and FIG. 10B is a circuit configuration diagram showing a specific example thereof.

Explanation of symbols

Qa1, Qa2 FET for amplification
Qb1, Qb2 Bias FET
Mp1 Power supply control transistor 200 High frequency power amplifier (RF power module)
210 High frequency power amplifier circuit 220 Operating voltage control circuit 221 Power conversion circuit

Claims (5)

A first amplifying FET in which a high-frequency signal from the input terminal is input to the gate terminal, and a second amplifying FET in which a signal output from the drain terminal of the first amplifying FET is input to the gate terminal And an operating voltage control circuit that controls the output power by changing the operating voltage applied to the drain terminals of the first and second amplifying FETs in accordance with a signal indicating the output level. Because
Bias switching means is provided for applying a voltage having a first potential different from the voltage applied to the gate terminal to the gate terminal of the first or second amplification FET until the start signal rises. A high frequency power amplifier characterized by that.   The high-frequency power amplifier according to claim 1, wherein the first potential is higher than a voltage applied to a gate terminal during a high-frequency signal amplification operation.   After the activation signal rises, the voltage applied to the gate terminal of the first or second amplifying FET during the amplifying operation of the high-frequency signal and the first voltage until the signal indicating the output level rises. The high frequency power amplifier according to claim 1, wherein a voltage having a second potential different from the one potential is applied.   4. The high frequency power amplifier according to claim 3, wherein the second potential is lower than the first potential and higher than a voltage applied to a gate terminal during a high frequency signal amplification operation. A first bias FET having a gate terminal connected to the first amplifying FET; a second bias FET having a gate terminal connected to the second amplifying FET; A first current source for flowing current to the bias FET; and a second current source for flowing current to the second bias FET;
Each of the first and second amplifying FETs has a gate and a drain coupled to each other, and converts currents from the first current source and the second current source into voltages, respectively, and converts the converted voltages into the first and second current FETs. The first current source or the second current source is applied as a bias voltage to the gate terminal of the second amplification FET until the signal indicating the output level rises after the start signal rises. The high-frequency power amplifier according to claim 4, configured to flow a current larger than a current that flows during a high-frequency signal amplification operation.

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