557627 A7 __B7 五、發明説明（1) (請先閲讀背面之注意事項再填寫本頁) 本發明是關於，應用在以主從方式連接多數半導體放 大元件的多級架構的高頻電力放大電路，及裝配有此高頻 電力放大電路的攜帶式電話機等無線電通信裝置時很有效 的技術，特別是關於，可以不依存於半導體放大元件的特 性參差不齊，能夠獲得所希望特性的輸出的高頻電力放大 電路。 如第1圖所示，在汽車電話機、攜帶式電話機等的無 線通信裝置（行動通信裝置）的發送側輸出級，裝配有主從 方式連接 M〇SFET(Metal Oxide Semiconductor Field Effect TransistoO或GaAs — MESFET等半導體放大元件Ql、Q2 、Q3的多級架構的高頻電力放大電路。再者，第1圖的 高頻電力放大電路的最末級的半導體放大元件Q3常以分 散的零件（輸出電力MOSFRET等）構成，前級的半導體放 大元件Ql、Q2及偏壓電路BIAS則常是在1個半導體晶 片上構成半導體積體電路。以下，此等組合包含半導體放 大元件或偏壓電路的半導體積體電路、電容器元件等者， 稱做高頻電力放大模組或簡稱爲模組。 經濟部智慧財產局員工消費合作社印製 而在一般，攜帶式電話機是構成，可配合使用環境， 依基地局的電力位準指示信號改變輸出（發送電力）使其能 夠適應周圍環境，而進行通話，不與其他攜帶式電話機產 生干擾的系統。例如，北美的900 MHz頻帶的標準方式 或歐洲的 GSM(Global System for Mobile Communication)方 式等的蜂巢式攜帶式電話機的發送側輸出級的高頻電力放 大模組，是藉由APC(Automatic Power Control)電路的輸出 本紙張尺度適用中國國家標準（cns ) A4規格（210X297公釐） -4 - 557627 A7 B7 五、發明説明（2) 電壓Vapc控制輸出電力MOSFET Q1〜Q3的閘極偏壓， 使其成爲通話所必要的輸出電力。 (請先閲讀背面之注意事項再填寫本頁) 以往，上述輸出電力MOSFET的閘極偏壓，是使用如 第1圖所示的電阻分割電路構成的偏壓電路BIAS生成， 藉電阻R11及R12、R21與R22、R31及R32的各電阻比 分別分割APC電路的輸出電壓Vapc，以生成閘極偏壓 Vgl、Vg2、Vg3(參照，例如日本特開平1 1 - 1 50483號） 也有如第2圖所示，由串聯的多數電組R 1〜R4與二 極體接續的MOSFET Qd所構成，藉由調整各電阻的比値 ，使其能在Vapc大的2V附近獲得最大的輸出電力，而 生成各級的輸出電力MOSFET的閘極偏壓Vgl、Vg2、Vg3 的偏壓電路（參照，例如日本特開200 1 - 1 0288 1號）。 如此，上述傳統的閘極偏壓電路均是以電阻將APC 電路的輸出電力Vapc分壓，而將所產生的偏壓施加在輸 出電力MOSFET的閘極。 經濟部智慧財產局員工消費合作社印製 但是輸出電力MOSFET的啓始値電壓會因製造上的參 差不齊或溫度變動而不齊一或發生變化。而且，輸出電力 MOSFET中特別是最後級的MOSFET Q3常使用分散型的 零件。因此，最後級的MOSFET Q3與前級的MOSFET Q1 、Q2的啓始値電壓的參插不齊不相同。亦即，各輸出電 力MOSFET的閘極-汲極電流特性不相同。 而，在輸出電力MOSFET的啓始値如此有參插不齊的 高頻電力放大器模組，如上述以電阻將APC電路的輸出 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -5- 557627 經濟部智慧財產局員工绡費合竹社即製 A7 __B7_五、發明説明（3) 電力Vapc分壓，而將所產生的偏壓施加在輸出電力 MOSFET的閘極時，高頻電力放大電路的輸出特性會大幅 度偏離所希望的特性。其結果，在具有藉由電阻分割生成 閘極偏壓的偏壓電路的模組，必須微調構成偏壓電路的電 阻，明顯地會有需要多餘的修正作業及修正電阻的課題。 本發明的目的在提供，不需要調整構成偏壓電路的電 阻値，便能夠獲得所希望特性的高頻電力放大電路。 本發明的另一目的在提供，輸出的控制性良好的高頻 電力放大電路。 本發明的再一目的在提供，能以低消耗電力，高效率 獲得高輸出的高頻電力放大電路。 本發明的上述及其他目的以及新穎的特徵，可以從本 說明書的記述及附圖獲得進一步的暸解。 茲說明本案揭示的發明中具代表性者的槪要如下。 亦即，在以主從方式連接多數輸出用半導體放大元件 (Ql、Q2、Q3)的多級架構的高頻電力放大電路，具備有 ，與上述多數半導體放大元件分別構成電流鏡電路的半導 體放大元件（Qll、Q12、Q13)，對該半導體放大元件供應 隨控制電壓以一定特性變化的電流（I 11、I 1 2、I 1 3)，以 電流驅動上述多數半導體放大元件。 依據上述手段時，因輸出用半導體元件是以具有一定 特性的電流驅動，因此可以獲得，具有輸出用半導體放大 元件的啓始値電壓等特性參差不齊時也不會依存此的輸出 特性的高頻電力放大電路。 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -6 - 557627 A7 B7 五、發明説明（4) (請先閲讀背面之注意事項再填寫本頁) 而，最好是，上述半導體放大元件是場效電晶體，上 述一定特性是場效電晶體的閘極電壓-汲極電流特性。場 效電晶體的汲極電流與閘極電壓的平方成比例，因此，可 以使控制電壓在場效電晶體的啓使値電壓的附近時的輸出 的變化率小，控制電壓變大時可使輸出的變化率較大。藉 此使輸出的控制性良好，而且可以獲利較大之輸出電力。 本發明的其他發明是，備有，以主從方式連接多數輸 出用半導體放大元件（Ql、Q2、Q3)的多級架構的輸出電 路，及隨控制電壓驅動上述半導體放大元件之偏壓電路的 高頻電力放大電路，具備有，與上述多數半導體放大元件 分別構成電流鏡電路的半導體放大元件（Qll、Q12、Q13) ，上述偏壓電路包含：將控制電壓變換成電流的電壓-電 流變換電路（1 〇);將該電壓-電流變換電路所供應的電流（I 1、I 3)變換成電壓的第1電阻（R1);具有第1電流源（31) 及與該第1電流源串聯連接的第1半導體放大元件（Q32) 經濟部智慧財產局員工消費合作社印製 ;可產生相當於該第1半導體放大元件的啓始値電壓的電 壓的控制電壓生成電路（30);以及，可生成對應該控制電 壓生成電路所生成的電壓，及在上述第1電阻變換的電壓 的合成電壓的電流的第2半導體放大元件（Q21、Q31)，而 將對應流通於該第2半導體放大元件的電流（I 21)同一特 性的電流（I 11)，分別供應上述構成電流鏡電路的半導體 元件，以電流驅動上述半導體放大元件。 而且，最好是，上述控制電壓生成電路備有，以相當 於第1半導體放大元件的啓始値電壓的電壓當作輸入電壓 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 557627 A7 B7 五、發明説明（5) (請先閲讀背面之注意事項再填寫本頁) 的第1差動電路構成的電壓輸出器（33)，在該電壓輸出器 的輸出端子連接上述第1電阻（R1)，使上述電壓-電流變 換電路供應的電流（I 1、I 3)經由該第1電阻在上述電壓 輸出器內流通。藉此，由於電壓輸出器的輸出阻抗小，可 以充分引進從電壓-電流變換電路供應的電流（I 1、I 3)， 產生與經第1電阻從上述電壓-電流變換電路供給的電 流（I 1、I 3)成比例的電壓，將其施加在第2半導體放大 元件的控制端子，使電流流通。 而且，最好是配設，可引進從連接在上述第2半導體 放大元件的控制端子的上述電壓-電流變換電路供應的電 流的第2電流源（21a、。藉此，可以令由第2半導體 放大元件使其流通的電流開始變化的初期控制電壓偏移， 容易獲得所希望的電流特性。 經濟部智慧財產局員工消費合作社印製 同時，上述第1電流源（31)備有：以產生定電壓的定 電壓電路（311)的定電壓（Vref)作爲輸入的第2差動電路 (312);及藉該第2差動電路使定電流流通的第3半導體 放大元件（Q30)。藉此，不論電源電壓的參差不齊如何， 均可以使輸出用的第1半導體放大元件的電流特性保持一 定。 並且，上述第2差動電路（3 12)的輸出是經由具有放 大元件（Q44)及第2電阻（R4)的電路’回授到一方的輸入 。藉由此項回授，上述第2差動動電路從輸出端子輸出與 上述定電壓（Vref)成比例的電壓（Vcl)。上述第3半導體放 大元件（Q30)與上述放大元件（Q44)構成電流鏡電路’流通 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐1 -8- 557627 A7 B7_ 五、發明説明（6) (請先閲讀背面之注意事項再填寫本頁) 對應上述第2電阻（R4)的電組値的電流作爲定電流（I 4)。 在此，上述第2電阻（R4)以外部附設電阻構成。外部附設 電阻可以使用精密度較晶片上的元件高的元件，因此，可 以提高電路的動作精確度。 並且，上述第2電流源（21a、21c)具有：以從產生對 上述電源電壓的依存性小的定電壓的定電壓電路（3 11)的 定電壓（Vref)作爲輸入的第3差動電路（321);及藉由該第 3差動電路的輸出（Vc2)使定電流流通的第4半導體放大元 件（Q31)。藉此，縱使電源電壓參照不齊，仍可使輸出用 的第1半導體放大元件的電流特性維持一定。 經濟部智慧財產局員工消費合作社印製 同時，上述第3差動電路（321)的輸出是經由具有放 大元件（Q45)及第33電阻（R5)的電路，回授到一方的輸入 。藉由此項回授，上述第3差動動電路從輸出端子輸出與 上述定電壓（Vref)成比例的電壓（Vc2)。上述第3半導體放 大元件（Q31)與上述放大元件（Q45)構成電流鏡電路，流通 對應上述第3電阻（R5)的電組値的電流作爲定電流（I 4)， 上述第3電阻與上述第1〜第4半導體放大元件是形成 在同一半導體晶片上。藉此，當設在電壓-電流變換電路 (1 0)的電阻（R 2)的製造上的參插不齊，使輸出電流（I 1、I 3)變動時，構成第2定電流源（2 1 a、21 c)的第3電阻（R 5) 會與電壓-電流變換電路的電阻同樣的參插不齊，因此電 流（15)變動，抵消輸出電流（I 1、I 3)的變動分。 而且，對應上述多數個半導體放大元件，配設上述第 1電阻、上述第2半導體放大元件、及上述第2電流源 本紙張尺度適用中關家標準（CNS ) A4規格（21GX297公釐） ~ -9- 557627 A7 B7 五、發明説明（7) (請先閲讀背面之注意事項再填寫本頁) 對應配設的上述第1電阻的電阻値及上述第2電流源的電 流値也設定成不相同的値。藉此，對多數輸出用半導體放 大元件分別以所希望的特性個別控制，可實現，輸出的控 制性良好’同時能以低消耗電力高效率輸出的高頻電力放 大電路。 茲參照附圖，說明本發明的可取實施例如下。再者， 在以下的說明，半導體放大元件的例子是場效電晶體（FET) ，但半導體放大元件不限定爲場效電晶體，另包含雙極電 晶體、異質結雙極電晶體（HBT ·· hetero -junction bipolar transistor)、HEMT(high-electron-mobility transistor)等， 而形成電晶體的半導體基板也不限定爲矽基板，也包含 矽-鍺基板、或鎵-砷基板等。 經濟部智慧財產局員工消費合作社印製 第3圖表示本發明的高頻電力放大電路的一個實施例 。在第3圖，Ql、Q2、Q3是作爲輸出用電晶體的輸出電 力MOSFET，此等輸出電力MOSFET Ql、Q2、Q3是連接 於前級的FET的汲極端子，並經由電容元件c 1、C2連接 於下一級的F E T的閘極端子。同時，初級的輸出電力 MOSFET Q1的閘極端子是經由電容元件C0輸入高頻信號 RF in，最後級的輸出電力MOSFET Q3的汲極端子是經由 電容元件C3連接在輸出端子OUT，切斷高頻信號RF in 的直流成分，僅放大交流成分輸出。而這時的輸出電力是 由以下說明的偏壓電路控制。 在本實施例，與上述各輸出電力MOSFET Ql、Q2、 Q 3並聯，分別設有閘極與汲極相結合的所謂二極體接續 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -10- 557627 A7 _B7_ 五、發明説明（8) (請先聞讀背面之注意事項再填寫本頁) 的 MOSFET Qll、Q12、Q13，各 MOSFET Qll、Q12、Q13 與上述各輸出電力MOSFET Ql、Q2、Q3相互間的閘極共 同連接在一起，而構成電流鏡電路。 再者，第3圖的高頻電力放大電路是，最後級的輸出 電力MOSFET Q3，與Q3 —起構成電流鏡電路的MOSFET Q13的兩個FET形成在1個半導體晶片上的分散型的零件 ，前級的輸出電力MOSFET Ql、Q2及與此構成電流鏡電 路的MOSFET Ql 1、Q12，及使偏壓電流流過MOSFET Ql 1 〜Q13的偏壓電路在另一個半導體晶片上構成半導體積體 電路。而，電容元件CO、Cl、C2是使用分散的零件，以 外加方式連接在包含上述偏壓電路的半導體積體電路。 經濟部智慧財產局員工消費合作社印製 上述偏壓電路是由，能輸出與控制電壓Vapc成比例 的電流I 1、I 3的電壓-電流變換電路10 ;依據該電流 I 1、I 3生成沒有啓始値依存性的所希望特性的電流，使 其流通於上述電流鏡用MOSFET Qll、Q12、Q13的電流 生成電路20A、20B、20C ;及生成對此等電流生成電路 20A〜20C的偏壓，由上述電流生成電路20A〜20C輸出 依照一定特性的電流的閘極電壓控制電路30，所構成。 上述電流生成電路20A及20C具有相同的電路架構 。雖未特別限制，但在本實施例，生成流通於跟第2級的 輸出電力MOSFET Q2形成電流鏡接續的MOSFET Q12的 電流I 12的電流生成電路20B，是由跟上述電流生成電路 20A的輸出MOSFET Q22電流鏡接續的MOSFET Q20所構 成，從MOSFET Q20生成極性與上述電流生成電路20A供 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -11 - 557627 A7 B7 五、發明説明（9) (請先閱讀背面之注意事項再填寫本頁) 給MOSFET Q11的電流I u相同的電流ί 12。上述電流 I 1 1與I 12的比値，可以藉由改變上述m〇SFET Q22與 Q20的尺寸比加以調整。 閘極電壓控制電路30是由流通電源依存性少的電流 的定電流源31 ;與該定電流源31串聯的MOSFET Q32 ; 接受該MOSFET Q32的汲極電壓而成電壓輸出器動作的差 動放大器33 ;所構成。在此，上述MOSFET Q32因採閘 極與汲極相結合的所謂二極體接續，因此，從汲極端子向 差動放大器33輸出相當於其啓始値電壓Vgsl的電壓，差 動放大器3 3則輸出與輸入電壓同一位準的電壓，亦即， 輸出與MOSFET Q32的啓始値電壓Vgsl同一位準的電壓 〇 經濟部智慧財產局員工消費合作社印製 電流生成電路20A是由：源極跟隨型的MOSFET Q21 ;連接在該MOSFET Q21的閘極與上述閘極電壓控制電路 30的差動放大器33的輸出端子間的電阻R1 ;連接在該 MOSFET Q21的閘極端子與接地點間的使定電流I 5a流通 的定電流源21a ;串聯在上述MOSFET Q21的汲極端子與 電源電壓端子Vdd間的MOSFET Q22 ;閘極相互連接而與 該MOSFET Q22構成電流鏡電路的MOSFET Q23 ;所構成 〇 用以供應對應從上述電壓-電流變換電路1 0輸出的上 述控制電壓Vapc的電流I 1的配線的終端，結合在上述 電阻R1與MOSFET Q21的閘極端子的連接節點η 1。藉此 ，從上述電壓-電流變換電路10的電流I 1在I 1 > I 5a 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -12- 557627 A7 B7 五、發明説明（i]b (請先閲讀背面之注意事項再填寫本頁) 時是分配至上述定電流源21a與差動放大器33的輸出端 子而流動，I 1 < I 5 a時則全部流進定電流源2 1 a。同時， 在I 1< I 5a時，有相當於（I 5a - I 1)的電流從差動放大器 33的輸出端子經過R1流向定電流源21a。 其次說明，電流生成電路20A的動作。 首先，假定電流生成電路20A沒有定電流源21a。電 壓-電流變換電路10的電流I 1經由電阻R 1從差動放大 器33的輸出端子流進放大器內部。而，差動放大器33的 輸出電壓是如上述與MOSFET Q32的啓始値電壓Vgsl同 一位準。因此，MOSFET Q21的閘極電壓VG2成爲較差動 放大器33的輸出電壓Vgsl高出R 1 · I 1的電壓（Vgsl + R 1 · I 1)。在此，從電壓-電流變換電路10供給的電流 I 1是如上述，與控制電壓Vapc成比例。 經濟部智慧財產局員工消費合作社印製 因此，MOSFET Q21的閘極電壓VG2是如第4圖以記 號A表示，與電壓Vapc成比例，大致上成直線變化。於 是，在MOSFET Q21流通的電流I 21將依MOSFET的汲 極電流特性，對應控制電壓Vapc如第5圖的記號a變化 。在此，上述MOSFETQ32與Q21因爲是形成在1片半導 體晶片上，因此，啓始値電壓的參差不齊相同。亦即， Q32的啓始値電壓昇高時，Q21的啓始値電壓也同樣昇高 相同値，Q32的啓始値電壓降低時，Q21的啓始値電壓也 同樣降低相同値。 其結果，流通於MOSFET Q21的電流I 21將與啓始 値電壓的參差不齊無關，以特定的特性變化。而，此項電 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -13- 557627 A7 B7 五、發明説明（1)1 (請先閲讀背面之注意事項再填寫本頁) 流I 21則經由MOSFET Q22、Q23及Qll、Q1的兩個電流 鏡電路，流至輸出電力MOSFET Q1。因此’在輸出電力 MOSFET Q1會有電流特性與MOSFET Q21的汲極電流特 性相同的電流流通。亦即，縱使起因於處理程序的參差不 齊或溫度變化使MOSFET Q1的啓始値電壓偏離所希望的 値，仍可以獲得不依存處理程序或溫度變化的輸出特性。 另一方面，若考慮流通於定電流源21a的電流I 5 a 時，藉由此電流I 5a從電壓-電流變換電路10經由電阻 R1流進差動放大器33內部的電流會減少，因此， M0SFETQ21 的閘極電壓 VG2 成爲 Vgsl + R 1· I 1 - R1 • I 5a。亦即，有定電流源21a時的MOSFET Q21的閘極 電壓VG2成爲如第4圖的記號B所示，將直線A向下挪 R 1 · I 5 a的直線。 經濟部智慧財產局員工消費合作社印製 在此，流通於定電流源2 1 a的電流I 5 a不論控制電 壓Vapc如何維持一定値。而，從電壓-電流變換電路1〇 供應的電流I 1與控制電壓Vapc成比例。因此，直線B 的斜度與直線A的斜度相同。藉此，流通於MOSFET Q21 的電流I 21將對應控制電壓Vapc隨第5圖以記號b所示 的曲線變化。第4圖的直線A、B的斜度可以藉由電阻R1 的値來調整，R1較小時，可使直線A、B的斜度較小，因 此，可以提高藉由控制電壓Vapc對輸出用電力MOSFET Q1〜Q3的控制性。 電流生成電路20C與電流生成電路20A同樣由：源 極跟隨型的MOSFET Q31 ;連接在該MOSFET Q31的閘極 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -14- 經濟部智慧財產局員工消費合作社印製 557627 A7 B7 五、發明説明（也 與上述閘極電壓控制電路30的差動放大器33的輸出端子 間的電阻R3 ;連接在該MOSFET Q31的閘極端子與接地 點間的流通定電流I 5c的定電流源21c ;串聯在上述 MOSFET Q31的汲極端子與電源電壓端子Vdd間的 MOSFET Q32 ;閘極相互連接而與該MOSFET Q32構成電 流鏡電路的MOSFET Q33 ;所構成。定電流源21c的電流 I 15c與電阻R3的値設定成，與電流生成電路20A的定電 流源21 a的電流I 1 5a與電阻R1的値不相同的値。 因此，MOSFET Q31的閘極電壓VG3將依第4圖以記 號C所示的直線變化。其結果，汲極電流，亦即，在 MOSFET Q13、 Q3流通的偏壓電流I 13將具有如第5圖的 記號c所示的特性。若適當設定電流生成電路20B的定電 流源21c的電流I 15c與電阻R3的値，及電流生成電路 20A的定電流源21a的電流I 15a與電阻R1的値，便能夠 以很小的動作電流獲得很大的輸出。 再者，在第1圖的實施例的篇壓電路，是僅以跟電流 生成電路20A的MOSFET Q22成鏡面接續的MOSFET Q20 ，構成生成第2級的輸出MOSFET Q2的偏壓電流的電流 生成電路20B，但也可以使電流生成電路20B的架構與電 流生成電路20A相同，依使用的輸出MOSFET Q1〜Q3， 分別適當設定相當於定電流源21a的電流源的電流及電阻 R1的値，便能夠使整體模組的特性成爲所希望的特性。 第6圖表示依據控制電壓Vapc生成供給電流生成電 路20A、20C的電流I 1、I 3的電壓-電流變換電路10的 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)557627 A7 __B7 V. Description of the invention (1) (Please read the precautions on the back before filling out this page) The present invention relates to a high-frequency power amplifier circuit with a multi-stage architecture that is connected to most semiconductor amplifier elements in a master-slave manner. It is a very effective technology for radio communication devices such as portable telephones equipped with this high-frequency power amplifier circuit, and in particular, it is possible to obtain a high-frequency output having a desired characteristic without depending on the characteristics of the semiconductor amplifying element. Power amplifier circuit. As shown in Fig. 1, a transmission stage of a wireless communication device (mobile communication device) such as a car phone or a portable phone is equipped with a master-slave method to connect a metal oxide semiconductor field effect transistor or GaAs-MESFET. The high-frequency power amplifier circuit with a multi-stage structure such as the semiconductor amplifier elements Q1, Q2, and Q3. Moreover, the semiconductor amplifier element Q3 at the last stage of the high-frequency power amplifier circuit in FIG. 1 is often composed of discrete components (output power MOSFRET Etc.), the semiconductor amplifier elements Q1 and Q2 of the previous stage and the bias circuit BIAS often constitute a semiconductor integrated circuit on a semiconductor wafer. Hereinafter, these combinations include semiconductor amplifier elements or semiconductors of the bias circuit. Integrated circuits, capacitor elements, etc. are called high-frequency power amplifier modules or modules for short. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, in general, portable telephones are composed, which can be used in conjunction with the environment and according to the base. The station ’s power level indicator signal changes the output (sends power) so that it can adapt to the surrounding environment, while talking, A system that interferes with other portable telephones. For example, the high-frequency power amplifier module of the transmission side output stage of the cellular portable telephone, such as the standard method of the 900 MHz band in North America or the GSM (Global System for Mobile Communication) method in Europe. ， It is through the output of APC (Automatic Power Control) circuit. The paper size is applicable to Chinese national standard (cns) A4 specification (210X297 mm) -4-557627 A7 B7 V. Description of the invention (2) Voltage Vapc control output power MOSFET Q1 The gate bias of ~ Q3 makes it the output power necessary for the call. (Please read the precautions on the back before filling this page) In the past, the gate bias of the output power MOSFET was used as shown in Figure 1. The bias circuit BIAS generated by the shown resistor division circuit is generated, and the output voltage Vapc of the APC circuit is divided by the respective resistance ratios of the resistors R11 and R12, R21 and R22, R31 and R32 to generate the gate bias voltages Vgl, Vg2, Vg3 (see, for example, Japanese Patent Application Laid-Open Nos. 1 1-1 and 50483), as shown in FIG. 2, is also composed of a plurality of MOSFETs Qd connected in series with a plurality of electric groups R 1 to R4 and a diode. The ratio of each resistor is adjusted so that it can obtain the maximum output power near 2V where Vapc is large, and generate the bias circuits Vgate, Vg2, Vg3 of the output power MOSFETs at each level (refer to, for example, Japan JP 200 1-1 0288 No. 1). In this way, the above-mentioned conventional gate bias circuit divides the output power Vapc of the APC circuit with a resistor, and applies the generated bias to the gate of the output power MOSFET. pole. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. However, the initial voltage of the output power MOSFET may vary or vary due to manufacturing variations or temperature changes. Furthermore, among the output power MOSFETs, especially the last-stage MOSFET Q3, discrete components are often used. Therefore, the starting voltage of the MOSFET Q3 of the last stage is different from that of the MOSFETs Q1 and Q2 of the previous stage. That is, the gate-drain current characteristics of each output power MOSFET are different. However, at the beginning of the output power MOSFET, there are such a high-frequency power amplifier module that is unevenly inserted, as described above, the output of the APC circuit with resistance is based on the Chinese paper standard (CNS) A4 (210X297 mm). -5- 557627 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, A7 __B7_, made by Fezhu Bamboo Co., Ltd. V. Description of the invention (3) When the power Vapc is divided, and the generated bias voltage is applied to the gate of the output power MOSFET, the voltage is high. The output characteristics of a high-frequency power amplifier circuit may greatly deviate from desired characteristics. As a result, in a module having a bias circuit that generates a gate bias voltage by resistance division, it is necessary to fine-tune the resistance constituting the bias circuit, and there is obviously a problem that an unnecessary correction operation and a resistance correction are required. An object of the present invention is to provide a high-frequency power amplifier circuit capable of obtaining desired characteristics without adjusting the resistor 构成 constituting the bias circuit. Another object of the present invention is to provide a high-frequency power amplifier circuit with excellent output controllability. Another object of the present invention is to provide a high-frequency power amplifier circuit capable of obtaining high output with low power consumption and high efficiency. The above and other objects and novel features of the present invention can be further understood from the description of the present specification and the accompanying drawings. The summary of the representative among the inventions disclosed in this application is as follows. That is, a high-frequency power amplifier circuit of a multi-stage structure in which a plurality of output semiconductor amplification elements (Q1, Q2, Q3) are connected in a master-slave manner is provided with a semiconductor amplifier that constitutes a current mirror circuit separately from the above-mentioned plurality of semiconductor amplification elements. The device (Q11, Q12, Q13) supplies a current (I 11, I 1 2, I 1 3) with a certain characteristic that varies with the control voltage to the semiconductor amplifying device, and drives most of the semiconductor amplifying devices with a current. According to the above method, since the output semiconductor element is driven by a current having a certain characteristic, it can be obtained that even if the characteristics such as the start-up voltage of the output semiconductor amplifying element are uneven, the output characteristic does not depend on the high output characteristics. Frequency power amplifier circuit. (Please read the precautions on the back before filling out this page) The paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) -6-557627 A7 B7 V. Description of the invention (4) (Please read the notes on the back first Please fill in this page for more details.) Preferably, the semiconductor amplifying element is a field effect transistor, and the certain characteristic is the gate voltage-drain current characteristic of the field effect transistor. The drain current of a field effect transistor is proportional to the square of the gate voltage. Therefore, the rate of change of the output when the control voltage is near the start-up voltage of the field effect transistor can be made small. The rate of change of the output is large. As a result, the output controllability is good, and large output power can be obtained. Other inventions of the present invention include an output circuit of a multi-stage structure in which a plurality of output semiconductor amplification elements (Ql, Q2, Q3) are connected in a master-slave manner, and a bias circuit that drives the semiconductor amplification elements with a control voltage. The high-frequency power amplifying circuit includes semiconductor amplifying elements (Q11, Q12, Q13) constituting a current mirror circuit separately from most of the semiconductor amplifying elements. The bias circuit includes a voltage-current that converts a control voltage into a current. A conversion circuit (10); a first resistor (R1) that converts the current (I1, I3) supplied by the voltage-current conversion circuit into a voltage; and has a first current source (31) and the first current The first semiconductor amplifying element (Q32) connected in series with the source is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs; a control voltage generating circuit (30) capable of generating a voltage equivalent to the initial voltage of the first semiconductor amplifying element; and A second semiconductor amplifying element (Q21, Q31) capable of generating a current corresponding to the voltage generated by the control voltage generating circuit and the combined voltage of the voltage converted by the first resistance, and Currents (I 11) corresponding to the same characteristics of the current (I 21) flowing through the second semiconductor amplifying element are supplied to the semiconductor elements constituting the current mirror circuit, and the semiconductor amplifying elements are driven by current. In addition, it is preferable that the control voltage generating circuit is provided with a voltage equivalent to a starting voltage of the first semiconductor amplifying element as an input voltage. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). 557627 A7 B7 V. Description of the invention (5) (Please read the precautions on the back before filling this page) The voltage output device (33) composed of the first differential circuit, and the output terminal of this voltage output device is connected to the above first The resistor (R1) causes a current (I1, I3) supplied from the voltage-current conversion circuit to flow in the voltage output device via the first resistor. Thereby, since the output impedance of the voltage output device is small, the current (I 1, I 3) supplied from the voltage-current conversion circuit can be sufficiently introduced, and the current (I) supplied from the voltage-current conversion circuit through the first resistor is generated. 1. I 3) A proportional voltage is applied to the control terminal of the second semiconductor amplifying element to cause a current to flow. Furthermore, it is preferable to provide a second current source (21a, which can supply a current supplied from the voltage-current conversion circuit connected to the control terminal of the second semiconductor amplifying element. This allows the second semiconductor The amplifying element shifts the control voltage at the initial stage when the current flowing through it changes, and it is easy to obtain the desired current characteristics. At the same time, it is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. A second differential circuit (312) whose input is a constant voltage (Vref) of the constant voltage circuit (311) of the voltage; and a third semiconductor amplifying element (Q30) through which the constant current flows through the second differential circuit. The current characteristics of the first semiconductor amplifying element for output can be kept constant regardless of the variation of the power supply voltage. In addition, the output of the second differential circuit (3 12) is provided by the amplifier element (Q44) and The circuit of the second resistor (R4) is fed back to one input. With this feedback, the second differential circuit outputs a voltage (Vcl) proportional to the constant voltage (Vref) from the output terminal. The third semiconductor amplifying element (Q30) and the aforesaid amplifying element (Q44) constitute a current mirror circuit. The size of this paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm 1 -8- 557627 A7 B7_ V. Description of the invention ( 6) (Please read the precautions on the back before filling out this page) The current corresponding to the electrical resistance of the second resistor (R4) is used as the constant current (I 4). Here, the second resistor (R4) is provided externally. Resistor structure. Externally attached resistors can use components with higher precision than those on the chip, so that the circuit's operation accuracy can be improved. In addition, the second current source (21a, 21c) has: A third differential circuit (321) whose input is a constant voltage (Vref) of a constant voltage constant voltage circuit (3 11) having a small dependency; and a constant current is made by an output (Vc2) of the third differential circuit The fourth semiconductor amplifying element (Q31) in circulation. In this way, the current characteristics of the first semiconductor amplifying element for output can be maintained even if the power supply voltage is not referenced. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs At this time, the output of the third differential circuit (321) is fed back to one of the inputs via a circuit having an amplifying element (Q45) and a 33rd resistor (R5). With this feedback, the third differential The dynamic circuit outputs a voltage (Vc2) proportional to the constant voltage (Vref) from the output terminal. The third semiconductor amplifying element (Q31) and the amplifying element (Q45) constitute a current mirror circuit, and the corresponding third resistance (R5) flows The current of the electric group 値 is a constant current (I 4), and the third resistor and the first to fourth semiconductor amplifying elements are formed on the same semiconductor wafer. Thereby, when the manufacturing of the resistor (R 2) of the voltage-current conversion circuit (1 0) is inconsistent, and the output currents (I 1 and I 3) are changed, a second constant current source ( 2 1 a, 21 c) The third resistance (R 5) will be inserted in the same way as the resistance of the voltage-current conversion circuit, so the current (15) changes to offset the change in the output current (I 1, I 3). Minute. In addition, corresponding to the above-mentioned many semiconductor amplifying elements, the first resistor, the second semiconductor amplifying element, and the second current source are provided. The paper size of this paper applies the Zhongguan Standard (CNS) A4 specification (21GX297 mm) ~- 9- 557627 A7 B7 V. Description of the invention (7) (Please read the precautions on the back before filling out this page) The resistance of the above-mentioned first resistor 値 and the current of the second current source 値 are also set differently.値. Thereby, a plurality of output semiconductor amplifier elements can be individually controlled with desired characteristics, and a high-frequency power amplifier circuit capable of outputting high controllability with low power consumption and high efficiency can be realized. A preferred embodiment of the present invention will be described below with reference to the drawings. Furthermore, in the following description, an example of a semiconductor amplifying element is a field effect transistor (FET), but the semiconductor amplifying element is not limited to a field effect transistor, and includes a bipolar transistor and a heterojunction bipolar transistor (HBT · · Hetero-junction bipolar transistor (HEMT), high-electron-mobility transistor (HEMT), etc., and the semiconductor substrate forming the transistor is not limited to a silicon substrate, but also includes a silicon-germanium substrate or a gallium-arsenic substrate. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs FIG. 3 shows an embodiment of the high-frequency power amplifier circuit of the present invention. In FIG. 3, Ql, Q2, and Q3 are output power MOSFETs as output transistors. These output power MOSFETs Ql, Q2, and Q3 are drain terminals of the FETs connected to the preceding stage, and pass through the capacitive elements c1, C2 is connected to the gate terminal of the next-stage FET. At the same time, the gate terminal of the output power MOSFET Q1 at the primary stage inputs the high-frequency signal RF in via the capacitive element C0, and the drain terminal of the output power MOSFET Q3 at the final stage is connected to the output terminal OUT via the capacitor element C3 to cut off the high frequency. The DC component of the signal RF in only amplifies the AC component output. The output power at this time is controlled by a bias circuit described below. In this embodiment, the so-called diodes connected to the output power MOSFETs Q1, Q2, and Q3 in parallel are provided with a gate and a drain, respectively. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297). ) -10- 557627 A7 _B7_ V. Description of the invention (8) (Please read the precautions on the back before filling this page) MOSFET Qll, Q12, Q13, each MOSFET Qll, Q12, Q13 and each of the above output power MOSFETs The gates of Q1, Q2, and Q3 are connected together to form a current mirror circuit. In addition, the high-frequency power amplifier circuit of FIG. 3 is a decentralized component in which the two output MOSFETs Q3 of the last stage and Q3 together form the MOSFET Q13 of the current mirror circuit on one semiconductor wafer. The output power MOSFETs Q1 and Q2 of the previous stage, and the MOSFETs Ql 1, Q12 constituting the current mirror circuit, and the bias circuit that causes a bias current to flow through the MOSFETs Ql 1 to Q13 constitute a semiconductor integrated body on another semiconductor wafer. Circuit. The capacitor elements CO, Cl, and C2 are connected to a semiconductor integrated circuit including the bias circuit in an external manner using discrete components. The above-mentioned bias circuit is printed by the staff consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, which is a voltage-current conversion circuit 10 that can output currents I 1 and I 3 proportional to the control voltage Vapc; generated based on the currents I 1 and I 3 The current without the desired characteristics of the initial dependency depends on the current generating circuits 20A, 20B, and 20C flowing through the current mirror MOSFETs Q11, Q12, and Q13; and generating biases for these current generating circuits 20A to 20C. The voltage is formed by the gate voltage control circuit 30 that outputs a current according to a certain characteristic in the current generating circuits 20A to 20C. The current generating circuits 20A and 20C have the same circuit architecture. Although not particularly limited, in this embodiment, the current generating circuit 20B that generates the current I 12 flowing through the MOSFET Q12 connected to the second-stage output power MOSFET Q2 to form a current mirror is the output of the current generating circuit 20A. MOSFET Q22 is composed of MOSFET Q20 connected to current mirror, generating polarity from MOSFET Q20 and the above current generating circuit 20A for this paper. Applicable to China National Standard (CNS) A4 specification (210X297 mm) -11-557627 A7 B7 V. Description of the invention (9) (Please read the precautions on the back before filling out this page) The same current I u for the MOSFET Q11 is 12. The ratio 値 of the current I 1 1 to I 12 can be adjusted by changing the size ratio of the above MOSFETs Q22 and Q20. The gate voltage control circuit 30 is a constant current source 31 that circulates a current with little dependence on the power source; a MOSFET Q32 connected in series with the constant current source 31; and a differential amplifier that operates as a voltage output device by receiving the drain voltage of the MOSFET Q32. 33; constituted. Here, the above-mentioned MOSFET Q32 is connected by a so-called diode that combines a gate and a drain. Therefore, a voltage equivalent to its initial voltage Vgsl is output from the drain terminal to the differential amplifier 33. The differential amplifier 3 3 The output voltage is at the same level as the input voltage, that is, the output voltage is at the same level as the starting voltage Vgsl of the MOSFET Q32. The current generation circuit 20A printed by the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is: MOSFET Q21; resistor R1 connected between the gate of the MOSFET Q21 and the output terminal of the differential amplifier 33 of the gate voltage control circuit 30; connection between the gate terminal of the MOSFET Q21 and the ground The constant current source 21a through which the current I 5a flows; the MOSFET Q22 connected in series between the drain terminal of the MOSFET Q21 and the power supply voltage terminal Vdd; the MOSFET Q23 whose gates are connected to form a current mirror circuit with the MOSFET Q22; The terminal of the wiring for supplying the current I 1 corresponding to the control voltage Vapc output from the voltage-current conversion circuit 10 is connected to the connection between the resistor R1 and the gate terminal of the MOSFET Q21. Node η 1. With this, the current I 1 from the voltage-current conversion circuit 10 is above I 1 > I 5a. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -12- 557627 A7 B7 V. Description of the invention ( i] b (please read the precautions on the back before filling this page). It flows to the output terminals of the constant current source 21a and differential amplifier 33 described above. When I 1 < I 5 a, all the constant current flows. Source 2 1 a. At the same time, when I 1 < I 5a, a current corresponding to (I 5a-I 1) flows from the output terminal of the differential amplifier 33 to the constant current source 21a through R1. Next, the current generating circuit 20A First, it is assumed that the current generating circuit 20A does not have a constant current source 21a. The current I 1 of the voltage-current conversion circuit 10 flows from the output terminal of the differential amplifier 33 into the amplifier via the resistor R 1. The output voltage is at the same level as the starting voltage Vgsl of the MOSFET Q32 as described above. Therefore, the gate voltage VG2 of the MOSFET Q21 becomes a voltage higher than the output voltage Vgsl of the differential amplifier 33 by R 1 · I 1 (Vgsl + R 1 · I 1). Here, the voltage-current The current I 1 supplied by the switching circuit 10 is as described above, and is proportional to the control voltage Vapc. It is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Therefore, the gate voltage VG2 of the MOSFET Q21 is represented by the symbol A in FIG. Vapc is proportional and changes approximately linearly. Therefore, the current I 21 flowing in the MOSFET Q21 will change according to the drain current characteristic of the MOSFET and the corresponding control voltage Vapc will change as the symbol a in Figure 5. Here, the above-mentioned MOSFETs Q32 and Q21 are It is formed on a single semiconductor wafer, so the variation of the start voltage is different. That is, when the start voltage of Q32 is increased, the start voltage of Q21 is also increased by the same. When the starting voltage decreases, the starting voltage of Q21 also decreases by the same amount. As a result, the current I 21 flowing through the MOSFET Q21 will change with a specific characteristic regardless of the variation of the starting voltage. However, this The paper size of this item applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) -13- 557627 A7 B7 V. Description of the invention (1) 1 (Please read the notes on the back before filling this page) Stream I 21 via The two current mirror circuits of MOSFETs Q22, Q23 and Q11 and Q1 flow to the output power MOSFET Q1. Therefore, a current having the same current characteristics as the drain current characteristics of the MOSFET Q21 flows in the output power MOSFET Q1. That is, even if the variation in the processing program or the temperature change causes the initial voltage of the MOSFET Q1 to deviate from the desired voltage, the output characteristics can be obtained without depending on the processing program or temperature change. On the other hand, if the current I 5 a flowing through the constant current source 21 a is considered, the current flowing from the voltage-current conversion circuit 10 through the resistor R1 into the differential amplifier 33 is reduced by the current I 5a. Therefore, M0SFETQ21 The gate voltage VG2 becomes Vgsl + R 1 · I 1-R1 • I 5a. That is, the gate voltage VG2 of the MOSFET Q21 when the constant current source 21a is present is a straight line that moves the straight line A downward by R 1 · I 5 a as shown by the symbol B in FIG. 4. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Here, the current I 5 a flowing through the constant current source 2 1 a is maintained constant regardless of the control voltage Vapc. The current I 1 supplied from the voltage-current conversion circuit 10 is proportional to the control voltage Vapc. Therefore, the slope of the straight line B is the same as the slope of the straight line A. As a result, the current I 21 flowing through the MOSFET Q21 changes the corresponding control voltage Vapc with the curve shown by the symbol b in FIG. 5. The slope of the straight lines A and B in Figure 4 can be adjusted by the resistance of the resistor R1. When R1 is small, the slope of the straight lines A and B can be made smaller. Therefore, the output voltage can be increased by the control voltage Vapc. Controllability of power MOSFETs Q1 to Q3. The current generating circuit 20C and the current generating circuit 20A are similarly composed of: a source-follower MOSFET Q31; a gate connected to the MOSFET Q31; the paper size of the paper applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) -14- Ministry of Economic Affairs Printed by the Intellectual Property Bureau employee consumer cooperative 557627 A7 B7 V. Description of the invention (also the resistance R3 between the output terminals of the differential amplifier 33 of the above-mentioned gate voltage control circuit 30; connected to the gate terminal and ground point of the MOSFET Q31 A constant current source 21c that transmits a constant current I 5c between them; a MOSFET Q32 connected in series between the drain terminal of the above-mentioned MOSFET Q31 and the power supply voltage terminal Vdd; a MOSFET Q33 whose gates are connected to form a current mirror circuit with the MOSFET Q32; The current I 15c of the constant current source 21c and the resistor R3 are set to be different from the current I 1 5a of the constant current source 21a of the current generation circuit 20A and the resistor R1. Therefore, the gate of the MOSFET Q31 The pole voltage VG3 will change in a straight line as indicated by the symbol C in FIG. 4. As a result, the drain current, that is, the bias current I 13 flowing through the MOSFETs Q13 and Q3 will have the symbol c shown in FIG. 5. Characteristics. If the current I 15c of the constant current source 21c of the current generating circuit 20B and the resistance of the resistor R3 and the current I 15a of the constant current source 21a of the current generation circuit 20A and the resistance of the resistor R1 are appropriately set, the The operating current obtains a large output. In addition, in the example circuit of FIG. 1, the MOSFET Q20 mirror-connected to the MOSFET Q22 of the current generating circuit 20A constitutes a second-stage output MOSFET. The current generating circuit 20B for the bias current of Q2, but the structure of the current generating circuit 20B may be the same as that of the current generating circuit 20A. Depending on the output MOSFETs Q1 to Q3 used, the current source corresponding to the constant current source 21a is appropriately set. The current and the resistance of the resistor R1 can make the characteristics of the overall module into desired characteristics. Figure 6 shows a voltage-current conversion circuit that generates currents I 1 and I 3 to the current generating circuits 20A and 20C based on the control voltage Vapc. This paper size of 10 is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page)
-15- 557627 A7 B7 五、發明説明（1)3 具體例子。 (請先閱讀背面之注意事項再填寫本頁) 本實施例的電壓-電流變換電路10是由：以控制電壓 Vapc作爲輸入的CMOS差動放大電路構成的差動放大器 11 ;該差動放大器1 1的反轉輸出節點的電位施加在閘極 端子的 MOSFET Q41、Q42、Q43 ;及跟 MOSFET Q41 串聯 的電阻R2 ;所構成，因爲，MOSFET Q41與電阻R2的連 接節點的電位回授到差動放大器11的另一方的端子，分 別使MOSFET Q42及Q43流通與輸入電壓Vapc成比例的 汲極電流。而，此Q42與Q43的汲極電流可以依MOSFET Q41與Q42的尺寸比（閘極寬度W的比）與電阻R2的値， 及Q41與Q43的尺寸比與電阻R2的値，分別任意設定， 而以此作爲供給電流生成電路20A、20C的電流I 1、I 3 而輸出。 經濟部智慧財產局員工消費合作社印製 第7圖表示構成上述閘極電壓控制電路30的定電流 源3 1的定電流電路的具體例子。本實施例的定電流電路 (31)是由：可產生電源依存性小的基準電壓Vref的頻帶間 隙基準電路3 11 ;以該頻帶間隙基準電路3 11的基準電壓 Vref作爲輸入，由一方的輸入接受的差動電路312;在其 閘極接受該差動電路312的輸出的MOSFET Q44 ;連接在 該Q44與接地點間的電阻R4 ;在其閘極端子接受差動電 路312的輸出電壓Vcl的MOSFET Q30 ;所構成，而由 Q44與電阻R4的連接點回授到差動電路312的另一方輸 入。 在第7圖的定電流電路（31)，上述差動電路312的輸 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -16- 557627 A7 ____B7_ 五、發明説明（分 (請先閲讀背面之注意事項再填寫本瓦) 出經由具有MOSFET Q44與R4的電路，回授到另一方的 輸入。藉此，可以從差動電路3 1 2的輸出端子獲得對應電 阻R4的値的定電壓Vcl。同時，此定電壓Vcl也供給 MOSFET Q30 的聞極，因此，MOSFET Q30 與 MOSFET Q44 構成電流鏡電路。因之，上述MOSFET Q30將對應上述電 阻R2之値的電流作爲電流I 4使其流通。在本實施例， 上述電阻R2使用附設在外部的電阻元件。藉此，較之使 用形成在晶片上的電阻，可以輸出精度較高的電流I 4。 經濟部智慧財產局員工消費合作社印製 第8圖表示構成上述電流生成電路20 A (20C)的定電 流源21a (21〇的定電流電路的具體例子。本實施例的定 電流電路（21a、21c)是由：以跟上述定電流電路（31)共同 的頻帶間隙基準電路311輸出的基準電壓Vref作爲輸入 的差動電路321 ;接受該差動電路321的輸出的MOSFET Q45 ;連接在該Q45與接地間的電阻R5 ;在閘極端子接受 差動電路321的輸出電壓Vc2的MOSFET Q31 ;與該Q31 串聯的MOSFET Q32 ;與該Q32連接成電流鏡的MOSFET Q33 ;所構成，而從上述MOSFET Q45與電阻R5的連接 點向差動電路321的輸入進行回授。 在第8圖的定電流電路21a (21c)，上述差動電路321 的輸出經由具有MOSFET Q45與R5的電路，回授到其輸 入。藉此，可以從差動電路3 2的輸出端子獲得對應電阻 R5的電阻値的定電壓Vc2。同時，此定電壓Vc2也供給 MOSFET Q3 1 的聞極，因此，MOSFET Q45 與 MOSFET Q31 構成電流鏡電路，在MOSFET Q31流通對應上述電阻R5 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -17- 557627 A7 B7 五、發明説明（作 (請先閱讀背面之注意事項再填寫本頁) 的電阻値的電流。流通於此MOSFET Q31的汲極電流由構 成電流鏡電路的MOSFET Q32、Q33加以複製，使Q33有 定電流I 5a (I 5c)流通。 再者，本實施例的定電流電路，與第7圖所示的使定 電流I 4流通的定電流源3 1不同，上述電阻R5不是使用 外部附加的元件，而是使用形成在晶片內部的電阻。藉此 ，當設在第6圖所示的電壓-電流變換電路10的電阻R2 的製造上的參差不齊使電流I 1、I 3變動時，構成第8圖 的定電流電路21 a(21c)的電阻R5與電壓-電流變換電路 10內的電阻R2同樣會參差不齊，因此，輸出電流I 5a會 變動而抵消從上述電壓-電流變換電路10輸出的電流I 1 、I 3的變動分。 再者，上述差動電路312、321雖不特別限制，但是 ，是由一對差動電晶體Qpl、Qp2，構成其負荷電路的電 流鏡電晶體Qcl、Qc2及定電流元件I所構成。 第9圖是表示裝配第3圖的高頻電力放大電路的行動 電話（攜帶式電話機）的一部分的電路方塊圖。 經濟部智慧財產局員工消費合作社印製 攜帶式電話機是如第9圖所示，在高頻電力放大器模 組1的輸入端子（Pin)輸入調變用的振盪器（VC〇）70的振盪 動作生成的RF發送信號。RF發送信號在高頻電力放大器 模組1放大後從輸出端子（Pout)輸出，經由電力檢測電路 71、發送濾波器72、到達天線73，從天線73成爲電波發 送出去。 另一方面，由天線73接收到的RF接收信號則在接 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -18- 557627 A7 B7 五、發明説明（life (請先閱讀背面之注意事項再填寫本頁) 收電路80予以信號處理。並從接收電路80輸出接收強度 信號SRI，以A / D變換器81變換成數位信號，供給控制 邏輯82。控制邏輯82輸出電力位準指示信號SPL，供給 輸出位準控制電路83的邏輯電路84。此邏輯電路84將 送來的輸出電力位準指示信號SPL加以處理，生成控制 碼，生成的控制碼由D / A變換器85變換成類比信號， 作爲電力位準指示電壓VPL供給自動電力控制（APC)電路 74。APC電路74則形成對應電力位準指示電壓VPL的電 力控制信號Vapc的供給高頻電力放大器模組1，高頻電 力放大器模組1便依此信號驅動輸出電晶體。再者，90 是向高頻電力放大器模組1供應電源電壓Vdd的電池。 第10圖是表示應用上述實施例的高頻電力放大電路 的攜帶式電話機的整體架構的方塊圖。 經濟部智慧財產局員工消費合作社印製 本實施例的攜帶式電話機具備有：作爲顯示部的液晶 面板200 ;發送接收用的天線321 ;輸出語音的揚聲器 3 22 ;輸入語音的麥克風323 ;驅動上述液晶面板200進 行顯示的液晶控制驅動器3 1 0 ;輸入輸出揚聲器322或麥 克風323的信號的語音介面3 30 ;經由天線321以GSM方 式等進行行動電話通信的高頻介面340 ;進行語音信號或 發送及接收信號的信號處理的DSP(Digital Signal Processor)351 ;提供定製功能（使用者邏輯）的 ASIC(Application Specific Integrated Circuit)352 ;控制包 含顯示控制的整個裝置的微處理器或微電腦等構成的系統 控制裝置3 5 3 ;資料或程式的記憶用記憶器360 ;以及， 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇X297公釐） -19- 557627 A7 B7 五、發明説明（1> (請先閲讀背面之注意事項再填寫本頁) 振盪電路（OSC) 370等。由上述DSP 351、ASIC 352及系統 控制裝置的微電腦353構成所謂基頻帶部350。上述實施 例的高頻電力放大電路是使用在高頻介面340的發送輸出 部。 以上是依據實施例具體說明本發明人所完成的發明， 但本發明並不限定如上述實施例，當然可以在不脫離其主 旨的範圍內作各種變更。例如，上述實施例的輸出用電晶 體是採3級接續，但也可以是兩級或4級以上，而上述實 施例是說明以不同晶片構成最末級的輸出用電晶體Q3及 與此構成電流鏡電路的電晶體Q 1 3，但也可以與其他電晶 體Q 1、Q2同樣形成在與偏壓電路同一片晶片上，或者相 反地，輸出電晶體Q 1與其電流鏡電路用電晶體Q 1 1或輸 出電晶體Q2與其電流鏡電路用電晶體Q 1 2均以不同晶片 構成。 經濟部智慧財產局員工消費合作社印製 以上，主要是就應用在成爲其背景的利用領域的無線 電通is裝置的局頻電力放大電路，說明本發明人所完成的 發明，但本發明並不限定如此，也同樣可以廣泛應用在主 從方式連接多數半導體放大元件的多級架構的放大電路， 及具有此電路的系統。 簡單說明從本案所揭示的發明中具代表性者所獲得的 效果如下。 亦即，因爲是以具有依循控制電壓的所希望特性的電 流驅動輸出用電晶體，因此，縱使輸出用電晶體的啓始値 參差不齊，仍可獲得具有不依存於此的輸出特性的高頻電 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -20- 557627 A7 B7 五、發明説明（作 (請先聞讀背面之注意事項再填寫本頁} 力放大電路。同時，由於以不同的偏壓電流驅動各級的輸 出電晶體，藉此可以實現，輸出的控制性良好，同時消耗 的電力低、效率佳、可獲得高輸出的高頻電力放大電路。 圖式的簡單說明 第1圖是表示傳統多級架構的高頻電力放大電路的一 個例子的電路圖。 第2圖是表示傳統高頻電力放大電路的偏壓電路的其 他例子的電路圖。 第3圖是表示本發明高頻電力放大電路的一個例子的 電路圖。 第4圖是表示本發明高頻電力放大電路的偏壓電路的 控制電壓Vapc與生成偏壓電流用MOSFET的閘極電壓的 關係的曲線圖。 第5圖是表示本發明高頻電力放大電路的偏壓電路的 控制電壓Vapc與生成偏壓電流用MOSFET的汲極電流的 關係的曲線圖。 經濟部智慧財產局員工消費合作社印製 第6圖是表示將控制電壓Vapc變換成供給偏壓電路 的電流的電壓-流變換電路的具體例子的電路圖。 第7圖是表示產生不依存電源電壓的定電流的具體例 子的電路圖。 第8圖是表示產生可以抵消從電壓-流變換電路輸出 的電流的參差不齊的定電流的定電流電路的具體例子的電 路圖。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -21 - 557627 A7 B7__ 五、發明説明（1知 第9圖是表示裝配在第3圖所示高頻電力放大電路的 行動電話（攜帶式電話機）的一部分的電路方塊圖。 (請先閲讀背面之注意事項再填寫本頁) 第10圖是表示應用實施例的高頻電力放大電路的攜 帶式電話機的整體架構方塊圖。 主要元件對照表 10..........電壓-電流變換電路 20A、20B、20C.......…電流生成電路 3〇..........閘極電壓控制電路 Q1、Q2、Q3-- —......輸出用電晶體 7〇.........-振盪器 71..........電力檢測電路 72……——發送濾波器 73 ..........天線 74 ..........APC 電路 8〇..........接收電路 81 ..........A / D變換器 經濟部智慧財產局員工消費合作社印製 82 ......……控制邏輯 83 ..........輸出位準控制電路 84- ---......邏輯電路 85- …………D / A變換器 90----------電池 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -22--15- 557627 A7 B7 V. Description of the invention (1) 3 Specific examples. (Please read the precautions on the back before filling this page) The voltage-current conversion circuit 10 of this embodiment is a differential amplifier 11 composed of a CMOS differential amplifier circuit with a control voltage Vapc as an input; the differential amplifier 1 The potential of the inverting output node of 1 is applied to the MOSFETs Q41, Q42, and Q43 of the gate terminal; and the resistor R2 connected in series with the MOSFET Q41; is formed because the potential of the connection node between the MOSFET Q41 and the resistor R2 is fed back to the differential The other terminals of the amplifier 11 allow the MOSFETs Q42 and Q43 to pass a drain current proportional to the input voltage Vapc, respectively. The drain currents of Q42 and Q43 can be arbitrarily set according to the size ratio of the MOSFETs Q41 and Q42 (the ratio of the gate width W) and the resistance R2, and the size ratio of Q41 and Q43 and the resistance R2. This is output as the currents I 1 and I 3 supplied to the current generating circuits 20A and 20C. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs FIG. 7 shows a specific example of a constant current circuit of the constant current source 31 which constitutes the gate voltage control circuit 30 described above. The constant current circuit (31) of this embodiment is composed of: a band gap reference circuit 3 11 that can generate a reference voltage Vref with small power supply dependency; and a reference voltage Vref of the band gap reference circuit 3 11 is used as an input and one of the inputs is The received differential circuit 312; the MOSFET Q44 that receives the output of the differential circuit 312 at its gate; the resistor R4 connected between this Q44 and the ground; the gate that receives the output voltage Vcl of the differential circuit 312 at its gate MOSFET Q30; and the connection point between Q44 and resistor R4 is fed back to the other input of differential circuit 312. In the constant current circuit (31) in Fig. 7, the paper size of the differential circuit 312 above applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) -16- 557627 A7 ____B7_ V. Description of the invention (minutes (please (Read the precautions on the back before filling in this tile.) The output is fed back to the other input via a circuit with MOSFETs Q44 and R4. This way, the 获得 of the resistor R4 can be obtained from the output terminal of the differential circuit 3 1 2 Constant voltage Vcl. At the same time, this constant voltage Vcl is also supplied to the sense electrode of MOSFET Q30. Therefore, MOSFET Q30 and MOSFET Q44 constitute a current mirror circuit. Therefore, the MOSFET Q30 uses the current corresponding to the value of the resistor R2 as the current I 4. It is circulated. In this embodiment, the above-mentioned resistor R2 uses a resistor element attached externally. As a result, it is possible to output a current I 4 with higher accuracy than using a resistor formed on a chip. The printed figure 8 shows a specific example of the constant current source 21a (210) of the constant current circuit constituting the current generating circuit 20 A (20C). The constant current circuit (21a, 21c) of this embodiment is A differential circuit 321 using a reference voltage Vref output from a band gap reference circuit 311 common to the constant current circuit (31) as an input; a MOSFET Q45 receiving the output of the differential circuit 321; a resistor connected between the Q45 and ground R5; the MOSFET Q31 that receives the output voltage Vc2 of the differential circuit 321 at the gate terminal; the MOSFET Q32 connected in series with this Q31; the MOSFET Q33 connected to this Q32 to form a current mirror; and the MOSFET Q45 and the resistor R5 The connection point gives feedback to the input of the differential circuit 321. In the constant current circuit 21a (21c) of FIG. 8, the output of the differential circuit 321 is fed back to its input via a circuit having MOSFETs Q45 and R5. The constant voltage Vc2 corresponding to the resistance 値 of the resistor R5 can be obtained from the output terminal of the differential circuit 32. At the same time, this constant voltage Vc2 is also supplied to the sense pole of the MOSFET Q3 1. Therefore, the MOSFET Q45 and the MOSFET Q31 constitute a current mirror circuit. Circulation in MOSFET Q31 corresponds to the above-mentioned resistor R5. This paper size applies Chinese National Standard (CNS) A4 specifications (210X297 mm) -17- 557627 A7 B7 V. Description of the invention (for (please read the precautions on the back first) The current in the resistor 値 of the MOSFET Q31 is copied. The drain current flowing through this MOSFET Q31 is copied by the MOSFETs Q32 and Q33 constituting the current mirror circuit, so that a constant current I 5a (I 5c) flows in Q33. In addition, the constant current circuit of this embodiment is different from the constant current source 31 that passes the constant current I 4 shown in FIG. 7. The resistor R5 does not use externally added components, but uses a resistor formed in the chip. resistance. As a result, when the manufacturing of the resistor R2 of the voltage-current conversion circuit 10 shown in FIG. 6 is uneven and the currents I 1 and I 3 are changed, the constant current circuit 21 a (21 c The resistor R5 in the same manner as the resistor R2 in the voltage-current conversion circuit 10 is also uneven. Therefore, the output current I 5a changes to offset the fluctuations of the currents I 1 and I 3 output from the voltage-current conversion circuit 10. . The differential circuits 312 and 321 are not particularly limited, but are composed of a pair of differential transistors Qpl, Qp2, current mirror transistors Qcl, Qc2, and a constant current element I constituting a load circuit thereof. Fig. 9 is a circuit block diagram showing a part of a mobile phone (portable telephone) equipped with the high-frequency power amplifier circuit of Fig. 3; As shown in Fig. 9, the mobile phone printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs enters the oscillation oscillator (VC0) 70 for modulation at the input terminal (Pin) of the high-frequency power amplifier module 1 Generated RF transmit signal. The RF transmission signal is amplified by the high-frequency power amplifier module 1 and output from the output terminal (Pout). The RF transmission signal passes through the power detection circuit 71, the transmission filter 72, and reaches the antenna 73. The antenna 73 transmits radio waves. On the other hand, the RF reception signal received by the antenna 73 applies the Chinese National Standard (CNS) A4 specification (210X297 mm) at the paper size. -18- 557627 A7 B7 V. Description of the invention (life (please read the back first) (Please fill in this page before filling in this page) The receiving circuit 80 performs signal processing. The receiving strength signal SRI is output from the receiving circuit 80, converted into a digital signal by the A / D converter 81, and supplied to the control logic 82. The control logic 82 outputs the power level The instruction signal SPL is supplied to the logic circuit 84 of the output level control circuit 83. This logic circuit 84 processes the output power level instruction signal SPL to generate a control code, and the generated control code is converted by the D / A converter 85 The analog signal is supplied to the automatic power control (APC) circuit 74 as the power level indicating voltage VPL. The APC circuit 74 forms a power control signal Vapc corresponding to the power level indicating voltage VPL and supplies it to the high-frequency power amplifier module 1, high-frequency The power amplifier module 1 drives the output transistor according to this signal. Furthermore, 90 is a battery that supplies the power supply voltage Vdd to the high-frequency power amplifier module 1. Figure 10 is Shows a block diagram of the overall structure of a portable telephone using the high-frequency power amplifier circuit of the above embodiment. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the portable telephone of this embodiment is provided with: a liquid crystal panel 200 as a display section; Antenna 321 for transmitting and receiving; speaker 3 22 for outputting voice; microphone 323 for inputting voice; liquid crystal control driver 3 1 0 for driving the above-mentioned liquid crystal panel 200 for display; voice interface 3 30 for inputting and outputting signals from speaker 322 or microphone 323; High-frequency interface 340 for mobile phone communication in GSM mode via antenna 321; DSP (Digital Signal Processor) 351 for signal processing of voice signals or sending and receiving signals; ASIC (Application) that provides custom functions (user logic) Specific Integrated Circuit) 352; a system control device consisting of a microprocessor or a microcomputer that controls the entire device including display control 3 5 3; a memory 360 for data or program memory; and, this paper standard applies Chinese National Standard (CNS ) A4 specifications (21 × 297 mm) -19- 557627 A7 B7 V. Invention (1> (Please read the precautions on the back before filling in this page) Oscillation circuit (OSC) 370, etc. The so-called baseband unit 350 is constituted by the above-mentioned DSP 351, ASIC 352, and microcomputer 353 of the system control device. The high-frequency power amplifier circuit is a transmission output section used in the high-frequency interface 340. The above is a detailed description of the invention made by the present inventors based on the embodiments, but the present invention is not limited to the above embodiments, and of course, various changes can be made without departing from the scope of the invention. For example, in the above embodiment, the output transistor is connected in three stages, but it may also be two or four or more stages. The above embodiment describes the structure of the final stage output transistor Q3 with different wafers and the structure. The transistor Q 1 3 of the current mirror circuit, but may be formed on the same chip as the bias circuit, like the other transistors Q 1 and Q 2, or on the contrary, the output transistor Q 1 and its current mirror circuit transistor The Q 1 1 or the output transistor Q 2 and the transistor Q 1 2 for the current mirror circuit are each composed of different chips. The above is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, mainly for the application of the local-frequency power amplifier circuit of the radio communication device used in the field of its background, to explain the invention completed by the inventor, but the invention is not limited. In this way, it can also be widely used in a multilevel architecture amplifier circuit in which a plurality of semiconductor amplifier components are connected in a master-slave manner, and a system having the circuit. A brief description of the effects obtained by the representative of the inventions disclosed in the present case is as follows. That is, since the output transistor is driven with a current having a desired characteristic in accordance with the control voltage, even if the start of the output transistor is uneven, a high output characteristic that does not depend on it can be obtained. The size of the frequency paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -20- 557627 A7 B7 V. Description of the invention (for (please read the precautions on the back before filling out this page) Force amplification circuit. At the same time Because the output transistors at different levels are driven with different bias currents, it can be achieved by this, the output is well controlled, and the power consumption is low, the efficiency is high, and a high-frequency power amplifier circuit with high output can be obtained. Brief Description Fig. 1 is a circuit diagram showing an example of a conventional high-frequency power amplifier circuit of a multi-stage architecture. Fig. 2 is a circuit diagram showing another example of a bias circuit of a conventional high-frequency power amplifier circuit. Fig. 3 is a diagram showing A circuit diagram of an example of the high-frequency power amplifier circuit of the present invention is shown in Fig. 4. Fig. 4 shows a control voltage Vapc and a voltage of a bias circuit of the high-frequency power amplifier circuit of the present invention. FIG. 5 is a graph showing the relationship between the gate voltage of the bias current MOSFET. FIG. 5 shows the relationship between the control voltage Vapc of the bias circuit of the high-frequency power amplifier circuit of the present invention and the drain current of the MOSFET for generating the bias current. Graph. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 6 is a circuit diagram showing a specific example of a voltage-current conversion circuit that converts the control voltage Vapc into a current supplied to the bias circuit. A circuit diagram of a specific example of a constant current that depends on the power supply voltage. Figure 8 is a circuit diagram showing a specific example of a constant current circuit that generates a constant current that can cancel the uneven current that is output from the voltage-current conversion circuit. China National Standard (CNS) A4 specification (210X297 mm) -21-557627 A7 B7__ V. Description of the invention (1 knows that Fig. 9 shows a mobile phone (portable phone) equipped with a high-frequency power amplifier circuit shown in Fig. 3 ) Part of the circuit block diagram. (Please read the precautions on the back before filling out this page) Figure 10 shows the high-frequency power amplifier of the application example Circuit block diagram of the overall structure of a portable telephone. The main components are compared in the table 10 ............. Voltage-current conversion circuits 20A, 20B, 20C ......... Current generation circuit 30. ......... Gate voltage control circuit Q1, Q2, Q3 --......... Output transistor 7〇 .........- Oscillator 71 ... ....... Power detection circuit 72 …… ——Send filter 73 .......... Antenna 74 .......... APC circuit 8〇 ..... ..... Receiving circuit 81 .......... A / D converter Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Employee Consumer Cooperatives 82 ............ Control logic 83 ..... ..... output level control circuit 84- ---... logic circuit 85- ............ D / A converter 90 ---------- battery This paper size applies China National Standard (CNS) A4 Specification (210X297 mm) -22-