JP2007019464A - Packaging structure of semiconductor device - Google Patents

Packaging structure of semiconductor device Download PDF

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Publication number
JP2007019464A
JP2007019464A JP2006093178A JP2006093178A JP2007019464A JP 2007019464 A JP2007019464 A JP 2007019464A JP 2006093178 A JP2006093178 A JP 2006093178A JP 2006093178 A JP2006093178 A JP 2006093178A JP 2007019464 A JP2007019464 A JP 2007019464A
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Japan
Prior art keywords
semiconductor device
mounting structure
connection member
underfill material
substrate
Prior art date
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Granted
Application number
JP2006093178A
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Japanese (ja)
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JP4835230B2 (en
Inventor
Takeshi Wakabayashi
猛 若林
Ichiro Mihara
一郎 三原
Osamu Okada
修 岡田
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP2006093178A priority Critical patent/JP4835230B2/en
Publication of JP2007019464A publication Critical patent/JP2007019464A/en
Priority to US11/729,650 priority patent/US7592672B2/en
Application granted granted Critical
Publication of JP4835230B2 publication Critical patent/JP4835230B2/en
Expired - Fee Related legal-status Critical Current
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Abstract

<P>PROBLEM TO BE SOLVED: To reduce a packaging area in a packaging structure of a semiconductor device called as an SOI. <P>SOLUTION: A connection member 25 made of conductive paste such as silver paste is provided at the whole one-side upper face of a silicon substrate 3 in the semiconductor device 1 at the outer face of an underfill member 24 near to the one-side upper face, and at the nearby upper face of a grounding wiring 23. In this case, a protrusion length projected outside the underfill member 24 of a connection member 25 can be reduced as much as possible, so that the substantial packaging area of the semiconductor device 1 can be reduced as compared with a case that bonding wire is used. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明は半導体装置の実装構造に関する。   The present invention relates to a mounting structure of a semiconductor device.

従来の半導体装置には、ＳＯＩ(silicon on insulator)と呼ばれるもので、半導体基板上に絶縁膜が設けられ、絶縁膜上に薄膜トランジスタを形成してなるＳＯＩ集積回路部が設けられたものがある。（例えば、特許文献１参照）。この従来の半導体装置では、リードフレーム上にフェースアップ方式でつまりＳＯＩ集積回路部を上側として搭載され、ＳＯＩ集積回路部上の接続パッドがリードフレームにボンディングワイヤを介して接続されている。この場合、半導体基板の電位の安定化を図るために、半導体基板の下面はグランド電位のリードフレームに接続されている。   Some conventional semiconductor devices are called SOI (silicon on insulator) and have an SOI integrated circuit portion formed by forming an insulating film on a semiconductor substrate and forming a thin film transistor on the insulating film. (For example, refer to Patent Document 1). In this conventional semiconductor device, the lead frame is mounted on the lead frame in a face-up manner, that is, with the SOI integrated circuit portion on the upper side, and the connection pads on the SOI integrated circuit portion are connected to the lead frame via bonding wires. In this case, in order to stabilize the potential of the semiconductor substrate, the lower surface of the semiconductor substrate is connected to a lead frame having a ground potential.

特開２００３−２１８３５６号公報（図１２）JP 2003-218356 A (FIG. 12)

しかしながら、上記従来の半導体装置の実装構造では、集積化が進むに従って、ＳＯＩ集積回路部上の接続パッドの数が増加すると、半導体装置の周囲に配置されているボンディングワイヤの長さが長くなり、ひいては実装面積が大きくなり、しかもボンディングワイヤを含む半導体装置を封止膜で封止すると、実装面積がさらに大きくなってしまうという問題があった。   However, in the conventional semiconductor device mounting structure, as the number of connection pads on the SOI integrated circuit portion increases as the integration proceeds, the length of the bonding wires arranged around the semiconductor device increases. As a result, there is a problem that the mounting area is increased, and further, when the semiconductor device including the bonding wire is sealed with the sealing film, the mounting area is further increased.

そこで、この発明は、実装面積を小さくすることができる半導体装置の実装構造を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device mounting structure capable of reducing the mounting area.

この発明は、上記目的を達成するため、半導体基板、該半導体基板下に設けられた絶縁膜および該絶縁膜下に設けられたＳＯＩ集積回路部を有する半導体装置が回路基板上にフェースダウン方式で搭載され、前記半導体装置と前記回路基板との間にアンダーフィル材が設けられ、前記アンダーフィル材の外側における前記回路基板上に設けられたグランド用配線と前記半導体装置の半導体基板とが、導電性ペーストからなる接続部材、あるいは導電性ペーストまたは異方性導電接着剤を介して前記グランド用配線および前記半導体基板に接続される金属箔からなる接続部材により接続されていることを特徴とするものである。   In order to achieve the above object, the present invention provides a semiconductor device having a semiconductor substrate, an insulating film provided under the semiconductor substrate, and an SOI integrated circuit portion provided under the insulating film in a face-down manner on the circuit board. An underfill material is provided between the semiconductor device and the circuit board, and a ground wiring provided on the circuit board outside the underfill material and the semiconductor substrate of the semiconductor device are electrically conductive. A connection member made of a conductive paste, or a connection member made of a metal foil connected to the ground wiring and the semiconductor substrate via a conductive paste or an anisotropic conductive adhesive It is.

この発明によれば、半導体基板、絶縁膜およびＳＯＩ集積回路部を有する半導体装置を回路基板上にフェースダウン方式で搭載し、半導体装置と回路基板との間にアンダーフィル材を設け、アンダーフィル材の外側における回路基板上に設けられたグランド用配線と半導体装置の半導体基板とを導電性ペーストあるいは金属箔からなる接続部材を介して接続しているので、ボンディングワイヤを用いる場合と比較して、実装面積を小さくすることができる。   According to the present invention, a semiconductor device having a semiconductor substrate, an insulating film, and an SOI integrated circuit portion is mounted on the circuit substrate in a face-down manner, and the underfill material is provided between the semiconductor device and the circuit substrate. Since the ground wiring provided on the circuit board on the outside of the semiconductor device and the semiconductor substrate of the semiconductor device are connected via a connection member made of conductive paste or metal foil, compared to the case of using a bonding wire, The mounting area can be reduced.

（第１実施形態）
図１はこの発明の第１実施形態としての半導体装置の実装構造の断面図を示し、図２はその一部を省略した平面図を示す。半導体装置１は、一般的にはＣＳＰ(chip size package)と呼ばれるものであり、ＳＯＩ基板２を備えている。 (First embodiment)
FIG. 1 shows a cross-sectional view of a semiconductor device mounting structure as a first embodiment of the present invention, and FIG. 2 shows a plan view with a part thereof omitted. The semiconductor device 1 is generally called a CSP (chip size package) and includes an SOI substrate 2.

ＳＯＩ基板２は、平面正方形状のシリコン基板（半導体基板）３の下面に酸化シリコン等からなる絶縁膜４が設けられ、絶縁膜４の下面に薄膜トランジスタを形成してなるＳＯＩ集積回路部５が設けられた構造となっている。この場合、ＳＯＩ集積回路部５の薄膜トランジスタのソース・ドレイン領域は、絶縁膜４に設けられた上下導通部（図示せず）を介してシリコン基板３に接続されている。   The SOI substrate 2 is provided with an insulating film 4 made of silicon oxide or the like on the lower surface of a planar square silicon substrate (semiconductor substrate) 3 and an SOI integrated circuit portion 5 formed by forming a thin film transistor on the lower surface of the insulating film 4. It has a structured. In this case, the source / drain region of the thin film transistor of the SOI integrated circuit portion 5 is connected to the silicon substrate 3 through a vertical conduction portion (not shown) provided in the insulating film 4.

ＳＯＩ集積回路部５の下面周辺部にはアルミニウム系金属等からなる複数の接続パッド６がＳＯＩ集積回路部５に接続されて設けられている。接続パッド６の下面中央部を除くＳＯＩ集積回路部５の下面には酸化シリコン等からなる絶縁膜７が設けられ、接続パッド６の下面中央部は絶縁膜７に設けられた開口部８を介して露出されている。   A plurality of connection pads 6 made of an aluminum-based metal or the like are provided on the periphery of the lower surface of the SOI integrated circuit portion 5 so as to be connected to the SOI integrated circuit portion 5. An insulating film 7 made of silicon oxide or the like is provided on the lower surface of the SOI integrated circuit portion 5 excluding the lower surface center portion of the connection pad 6, and the lower surface center portion of the connection pad 6 passes through an opening 8 provided in the insulating film 7. Is exposed.

絶縁膜７の下面にはポリイミド系樹脂等からなる保護膜（絶縁膜）９が設けられている。絶縁膜７の開口部８に対応する部分における保護膜９には開口部１０が設けられている。保護膜９の下面には銅等からなる下地金属層１１が設けられている。下地金属層１１の下面全体には銅からなる配線１２が設けられている。下地金属層１１を含む配線１２の一端部は、保護膜９および絶縁膜７の開口部１０、８を介して接続パッド６に接続されている。   A protective film (insulating film) 9 made of polyimide resin or the like is provided on the lower surface of the insulating film 7. An opening 10 is provided in the protective film 9 at a portion corresponding to the opening 8 of the insulating film 7. A base metal layer 11 made of copper or the like is provided on the lower surface of the protective film 9. A wiring 12 made of copper is provided on the entire lower surface of the base metal layer 11. One end of the wiring 12 including the base metal layer 11 is connected to the connection pad 6 through the protective film 9 and the openings 10 and 8 of the insulating film 7.

配線１２の接続パッド部下面には銅からなる柱状電極１３が設けられている。配線１２を含む保護膜９の下面にはエポキシ系樹脂等からなる封止膜１４がその下面が柱状電極１３の下面と面一となるように設けられている。柱状電極１３の下面には半田ボール１５が設けられている。複数の半田ボール１５は、封止膜１４下にマトリクス状に配置されている。   A columnar electrode 13 made of copper is provided on the lower surface of the connection pad portion of the wiring 12. A sealing film 14 made of an epoxy resin or the like is provided on the lower surface of the protective film 9 including the wiring 12 so that the lower surface thereof is flush with the lower surface of the columnar electrode 13. A solder ball 15 is provided on the lower surface of the columnar electrode 13. The plurality of solder balls 15 are arranged in a matrix under the sealing film 14.

一方、回路基板２１の上面には平面円形状の複数の接続パッド２２がマトリクス状に設けられている。接続パッド２２は、回路基板２１の上面に設けられた配線（図示せず）の一端部に接続されている。回路基板２１の上面の所定の箇所にはグランド用配線２３が設けられている。   On the other hand, a plurality of planar circular connection pads 22 are provided in a matrix on the upper surface of the circuit board 21. The connection pad 22 is connected to one end of a wiring (not shown) provided on the upper surface of the circuit board 21. A ground wiring 23 is provided at a predetermined location on the upper surface of the circuit board 21.

そして、半導体装置１は、各半田ボール１５がそれぞれ対応する各接続パッド２２に接合されていることにより、回路基板２１上にフェースダウン方式で搭載されている。半導体装置１と回路基板２１との間にはエポキシ系樹脂等からなるアンダーフィル材２４が設けられている。この場合、アンダーフィル材２４は、半導体装置１の周囲における回路基板２１の上面および半導体装置１の周側面を覆うように設けられている。   The semiconductor device 1 is mounted on the circuit board 21 in a face-down manner by bonding each solder ball 15 to each corresponding connection pad 22. An underfill material 24 made of epoxy resin or the like is provided between the semiconductor device 1 and the circuit board 21. In this case, the underfill material 24 is provided so as to cover the upper surface of the circuit board 21 and the peripheral side surface of the semiconductor device 1 around the semiconductor device 1.

ここで、回路基板２１上のグランド用配線２３の一端部は、半導体装置１の一辺に沿う位置においてアンダーフィル材２４の外側に配置されている。そして、半導体装置１のシリコン基板３の一辺部上面全体、その近傍のアンダーフィル材２４の外面およびその近傍のグランド用配線２３の上面には、デイスペンサーを用いて銀ペースト等の導電性ペーストを塗布して硬化させることにより、アンダーフィル材２４に固着された接続部材２５が設けられている。   Here, one end of the ground wiring 23 on the circuit board 21 is disposed outside the underfill material 24 at a position along one side of the semiconductor device 1. Then, a conductive paste such as a silver paste is applied to the entire upper surface of one side of the silicon substrate 3 of the semiconductor device 1, the outer surface of the underfill material 24 in the vicinity thereof, and the upper surface of the ground wiring 23 in the vicinity thereof using a dispenser. A connecting member 25 fixed to the underfill material 24 is provided by applying and curing.

以上のように、この半導体装置の実装構造では、接続パッド６を含むＳＯＩ集積回路部５下に絶縁膜７および保護膜９を設け、保護膜９下に下地金属層１１を含む配線１２を接続パッド６に接続させて設け、配線１２の接続パッド部下に柱状電極１３を設け、配線１２を含む保護膜９下に封止膜１４を設け、柱状電極１３下に半田ボール１５を設け、半田ボール１５をその下に配置された回路基板２１上の接続パッド２２に接合させているので、この場合の電気的接続配線が主としてシリコン基板３の厚さ方向となり、実装面積を小さくすることができる。   As described above, in this semiconductor device mounting structure, the insulating film 7 and the protective film 9 are provided under the SOI integrated circuit portion 5 including the connection pads 6, and the wiring 12 including the base metal layer 11 is connected under the protective film 9. Provided by being connected to the pad 6, a columnar electrode 13 is provided below the connection pad portion of the wiring 12, a sealing film 14 is provided below the protective film 9 including the wiring 12, a solder ball 15 is provided below the columnar electrode 13, and a solder ball 15 is bonded to the connection pads 22 on the circuit board 21 disposed thereunder, the electrical connection wiring in this case is mainly in the thickness direction of the silicon substrate 3, and the mounting area can be reduced.

また、この半導体装置の実装構造では、アンダーフィル材２４を半導体装置１と回路基板２１との間に設け、且つ、半導体装置１の周囲における回路基板２１の上面および半導体装置１の周側面を覆うように設けているので、アンダーフィル材２４の半導体装置１の周側面の外側に突出する突出長を可及的に小さくすることができる。また、半導体装置１のシリコン基板３の一辺部上面全体、その近傍のアンダーフィル材２４の外面およびその近傍のグランド用配線２３の上面に導電性ペーストからなる接続部材２５を設けているので、接続部材２５のアンダーフィル材２４の外側に突出する突出長を可及的に小さくすることができる。これらの結果、半導体装置１の実質的な実装面積を、ボンディングワイヤを用いる場合と比較して、小さくすることができる。   In this semiconductor device mounting structure, the underfill material 24 is provided between the semiconductor device 1 and the circuit substrate 21, and covers the upper surface of the circuit substrate 21 and the peripheral side surface of the semiconductor device 1 around the semiconductor device 1. Thus, the protruding length of the underfill material 24 protruding outside the peripheral side surface of the semiconductor device 1 can be made as small as possible. Further, since the connection member 25 made of conductive paste is provided on the entire upper surface of one side of the silicon substrate 3 of the semiconductor device 1, the outer surface of the underfill material 24 in the vicinity thereof, and the upper surface of the ground wiring 23 in the vicinity thereof, the connection The protrusion length which protrudes outside the underfill material 24 of the member 25 can be made as small as possible. As a result, the substantial mounting area of the semiconductor device 1 can be reduced as compared with the case where a bonding wire is used.

（第２実施形態）
図３はこの発明の第２実施形態としての半導体装置の実装構造の断面図を示す。この半導体装置の実装構造において、図１に示す場合と異なる点は、半導体装置１のシリコン基板３の上面周辺部に傾斜面３ａを設けた点である。このようにした場合には、シリコン基板３の傾斜面３ａおよびその近傍を覆うように設けられた接続部材２５が、図１に示す場合と比較して、断線しにくいようにすることができる。 (Second Embodiment)
FIG. 3 shows a sectional view of a semiconductor device mounting structure as a second embodiment of the present invention. In this semiconductor device mounting structure, the difference from the case shown in FIG. 1 is that an inclined surface 3 a is provided in the periphery of the upper surface of the silicon substrate 3 of the semiconductor device 1. In this case, the connection member 25 provided so as to cover the inclined surface 3a of the silicon substrate 3 and the vicinity thereof can be made less likely to be disconnected than the case shown in FIG.

次に、この第２実施形態における半導体装置１の製造方法の一部について説明する。まず、ウエハ状態のシリコン基板３下に絶縁膜４、ＳＯＩ集積回路部５、接続パッド６、絶縁膜７、保護膜９、下地金属層１１を含む配線１２、柱状電極１３、封止膜１４および半田ボール１５を形成し、次いでウエハ状態のシリコン基板３の上面にダイシングストリートに沿ってダイシングストリートよりも幅広のほぼＶ字状の溝（例斜面３ａ）を形成し、次いでダイシングストリートに沿って切断すると、図３に示す半導体装置１が複数個得られる。この場合、例斜面３ａの角度は、ダイシングストリートの幅にもよるが、４５°付近が望ましい。   Next, a part of the manufacturing method of the semiconductor device 1 in the second embodiment will be described. First, an insulating film 4, an SOI integrated circuit unit 5, a connection pad 6, an insulating film 7, a protective film 9, a wiring 12 including a base metal layer 11, a columnar electrode 13, a sealing film 14 and a silicon substrate 3 in a wafer state A solder ball 15 is formed, and then a substantially V-shaped groove (eg, slope 3a) wider than the dicing street is formed on the upper surface of the silicon substrate 3 in a wafer state along the dicing street, and then cut along the dicing street. Then, a plurality of semiconductor devices 1 shown in FIG. 3 are obtained. In this case, the angle of the slope 3a is preferably around 45 °, although it depends on the width of the dicing street.

（第３実施形態）
図４はこの発明の第３実施形態としての半導体装置の実装構造の断面図を示す。この半導体装置の実装構造において、図１に示す場合と異なる点は、半導体装置１のシリコン基板３の上面全体に銅等からなる金属膜１６を設け、金属膜１６の上面の所定の箇所に接続部材２５の一端部を設けた点である。 (Third embodiment)
FIG. 4 is a sectional view of a semiconductor device mounting structure as a third embodiment of the present invention. The semiconductor device mounting structure is different from that shown in FIG. 1 in that a metal film 16 made of copper or the like is provided on the entire upper surface of the silicon substrate 3 of the semiconductor device 1 and connected to a predetermined location on the upper surface of the metal film 16. This is a point where one end of the member 25 is provided.

なお、図３に示すような半導体装置１の場合には、ウエハ状態のシリコン基板３の上面にダイシングストリートに沿ってダイシングストリートよりも幅広のほぼＶ字状の溝（例斜面３ａ）を形成し、次いでほぼＶ字状の溝を含むシリコン基板１の上面にスパッタ法等により金属膜を成膜し、次いでダイシングストリートに沿って切断するようにすればよい。また、金属膜１６の代わりに、導電性ペーストや異方性導電接着剤等からなる導電膜を形成するようにしてもよい。   In the case of the semiconductor device 1 as shown in FIG. 3, a substantially V-shaped groove (eg, slope 3a) wider than the dicing street is formed along the dicing street on the upper surface of the silicon substrate 3 in the wafer state. Then, a metal film may be formed on the upper surface of the silicon substrate 1 including a substantially V-shaped groove by sputtering or the like, and then cut along a dicing street. Further, instead of the metal film 16, a conductive film made of a conductive paste, an anisotropic conductive adhesive or the like may be formed.

（第４実施形態）
図５はこの発明の第４実施形態としての半導体装置の実装構造の断面図を示す。この半導体装置の実装構造において、図４に示す場合と異なる点は、半導体装置１のシリコン基板３の上面および周側面に金属膜１６を設けた点である。 (Fourth embodiment)
FIG. 5 shows a sectional view of a semiconductor device mounting structure as a fourth embodiment of the present invention. This semiconductor device mounting structure is different from the case shown in FIG. 4 in that a metal film 16 is provided on the upper surface and the peripheral side surface of the silicon substrate 3 of the semiconductor device 1.

次に、この第４実施形態における半導体装置１の製造方法の一部について説明する。まず、ウエハ状態のシリコン基板３下に絶縁膜４、ＳＯＩ集積回路部５、接続パッド６、絶縁膜７、保護膜９、下地金属層１１を含む配線１２、柱状電極１３および封止膜１４を形成し、次いでウエハ状態のシリコン基板３の上面にダイシングストリートに沿ってダイシングストリートよりも幅広の溝を形成し、次いでこの溝を含むウエハ状態のシリコン基板３の上面にスパッタ法等により金属膜１６を成膜し、次いで柱状電極１３下に半田ボール１５を形成し、次いでダイシングストリートに沿って切断すると、図５に示す半導体装置１が複数個得られる。   Next, a part of the manufacturing method of the semiconductor device 1 in the fourth embodiment will be described. First, an insulating film 4, an SOI integrated circuit unit 5, a connection pad 6, an insulating film 7, a protective film 9, a wiring 12 including a base metal layer 11, a columnar electrode 13 and a sealing film 14 are formed under the silicon substrate 3 in a wafer state. Next, a groove wider than the dicing street is formed along the dicing street on the upper surface of the silicon substrate 3 in the wafer state, and then the metal film 16 is formed on the upper surface of the silicon substrate 3 including the groove by sputtering or the like. Then, the solder balls 15 are formed under the columnar electrodes 13 and then cut along the dicing streets. Thus, a plurality of semiconductor devices 1 shown in FIG. 5 are obtained.

なお、金属膜１６の代わりに、導電性ペーストや異方性導電接着剤等からなる導電膜を形成するようにしてもよい。この場合、シリコン基板３の周側面のみに導電膜を形成するようにしてもよい。すなわち、ウエハ状態のシリコン基板３の上面にダイシングストリートに沿って形成された溝内のみに導電性ペーストや異方性導電接着剤等からなる導電膜を形成すると、シリコン基板３の周側面のみに導電膜が形成された半導体装置が得られる。   Instead of the metal film 16, a conductive film made of a conductive paste, an anisotropic conductive adhesive, or the like may be formed. In this case, the conductive film may be formed only on the peripheral side surface of the silicon substrate 3. That is, when a conductive film made of a conductive paste, an anisotropic conductive adhesive, or the like is formed only in the groove formed along the dicing street on the upper surface of the silicon substrate 3 in the wafer state, only on the peripheral side surface of the silicon substrate 3. A semiconductor device in which a conductive film is formed is obtained.

（第５実施形態）
図６はこの発明の第５実施形態としての半導体装置の実装構造の断面図を示す。この半導体装置の実装構造において、図１に示す場合と異なる点は、半導体装置１のシリコン基板３の上面、接続部材２５の表面およびグランド用配線２３の一側面にエポキシ系樹脂等からなる絶縁膜２６を設けた点である。なお、図４および図５に示す場合には、金属膜１（導電膜）６の上面、接続部材２５の表面およびグランド用配線２３の一側面にエポキシ系樹脂等からなる絶縁膜２６を設けるようにしてもよい。 (Fifth embodiment)
FIG. 6 shows a sectional view of a semiconductor device mounting structure as a fifth embodiment of the present invention. This semiconductor device mounting structure is different from the case shown in FIG. 1 in that an insulating film made of epoxy resin or the like is formed on the upper surface of the silicon substrate 3 of the semiconductor device 1, the surface of the connection member 25, and one side surface of the ground wiring 23. 26 is provided. 4 and 5, an insulating film 26 made of an epoxy resin or the like is provided on the upper surface of the metal film 1 (conductive film) 6, the surface of the connection member 25, and one side surface of the ground wiring 23. It may be.

（第６実施形態）
図７はこの発明の第６実施形態としての半導体装置の実装構造の断面図を示す。この半導体装置の実装構造において、図１に示す場合と異なる点は、グランド用配線２３を半導体装置１の一辺下に配置し、半導体装置１のシリコン基板３の一辺部上面全体、半導体装置１の一辺側側面全体およびその近傍のグランド用配線２３の上面に接続部材２５を設けた点である。この場合、グランド用配線２３の内側における回路基板２１の上面の所定の箇所にはレジスト等からなるアンダーフィル材堰き止め部２７が設けられている。 (Sixth embodiment)
FIG. 7 is a sectional view of a semiconductor device mounting structure as a sixth embodiment of the present invention. In this semiconductor device mounting structure, the difference from the case shown in FIG. 1 is that the ground wiring 23 is arranged below one side of the semiconductor device 1, the entire upper surface of one side of the silicon substrate 3 of the semiconductor device 1, and the semiconductor device 1. The connection member 25 is provided on the entire side surface of the one side and the upper surface of the ground wiring 23 in the vicinity thereof. In this case, an underfill material damming portion 27 made of a resist or the like is provided at a predetermined position on the upper surface of the circuit board 21 inside the ground wiring 23.

次に、この第６実施形態におけるアンダーフィル材２４の形成方法について説明する。まず、半導体装置１を回路基板２１上にフェースダウン方式で搭載し、次いでディスペンサーを用いてグランド用配線２３の配置位置とは反対側の方向から半導体装置１と回路基板２１との間にアンダーフィル材を注入する。この場合、半導体装置１と回路基板２１との間に注入されたアンダーフィル材は、アンダーフィル材堰き止め部２７で堰き止められるため、グランド用配線２３の上面に流れることはない。   Next, a method for forming the underfill material 24 in the sixth embodiment will be described. First, the semiconductor device 1 is mounted on the circuit board 21 in a face-down manner, and then an underfill is applied between the semiconductor device 1 and the circuit board 21 from the direction opposite to the arrangement position of the ground wiring 23 using a dispenser. Inject the material. In this case, the underfill material injected between the semiconductor device 1 and the circuit board 21 is blocked by the underfill material blocking section 27 and therefore does not flow to the upper surface of the ground wiring 23.

そして、この第４実施形態では、グランド用配線２３を半導体装置１の一辺下に配置し、半導体装置１のシリコン基板３の一辺部上面全体、半導体装置１の一辺側側面全体およびその近傍のグランド用配線２３の上面に接続部材２５を設けているので、半導体装置１の実質的な実装面積を、図１に示す場合よりもさらに小さくすることができる。   In the fourth embodiment, the ground wiring 23 is arranged below one side of the semiconductor device 1, and the entire upper surface of one side of the silicon substrate 3 of the semiconductor device 1, the entire side surface of one side of the semiconductor device 1, and the ground in the vicinity thereof. Since the connection member 25 is provided on the upper surface of the main wiring 23, the substantial mounting area of the semiconductor device 1 can be further reduced as compared with the case shown in FIG.

（第７実施形態）
図８はこの発明の第７実施形態としての半導体装置の実装構造の図２同様の断面図を示す。この半導体装置の実装構造において、図２に示す場合と異なる点は、グランド用配線２３の一端部を半導体装置１の一辺に直交する位置においてアンダーフィル材２４の外側に配置し、半導体装置１のシリコン基板３の一辺部上面の一部、その近傍のアンダーフィル材２４の外面およびその近傍のグランド用配線２３の上面に接続部材２５を設けた点である。 (Seventh embodiment)
FIG. 8 is a sectional view similar to FIG. 2 of a semiconductor device mounting structure according to a seventh embodiment of the present invention. The semiconductor device mounting structure is different from the case shown in FIG. 2 in that one end of the ground wiring 23 is arranged outside the underfill material 24 at a position orthogonal to one side of the semiconductor device 1. The connection member 25 is provided on a part of the upper surface of one side of the silicon substrate 3, the outer surface of the underfill material 24 in the vicinity thereof, and the upper surface of the ground wiring 23 in the vicinity thereof.

（その他の実施形態）
例えば、図１に示す場合において、半導体装置１のシリコン基板３のエッジ部に起因する接続部材２５の断線を防止するために、ジェットディスペンサー方式と呼ばれ、スクリューピストン等を用いて導電性ペーストを吹き付ける方法により、接続部材２５を形成するようにしてもよい。また、アンダーフィル材２４および導電性ペーストからなる接続部材２５の本硬化は、別々に行なうようにしてもよく、また、アンダーフィル材２４を半硬化させておき、同時に行なうようにしてもよい。 (Other embodiments)
For example, in the case shown in FIG. 1, in order to prevent disconnection of the connection member 25 due to the edge portion of the silicon substrate 3 of the semiconductor device 1, this is called a jet dispenser method, and a conductive paste is applied using a screw piston or the like. The connecting member 25 may be formed by a spraying method. Further, the main curing of the underfill material 24 and the connecting member 25 made of a conductive paste may be performed separately, or the underfill material 24 may be semi-cured and performed simultaneously.

また、上記実施形態では、半導体装置１のシリコン基板３とグランド用配線２３とを接続する接続部材２５は、全体が導電性ペーストから構成されるものとしたが、シリコン基板３上およびグランド用配線２３上のみに導電性ペーストを設け、両者を銅箔等の金属箔、または金属箔の裏面に樹脂フィルムを有する接続部材で接続してもよい。   In the above embodiment, the connection member 25 that connects the silicon substrate 3 of the semiconductor device 1 and the ground wiring 23 is entirely made of a conductive paste. A conductive paste may be provided only on 23, and both may be connected by a metal foil such as a copper foil or a connection member having a resin film on the back surface of the metal foil.

さらには、金属箔の一面に、絶縁材中に導電性フィラーが分散された異方性導電接着剤が被着された異方性導電接着剤付の接続部材で接続することもできる。この場合、上記金属箔を有する接続部材は、金属箔の接続部以外の領域に接着剤を設けてアンダーフィル材２４に接着する構造とすることが望ましい。   Furthermore, it can also be connected to one surface of the metal foil by a connecting member with an anisotropic conductive adhesive in which an anisotropic conductive adhesive in which a conductive filler is dispersed in an insulating material is attached. In this case, it is desirable that the connection member having the metal foil has a structure in which an adhesive is provided in a region other than the connection portion of the metal foil to adhere to the underfill material 24.

この発明の第１実施形態としての半導体装置の実装構造の断面図。Sectional drawing of the mounting structure of the semiconductor device as 1st Embodiment of this invention. 図１に示す半導体装置の実装構造の一部を省略した平面図。The top view which abbreviate | omitted a part of mounting structure of the semiconductor device shown in FIG. この発明の第２実施形態としての半導体装置の実装構造の断面図。Sectional drawing of the mounting structure of the semiconductor device as 2nd Embodiment of this invention. この発明の第３実施形態としての半導体装置の実装構造の断面図。Sectional drawing of the mounting structure of the semiconductor device as 3rd Embodiment of this invention. この発明の第４実施形態としての半導体装置の実装構造の断面図。Sectional drawing of the mounting structure of the semiconductor device as 4th Embodiment of this invention. この発明の第５実施形態としての半導体装置の実装構造の断面図。Sectional drawing of the mounting structure of the semiconductor device as 5th Embodiment of this invention. この発明の第６実施形態としての半導体装置の実装構造の断面図。Sectional drawing of the mounting structure of the semiconductor device as 6th Embodiment of this invention. この発明の第７実施形態としての半導体装置の実装構造の図２同様の平面図。The top view similar to FIG. 2 of the mounting structure of the semiconductor device as 7th Embodiment of this invention.

符号の説明Explanation of symbols

１ 半導体装置
２ ＳＯＩ基板
３ シリコン基板
３ａ 傾斜面
４ 絶縁膜
５ ＳＯＩ集積回路部
６ 接続パッド
７ 絶縁膜
８ 保護膜
１１ 下地金属層
１２ 配線
１３ 柱状電極
１４ 封止膜
１５ 半田ボール
１６ 金属膜
２１ 回路基板
２２ 接続パッド
２３ グランド用配線
２４ アンダーフィル材
２５ 接続部材
２６ 絶縁膜
２７ アンダーフィル材堰き止め材 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 SOI substrate 3 Silicon substrate 3a Inclined surface 4 Insulating film 5 SOI integrated circuit part 6 Connection pad 7 Insulating film 8 Protective film 11 Base metal layer 12 Wiring 13 Columnar electrode 14 Sealing film 15 Solder ball 16 Metal film 21 Circuit Substrate 22 Connection pad 23 Ground wiring 24 Underfill material 25 Connection member 26 Insulating film 27 Underfill material blocking material

Claims (11)

半導体基板、該半導体基板下に設けられた絶縁膜および該絶縁膜下に設けられたＳＯＩ集積回路部を有する半導体装置が回路基板上にフェースダウン方式で搭載され、前記半導体装置と前記回路基板との間にアンダーフィル材が設けられ、前記アンダーフィル材の外側における前記回路基板上に設けられたグランド用配線と前記半導体装置の半導体基板とが、導電性ペーストからなる接続部材、あるいは導電性ペーストまたは異方性導電接着剤を介して前記グランド用配線および前記半導体基板に接続される金属箔からなる接続部材により接続されていることを特徴とする半導体装置の実装構造。   A semiconductor device having a semiconductor substrate, an insulating film provided under the semiconductor substrate, and an SOI integrated circuit portion provided under the insulating film is mounted on the circuit substrate in a face-down manner, and the semiconductor device, the circuit substrate, An underfill material is provided in between, and a ground wiring provided on the circuit board outside the underfill material and the semiconductor substrate of the semiconductor device are a connection member made of a conductive paste, or a conductive paste Alternatively, the semiconductor device mounting structure is characterized by being connected by a connecting member made of a metal foil connected to the ground wiring and the semiconductor substrate via an anisotropic conductive adhesive. 請求項１に記載の発明において、前記接続部材は前記アンダーフィル材に固着されていることを特徴とする半導体装置の実装構造。   2. The semiconductor device mounting structure according to claim 1, wherein the connection member is fixed to the underfill material. 請求項１に記載の発明において、前記アンダーフィル材は前記半導体装置の周側面を覆うように設けられ、前記接続部材は前記グランド用配線の上面、その近傍の前記アンダーフィル材の外面およびその近傍の前記半導体装置の半導体基板の上面側に設けられていることを特徴とする半導体装置の実装構造。   2. The invention according to claim 1, wherein the underfill material is provided so as to cover a peripheral side surface of the semiconductor device, and the connection member is an upper surface of the ground wiring, an outer surface of the underfill material in the vicinity thereof, and a vicinity thereof. The semiconductor device mounting structure is provided on the upper surface side of the semiconductor substrate of the semiconductor device. 請求項１に記載の発明において、前記グランド用配線は前記半導体装置の一辺下に配置され、前記接続部材は前記グランド用配線の上面、前記半導体装置の一辺側側面およびその近傍の前記半導体装置の半導体基板の上面側に設けられていることを特徴とする半導体装置の実装構造。   The ground wiring is arranged under one side of the semiconductor device, and the connection member includes an upper surface of the ground wiring, a side surface of one side of the semiconductor device, and the vicinity of the semiconductor device. A mounting structure of a semiconductor device, which is provided on an upper surface side of a semiconductor substrate. 請求項４に記載の発明において、前記グランド用配線の内側における前記回路基板上にアンダーフィル材堰き止め部が設けられていることを特徴とする半導体装置の実装構造。   5. The semiconductor device mounting structure according to claim 4, wherein an underfill material damming portion is provided on the circuit board inside the ground wiring. 請求項３または４に記載の発明において、前記半導体装置の半導体基板の上面および前記接続部材の表面に絶縁膜が設けられていることを特徴とする半導体装置の実装構造。   5. The semiconductor device mounting structure according to claim 3, wherein an insulating film is provided on an upper surface of a semiconductor substrate of the semiconductor device and a surface of the connection member. 請求項３または４に記載の発明において、前記半導体装置の半導体基板の上面に導電膜が設けられ、該導電膜の上面に前記接続部材の一端部が設けられていることを特徴とする半導体装置の実装構造。   5. The semiconductor device according to claim 3, wherein a conductive film is provided on an upper surface of a semiconductor substrate of the semiconductor device, and one end portion of the connection member is provided on the upper surface of the conductive film. Implementation structure. 請求項３または４に記載の発明において、前記半導体装置の半導体基板の上面および周側面に導電膜が設けられ、該導電膜の上面に前記接続部材の一端部が設けられていることを特徴とする半導体装置の実装構造。   The invention according to claim 3 or 4, wherein a conductive film is provided on an upper surface and a peripheral side surface of a semiconductor substrate of the semiconductor device, and one end of the connection member is provided on the upper surface of the conductive film. Mounting structure of a semiconductor device. 請求項７または８に記載の発明において、前記導電膜の上面および前記接続部材の表面に絶縁膜が設けられていることを特徴とする半導体装置の実装構造。   9. The semiconductor device mounting structure according to claim 7, wherein an insulating film is provided on the upper surface of the conductive film and the surface of the connection member. 請求項３または４に記載の発明において、前記半導体装置の半導体基板の上面周辺部に傾斜面が設けられていることを特徴とする半導体装置の実装構造。   5. The semiconductor device mounting structure according to claim 3, wherein an inclined surface is provided in a peripheral portion of the upper surface of the semiconductor substrate of the semiconductor device. 請求項１に記載の発明において、前記半導体装置は前記ＳＯＩ集積回路部下に該ＳＯＩ集積回路部に接続されて設けられた複数の半田ボールを有し、前記半田ボールは前記回路基板上に設けられた接続パッドに接合されていることを特徴とする半導体装置の実装構造。   3. The semiconductor device according to claim 1, wherein the semiconductor device has a plurality of solder balls provided below the SOI integrated circuit portion and connected to the SOI integrated circuit portion, and the solder balls are provided on the circuit board. A mounting structure of a semiconductor device, wherein the mounting structure is bonded to a connection pad.
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JP2009152257A (en) * 2007-12-19 2009-07-09 Casio Comput Co Ltd Semiconductor device, and manufacturing method thereof

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