JP2002026178A - Semiconductor device and its manufacturing method, and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress leakage and infiltration of electromagnetic waves. SOLUTION: The semiconductor device comprises a wiring board, having first and second major surfaces facing each other; a plurality of first electrodes formed on the first major surface and a plurality of second electrodes formed on the second major surface; a semiconductor chip having a first major surface, on which a plurality of electrodes are formed and a second major surface facing the first major surface, in which the first major surface is placed on the wiring board while facing the first major surface of substrate and the plurality of electrodes of chip are connected electrically with the plurality of electrodes of substrate interposed with connecting means; and a conductive film covering the first major surface of substrate, the second major surface of chip and the side face of the wiring board.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a method of manufacturing the same, and an electronic device, and more particularly to a semiconductor device having a semiconductor chip on a wiring board, a manufacturing technology thereof, and a technology effective when applied to an electronic device. It is.

[0002]

2. Description of the Related Art Various types of package structures have been proposed and commercialized for semiconductor devices having a semiconductor chip having a built-in integrated circuit. For example, JP
Japanese Unexamined Patent Application Publication No. 270496 (published October 9, 1998) discloses a semiconductor device having a package structure called an underfill structure. In this semiconductor device having an underfill structure, a semiconductor chip is mounted on one main surface of a wiring board by a face down method, and one main surface of the wiring substrate and a circuit forming surface (one main surface) of the semiconductor chip are formed. The structure is such that a resin is filled between them. The face-down method is a method in which a semiconductor chip is mounted on one main surface of a wiring substrate in a state where a circuit formation surface of the semiconductor chip faces one main surface of the wiring substrate. The connection between the electrode formed on the circuit formation surface of the semiconductor chip and the electrode formed on one main surface of the wiring board is performed, for example, with a conductive bump interposed between the two electrodes. Semiconductor devices with an underfill structure
The heat dissipation is higher than that of a semiconductor device in which the entire semiconductor chip is sealed with resin, and the mounting area and the signal propagation path can be reduced as compared with the bonding wire method.

[0003] The face-down system is also employed in electronic devices such as CPU modules, memory modules, and high-frequency modules. The above publication discloses a CPU
An example in which a face-down system is adopted for a module is described.

[0004]

The operating frequency of integrated circuits has been increasing year by year, and in recent years, integrated circuits that operate at a high speed in the GHz (GHz) band have been mounted on semiconductor chips. In semiconductor devices and electronic devices incorporating such a semiconductor chip, it is necessary to take measures against electromagnetic waves. Electromagnetic waves are more likely to generate unnecessary radiation as the operating frequency of an integrated circuit increases, and their intensity also increases. Therefore, when a plurality of semiconductor devices are mounted on a module substrate (wiring substrate), a specific semiconductor device may generate The radiated electromagnetic wave causes a malfunction such that an integrated circuit of another semiconductor device malfunctions.

[0005] For this reason, a technique for countermeasures against electromagnetic waves is disclosed in, for example, Japanese Patent Application Laid-Open
000-31207 (published Jan. 28, 2000). The technology described in this publication discloses, `` By configuring the back surface of the face of a flip chip mounted face down on a substrate and the surface of the substrate as a ground conductor layer with a conductive metal layer, Since the conductive metal layer acts as a shielding metal for the signal transmission line formed in the inner layer of the substrate, no signal leakage from the flip chip itself, the flip chip mounting land and the signal transmission line occurs, Since there is no need to use a special metal case for shielding, the size of the substrate on which the flip chip is mounted can be reduced. "

However, since the wiring board has a multilayer conductive structure (multilayer wiring structure) in which an insulating layer and a conductive layer are sequentially stacked, electromagnetic waves leak to the outside from the side surface of the wiring board through the insulating layer. I do. Further, an electromagnetic wave generated outside propagates through the insulating layer from the side surface of the wiring board and enters the inside. That is, it is difficult for the above-described technology to take measures against electromagnetic waves propagating in a planar direction inside the wiring board.

An object of the present invention is to provide a technique capable of suppressing leakage and intrusion of electromagnetic waves.

Another object of the present invention is to provide a semiconductor device having high reliability against electromagnetic waves.

Another object of the present invention is to provide an electronic device having high reliability against electromagnetic waves.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. (1) A semiconductor device according to the present invention includes a first substrate main surface and a second substrate main surface facing each other, a plurality of first substrate electrodes formed on the first substrate main surface, and a second substrate main surface. A wiring substrate having a plurality of second substrate electrodes formed on a first chip main surface on which circuits and a plurality of chip electrodes are formed; and a second chip main surface facing the first chip main surface. A semiconductor chip having the first chip main surface disposed on the wiring board in a state where the first chip main surface faces the first substrate main surface,
And a semiconductor chip in which the plurality of chip electrodes are electrically connected to the plurality of first substrate electrodes via connection means, respectively, and the first chip main surface, the second chip main surface, and the wiring substrate. A conductive film that covers the side surface. The conductive film is electrically connected to a second substrate electrode to which a fixed potential is supplied, among the plurality of second substrate electrodes.

(2) A semiconductor device according to the present invention is a wiring board having a plurality of substrate electrodes on one main surface and a semiconductor chip having a circuit and a plurality of chip electrodes on one main surface, wherein the one main surface is A semiconductor chip disposed on the wiring board so as to face one main surface of the wiring board, wherein the plurality of chip electrodes are electrically connected to the plurality of board electrodes via connection means; The wiring board has two layers of first fixed potential planes therein and the second fixed potential plane.
A first fixed potential plane formed between the first and second fixed potential planes, a signal wiring and a second fixed potential plane formed on a conductive layer between the two insulating layers, The first
The thickness of the insulating layer between the fixed potential plane and the second fixed potential plane is smaller than 1/100 of the wavelength of the electromagnetic wave. The wavelength of the electromagnetic wave is defined by “propagation speed of light (electromagnetic wave) in medium / operating frequency of circuit”.

(3) The electronic device of the present invention comprises a wiring board having a plurality of substrate electrodes on one main surface, and first and second semiconductor chips having a circuit and a plurality of chip electrodes on one main surface, The one main surface was disposed on the wiring substrate in a state facing the one main surface of the wiring substrate, and the plurality of chip electrodes were electrically connected to the plurality of substrate electrodes via connection means, respectively. First and second semiconductor chips,
An electromagnetic wave barrier to which a fixed potential is supplied is provided inside the wiring board between the first semiconductor chip and the second semiconductor chip. The electromagnetic wave barrier is constituted by a conductor formed in a plurality of via holes. The distance between the via holes is smaller than 1/100 of the wavelength of the electromagnetic wave.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) In the present embodiment, a semiconductor chip is mounted on one main surface of a wiring board by a face-down method, and an external surface is provided on a back surface (other main surface) opposite to one main surface of the wiring substrate. An example in which the present invention is applied to a BGA type semiconductor device in which a plurality of ball-shaped bumps (conductive bumps) are arranged as connection terminals will be described.

FIG. 1 is a schematic plan view of the semiconductor device of the first embodiment, FIG. 2 is a schematic cross-sectional view taken along the line aa of FIG. 1, and FIG. FIG. 4 is a schematic plan view showing a first conductive layer pattern in the wiring board of FIG. 4, and FIG. 4 is a schematic plan view showing a second conductive layer pattern in the wiring board of the first embodiment. Yes, Figure 5
FIG. 6 is a schematic plan view showing a third conductive layer pattern in the wiring board of the first embodiment. FIG. 6 is a diagram showing a fourth conductive layer pattern in the wiring board of the first embodiment. FIG. 7 is a schematic plan view showing a fifth conductive layer pattern in the wiring board according to the first embodiment, and FIG. 8 is a schematic plan view showing a fifth conductive layer pattern in the wiring board according to the first embodiment. FIG. 9 is a schematic plan view showing a sixth conductive layer pattern, and FIG.
FIG. 1 is a schematic plan view showing a conductive layer pattern of a layer, and FIG.
0 is a schematic sectional view showing a multilayer state of the wiring board of the first embodiment, FIG. 11 is a schematic sectional view showing a multilayer state of the wiring board of the first embodiment, and FIG. FIG. 13 is a schematic plan view showing an arrangement pattern of conductors provided in via holes of a second insulating layer in the wiring board according to the first embodiment. FIG. 13 shows a multilayer state of the wiring board according to the first embodiment. FIG. 14 is a schematic cross-sectional view showing a state in which the semiconductor device of the first embodiment is mounted on a mounting board.

FIG. 10 is a sectional view taken along the sectional direction of FIG. 2, and FIGS. 11, 13 and 17 are sectional views taken along a direction perpendicular to the sectional direction of FIG.

As shown in FIGS. 1 and 2, the first embodiment
In the semiconductor device 1A, a semiconductor chip 30 is mounted in a face-down manner on one main surface 2X of one main surface 2X and another main surface (rear surface) 2Y of the wiring substrate 1 facing each other. A plurality of ball-shaped bumps 35 are arranged as external connection terminals on the back surface 2Y side. The planar shape of the wiring board 2 and the semiconductor chip 30 is formed in a square shape, and in the present embodiment, is formed in a rectangular shape.

The semiconductor chip 30 has, for example, 10 [GH
A frequency conversion circuit for an optical transmission module that operates at high speed in the [z] band is mounted. A plurality of electrodes 30A are formed on a circuit forming surface 30X of a circuit forming surface (one main surface) 30X and a back surface (another main surface) 30Y of the semiconductor chip 30 facing each other.

The wiring board 2 has a multilayer wiring structure in which an insulating layer and a conductive layer are sequentially stacked. In the present embodiment, seven conductive layers are provided, and six insulating layers (4, 4) are provided.
7, 10, 13, 16, 19) are provided. Each insulating layer is formed of, for example, an insulating film made of a glass ceramic material, and each conductive layer is formed of, for example, a metal film made of copper (Cu) or a copper-based alloy material. Each insulating layer (4
7, 10, 13, 16, 19), a plurality of via holes are formed, and a conductor (5, 5) is formed inside these via holes.
8, 11, 14, 17, 20) are formed.

As shown in FIG. 3, a plurality of electrodes 3A and 3B are formed on the first conductive layer. Electrode 3
A is disposed in a chip mounting area where the semiconductor chip 30 is mounted, and the electrode 3B is disposed outside the chip mounting area. The plurality of electrodes 3A are arranged in a grid (in a matrix) inside the chip mounting area.

As shown in FIG. 4, a fixed potential plane 6A to which a reference potential (eg, 0 [V] potential) is supplied as a fixed potential is formed in the second conductive layer. A plurality of openings 6B are formed in the plane 6A. The openings 6B are formed in a smaller number than the electrodes 3A,
It is arranged at a position facing the first layer electrode 3A.
Inside the opening 6B, among the plurality of conductors 5 provided in the insulating layer 4, a conductor 5 for electrically connecting any of the upper and lower conductive layers is arranged.

As shown in FIG. 5, a fixed potential plane 9A to which the same fixed potential as that of the fixed potential plane 6A is supplied is formed in the third conductive layer, and a plurality of signal wirings 9D are formed. Is formed. 9A fixed potential plane
Are formed with a plurality of openings 9B and 9C. Opening 9
B is formed in a smaller number than the openings 6B of the second layer, and is arranged at a position facing the openings 6B. Signal wiring 9D
Are formed inside the opening 9D. The signal wiring 9D extends from a region facing the chip mounting region toward the outside thereof. One end of the signal wiring 9D is disposed at a position facing the outermost electrode 3A among the plurality of electrodes 3A of the first layer. A plurality of signal wirings 9D have 10
A high frequency signal in the [GHz] band is supplied. Inside the opening 9B, among the plurality of conductors 8 provided in the insulating layer 7, a conductor 8 for electrically connecting any of the upper and lower conductive layers is arranged. A conductor 8 electrically connected to the conductor 5 is electrically connected to one end of the signal wiring 9D. The other end of the signal wiring 9D is electrically connected to one of the plurality of conductors 11 provided in the insulating layer 10 and arranged opposite to the other end of the signal wiring 9D. I have.

As shown in FIG. 6, a fixed potential plane 12A to which the same fixed potential as the first fixed potential plane 6A is supplied is formed in the fourth conductive layer. In the fixed potential plane 12A, a plurality of openings 12B are formed in a region facing the chip mounting region, and further, a plurality of openings 12C are formed on the peripheral side of the wiring board 2. The openings 12B are formed in a smaller number than the openings 9B of the third layer, and are arranged at positions facing the openings 9B.
The openings 12C are formed in the same number as the third-layer signal wires 9C, and are arranged at positions facing the other end of the signal wires 9C. An insulating layer 10 is provided inside the openings 12B and 12C.
Among the plurality of conductors 11 provided therein, the conductor 11 for electrically connecting any of the upper and lower conductive layers is disposed.

As shown in FIG. 7, in the fifth conductive layer, a fixed potential plane 15A to which the same fixed potential as the first fixed potential plane 6A is supplied is formed.
Further, a fixed potential plane 15E to which a power supply potential is supplied as a fixed potential is formed. In this embodiment,
Four fixed potential planes 15E are provided, and different power supply potentials are supplied to these fixed potential planes 14E. A plurality of openings 15B are formed in the fixed potential plane 15A in a region facing the chip mounting region, and a plurality of openings 15C are formed in the peripheral side of the wiring board 2. The openings 15B are formed in a smaller number than the openings 12B of the fourth layer, and are arranged at positions facing the openings 12B. The openings 15C are formed in the same number as the openings 12C, and are arranged at positions facing the openings 12C. Opening 15B
And 15C, a conductor 14 for electrically connecting any of the upper and lower conductive layers among the plurality of conductors 14 provided in the insulating layer 13 is arranged.

As shown in FIG. 8, a fixed potential plane 18A to which the same fixed potential as the first fixed potential plane 6A is supplied is formed in the sixth conductive layer.
Further, a plurality of signal wirings 18D are formed. The signal wiring 18D extends outward from a region facing the chip mounting region. One end of the signal wiring 18D is arranged at a position facing the opening 15B of the fifth layer.
A signal having a relatively low frequency of several KHz is supplied to the plurality of signal wirings 18D. Fixed potential plane 18A
Are formed with a plurality of openings 18C on the peripheral edge side of the wiring board 2. The opening 18C is arranged at a position facing the opening 15C of the fifth layer. Inside the opening 18C, among the plurality of conductors 17 provided in the insulating layer 16, a conductor 17 for electrically connecting one of the upper and lower conductor layers is arranged. The conductor 17 electrically connected to the conductor 14 is electrically connected to one end of the signal wiring 18D. The other conductor of the plurality of conductors 20 provided in the insulating layer 19 is electrically connected to the other end of the signal wiring 18D so as to face the other end of the signal wiring 18D. I have.

As shown in FIG. 9, a plurality of electrodes 21 are formed on the seventh conductive layer. Multiple electrodes 21
Are arranged in two rows along the periphery of the wiring board 2.

Among the plurality of electrodes 3A, the electrode 3A to which the reference potential is supplied is connected to the fixed potential plane 6 via the conductor 5.
A, the fixed potential plane 6A is electrically connected to the fixed potential plane 9A via the conductor 8, and the fixed potential plane 9A is electrically connected to the fixed potential plane 9A via the conductor 11. The fixed potential plane 12A is electrically connected to the fixed potential plane 12A via a conductor 14, and the fixed potential plane 15A is electrically connected to the fixed potential plane 15A via a conductor 17. The fixed potential plane 18A is electrically connected to the electrode 21 via the conductor 20.

Of the plurality of electrodes 3A, the electrode 3A to which the power supply potential is supplied is electrically connected to the fixed potential plane 15E via the conductors 5, 8, 11, and 14, and the fixed potential plane 15E is Electrode 2 via conductors 17 and 20
1 and is electrically connected.

Of the plurality of electrodes 3A, the electrode 3A to which a high-frequency signal is supplied is electrically connected to one end of a signal wiring 9D via conductors 5 and 8, and the other end of the signal wiring 9D is electrically conductive. It is electrically connected to the electrode 21 via the bodies 11, 14, 17, 20.

Of the plurality of electrodes 3A, the electrode 3A to which a signal having a relatively low frequency is supplied is one of the conductors 5, 8, 11, 1
The other end of the signal line 18D is electrically connected to the electrode 21 via the conductor 20 via the conductors 4 and 17.

The plurality of electrodes 3B are electrically connected to the fixed potential plane 6A via the conductor 5.

Electrode 3A formed on one main surface of wiring board 2
And the electrodes 30A formed on the circuit forming surface 30X of the semiconductor chip 30 are connected to the conductive bumps 3 interposed therebetween.
1 electrically and mechanically connected. As the conductive bump 31, for example, 3 [% by weight] Ag-97 is used.
[Weight%] A conductive bump made of an alloy material having a Sn composition is used.

One main surface 2X of the wiring board 2 and the semiconductor chip 3
The resin 32 is filled between the circuit board 30 and the circuit forming surface 30X.
These are sealed with a resin 32. Resin 3
As 2, for example, an epoxy-based thermosetting resin to which a silica filler, a curing accelerator, a coupling agent, and the like are added is used.

A ball-shaped bump 35 is formed on the electrode 21 on the back surface 2Y of the wiring board 2. As the ball-shaped bump, for example, 37 [% by weight] Pb-63 [% by weight] S
A conductive bump made of an alloy material having an n composition is used.

The back surface 30 Y and side surfaces of the semiconductor chip 30 and the one main surface 2 X and side surfaces of the wiring board 2 are covered with a conductive film 34. The conductive film 34 is electrically connected to the electrode 3B on one main surface 2X of the wiring board 2. That is,
The conductive film 34 is fixed at a reference potential. The conductive film 34 is formed of, for example, a Cu film formed by a sputtering method.

In the present embodiment, the back surface 30Y and the side surface of the semiconductor chip 30 and the one main surface 2X and the side surface of the wiring board 2 are covered with a conductive film 34 that is fixed at a reference potential, and a high-frequency signal is supplied. The wiring 9D is connected to the fixed potential planes 6A and 12A that are fixed to the reference potential.
A. Therefore, electromagnetic waves generated from the semiconductor chip 30, the conductive bumps 31, and the signal wiring of the wiring board 2 by the operation of the high-frequency circuit formed on the semiconductor chip 30 are reflected by the conductive film 34 and the fixed potential planes (6A, 12A). Alternatively, since the electromagnetic waves are absorbed, electromagnetic waves leaking to the outside of the package can be suppressed. In addition, since the electromagnetic wave generated outside the package is reflected or absorbed by the conductive film 34, the electromagnetic wave entering the inside of the package can be suppressed.

On the other hand, since the electromagnetic wave propagating through the insulating layer of the wiring board 2 is reflected or absorbed by the conductive film 34 covering the side surface of the wiring board 2, the electromagnetic wave propagates through the insulating layer inside the wiring board 2 and is Electromagnetic waves leaking to the vehicle can be suppressed. In addition, since the electromagnetic wave generated outside the package is reflected or absorbed by the conductive film 34 covering the side surface of the wiring board 2, the electromagnetic wave propagating through the insulating layer from the side surface of the wiring board 2 and entering the inside of the package is suppressed. can do.

The electromagnetic wave propagating through the insulating layer of the wiring board 2 is
As shown in FIGS. 10 and 11, the thickness of the insulating layer between the fixed potential planes (gap between the fixed potential planes)
It can be suppressed by making t1 smaller than one hundredth of the electromagnetic wave wavelength. The wavelength of the electromagnetic wave is defined by “propagation speed of light (electromagnetic wave) in medium / operating frequency of circuit”. In this embodiment, the operating frequency of the circuit is 10
[GHz], the thickness t1 of the insulating layer is set to 0.15 [μ
m] or less, it is possible to suppress electromagnetic waves that propagate through the insulating layer of the wiring board 2 and leak to the outside of the package and electromagnetic waves that enter the inside of the package.

The electromagnetic wave propagating through the insulating layer of the wiring board 2 can be suppressed by providing an electromagnetic wave barrier to which a fixed potential is supplied to the insulating layer between the fixed potential planes. As shown in FIGS. 12 and 13, the electromagnetic wave barrier according to the present embodiment includes a plurality of conductors (8, 11, 1, 1) arranged at predetermined intervals along the periphery of the wiring board 2.
4, 17). These conductors are formed inside via holes formed in the insulating layer. The distance between the conductors (8, 11, 14, 17), ie,
The interval between the via holes is smaller than one hundredth of the electromagnetic wave wavelength. By providing the electromagnetic wave barrier having such a configuration on the insulating layer between the fixed potential planes, the wiring board 2
Electromagnetic waves that propagate through the insulating layer and leak out of the package and electromagnetic waves that enter the inside of the package can be suppressed.

The electromagnetic wave barrier may be formed by forming a frame-shaped via hole extending continuously along the periphery of the wiring board 2 in the insulating layer, and using a conductor formed inside the via hole. .

The semiconductor device 1A thus configured is
As shown in FIG. 14, in the assembly process of the electronic device, the electronic device is mounted on the mounting board 40 together with other mounted components.
The mounting of the semiconductor device 1A is performed by melting the ball-shaped bumps 35 and electrically and mechanically connecting the electrodes 21 on the back surface 2Y of the wiring board 2 and the electrodes 40A on the mounting surface of the mounting board 40.

Next, the manufacture of the semiconductor device 1A will be described with reference to FIGS. FIG. 15 and FIG. 16 are schematic cross-sectional views for explaining the manufacture of the semiconductor device.

First, a wiring board 2 is prepared.
As shown in FIG. 5A, the conductive bumps 31 are formed on the plurality of electrodes 3A formed on one main surface 2X of the wiring board 2. The conductive bump 31 is formed by, for example, but not limited to, supplying a solder ball having a Pb-Sn composition onto the electrode 3A of the wiring board 2 by a ball supply method, and then melting the solder ball.

Next, the semiconductor chip 30 is positioned on the one main surface 2X of the wiring board 2 with the circuit forming surface 30X of the semiconductor chip 30 facing the one main surface 2X of the wiring board 2,
Thereafter, the conductive bumps 31 are melted, and the electrodes 3A of the wiring board 2 and the electrodes 30A of the semiconductor chip 30 are electrically and mechanically connected. By this step, the semiconductor chip 30 is mounted on the one main surface 2X of the wiring board 1.

Next, a resin 32 is filled between the one main surface 2X of the wiring board 2 and the circuit forming surface 30X of the semiconductor chip 30, and as shown in FIG. Seal with 32.

Next, a protective film 33 is formed on the back surface 1Y of the wiring board 2.
Then, as shown in FIG. 15C, the back surface 1Y of the wiring board 1 is covered with a protective film 33. As the protective film 33, for example, a film made of a silicone resin having excellent heat resistance is used. Since the silicone resin can be easily separated after being attached, the electrode 21 on the back surface of the wiring board 2 is not damaged. Also, workability is good.

Next, the wiring substrate 2 is placed in, for example, a chamber of a sputtering apparatus, and a metal film 34 made of, for example, a Cu film is formed as shown in FIG. In this step, since the back surface 2Y of the wiring board 2 is covered with the protective film 33, the conductive film 34 is not formed on the back surface 2Y of the wiring board 2.

Next, as shown in FIG. 16B, by removing the protective film 33 from the back surface of the wiring substrate 2, the conductive film 34 is not formed on the back surface of the wiring substrate 2, and the semiconductor chip is not formed. 30 back surface 30Y and side surface and wiring substrate 2
The conductive film 34 that covers the one main surface 2X and the side surface can be selectively formed.

Next, a ball-shaped bump 35 is formed on the electrode 21 on the back surface 2Y of the wiring board 2, whereby the semiconductor device 1A of the present embodiment is almost completed.

As described above, according to the present embodiment, the following effects can be obtained. (1) The back surface 30Y and the side surface of the semiconductor chip 30 and the one main surface 2X and the side surface of the wiring board 2 are covered with the conductive film 34. With such a configuration, the electromagnetic waves generated from the semiconductor chip 30, the conductive bumps 31, and the signal wiring of the wiring board 2 by the operation of the high-frequency circuit formed on the semiconductor chip 30 are transmitted to the conductive film 34 and the fixed potential plane. Since the light is reflected or absorbed by (6A, 12A), electromagnetic waves leaking to the outside of the package can be suppressed. In addition, since electromagnetic waves generated outside the package are reflected or absorbed by the conductive film 34, it is possible to suppress electromagnetic waves entering the inside of the package,
The occurrence of a malfunction of the circuit can be suppressed. On the other hand, since the electromagnetic wave propagating through the insulating layer of the wiring board 2 is reflected or absorbed by the conductive film 34 covering the side surface of the wiring board 2, it propagates through the insulating layer inside the wiring board 2 and leaks out of the package. Electromagnetic waves can be suppressed. In addition, since the electromagnetic wave generated outside the package is reflected or absorbed by the conductive film 34 covering the side surface of the wiring board 2, the electromagnetic wave propagating through the insulating layer from the side surface of the wiring board 2 and entering the inside of the package is suppressed. And the occurrence of a malfunction of the circuit can be suppressed. Further, since an electromagnetic wave leaking to the outside of the package and an electromagnetic wave entering the inside of the package can be suppressed, a semiconductor device with high reliability against electromagnetic waves can be provided.

(2) The thickness t1 of the insulating layer between the fixed potential planes (gap between the fixed potential planes) is made smaller than 1/100 of the wavelength of the electromagnetic wave. With such a configuration, it is possible to suppress electromagnetic waves that propagate through the insulating layer of the wiring board 2 and leak to the outside of the package and electromagnetic waves that enter the inside of the package, thereby suppressing occurrence of malfunction of the circuit. As a result, a semiconductor device with high reliability against electromagnetic waves can be provided.

(3) In the insulating layer between the fixed potential planes,
An electromagnetic wave barrier to which a fixed potential is supplied is provided. With such a configuration, it is possible to suppress electromagnetic waves that propagate through the insulating layer of the wiring board 2 and leak to the outside of the package and electromagnetic waves that enter the inside of the package, thereby suppressing occurrence of malfunction of the circuit. As a result, a semiconductor device with high reliability against electromagnetic waves can be provided.

(4) A conductive film 34 is formed with the back surface of the wiring board 2 covered with the protective film 33, and then the protective film 33 is peeled off. As a result, the back surface 30Y of the semiconductor chip 30 is formed without forming the conductive film 34 on the back surface of the wiring substrate 2.
And the conductive film 34 covering the side surface and the one main surface 2X and the side surface of the wiring board 2 can be selectively formed.

In this embodiment, an example is described in which the fixed potential plane 9A and the signal wiring 9D are formed on the third conductive layer. However, as shown in FIG. 17, the third conductive layer is formed on the third conductive layer. When the fixed potential plane is not formed, the electromagnetic waves propagating through the insulating layer of the wiring board 2 are separated by the film thickness of the two insulating layers between the fixed potential planes (the fixed potential plane 6).
The gap (t3 between A and 12A) can be suppressed by making it smaller than 1/100 of the wavelength of the electromagnetic wave.

In this embodiment, an example in which the entire side surface of the wiring board 2 is covered with the conductive film 34 has been described. However, the potential fixing plane 12A is located below the signal wiring 9D to which a high-frequency signal is supplied. In this case, leakage and penetration of electromagnetic waves can be suppressed by covering the side surface of the wiring board 2 with the conductive film 34 to the same level as or lower than the potential fixing plane 12A.

In the present embodiment, the example in which the conductive film 34 is formed by using the sputtering method has been described. However, the film formation of the conductive film 34 is not limited to this. The conductive film 34 may be formed by using any one of a chemical vapor deposition method and a chemical vapor deposition method.

Further, in the present embodiment, the example in which the conductive film 34 is formed integrally from the one main surface 2X of the wiring substrate 2 to the side surface has been described. The side surface of the wiring board 2 may be covered with the separated conductor. However, in this case, the number of assembling steps of the semiconductor device increases, and a gap is easily generated between the conductive film covering one main surface of the wiring substrate 2 and the conductor covering the side surface of the wiring substrate 1. Therefore, by integrally forming the conductive film 34 from one main surface to the side surface of the wiring board 2 as in the present embodiment, it is possible to reduce the number of assembly steps and suppress leakage of electromagnetic waves.

Although an example in which a Cu film is used as the conductive film 34 has been described, the conductive film 34 may be a nickel (Ni) film, a silver (Ag) film, a gold (Au) film, or a platinum (P) film.
Any of t) film, palladium (Pd) film, carbon (C) film, and aluminum (Al) film or an alloy film thereof may be used.

In the present embodiment, the conductive bumps 31
Has been described as an example using a conductive bump made of an alloy material having a Pb-Sn composition, but the conductive bump 31 may have another composition.

In this embodiment, the example in which the conductive bumps 31 are formed on the electrodes 3A of the wiring board 2 has been described.
It may be formed on A.

In the present embodiment, an example in which the conductive bumps 31 are used as means for electrically connecting the electrodes 3A of the wiring board 2 and the electrodes 30A of the semiconductor chip 30 has been described. a number of conductive particles anisotropic conductive resin is mixed in an insulating resin (e.g. ACF: a nisotropic C onductive F ilm ), or may be an anisotropic conductive resin and a conductive bump .

In this embodiment, an example in which the present invention is applied to a BGA type semiconductor device has been described.
The electrode L on the back surface of the wiring board 2 is used as an external connection terminal.
It can be applied to GA (L and G rid A rray ) type semiconductor device.

(Embodiment 2) FIG. 18 is a schematic cross-sectional view showing a state where a semiconductor device according to Embodiment 2 of the present invention is mounted on a mounting board, and FIG. 19 is a sectional view of the semiconductor device according to Embodiment 2 of the present invention. It is a bottom view.

As shown in FIGS. 18 and 19, the semiconductor device 1B of the present embodiment has basically the same configuration as that of the above-described first embodiment, but differs in the following configuration.

That is, the conductor 36 extending along the periphery of the wiring board 2 is provided on the back surface 2Y side of the wiring board 2. The conductor 36 is electrically connected to the electrode 21 of the wiring substrate 2 to which the reference potential is supplied.
With this configuration, it is possible to suppress electromagnetic waves leaking to the outside of the package from between the mounting board 40 and the wiring board 2 and electromagnetic waves entering the inside of the package from between the mounting board 40 and the wiring board 2. And the occurrence of a malfunction of the circuit can be suppressed.

The conductor 36 may be provided on the mounting board 40 side.

(Embodiment 3) In this embodiment, an example in which the present invention is applied to a module (electronic device) having a semiconductor chip mounted on one main surface of a wiring board in a face-down manner will be described.

FIG. 20 is a schematic sectional view of a module according to the third embodiment of the present invention.

As shown in FIG. 20, the module 45 of the present embodiment includes a first main surface 2 of a wiring board (module board) 2.
The configuration is such that two semiconductor chips 30 are mounted on X in a face-down manner. An electromagnetic wave barrier to which a fixed potential is supplied is provided inside the wiring board 2 between one semiconductor chip 30 and the other semiconductor chip 30. The electromagnetic wave barrier of the present embodiment is made of a conductor formed in a via hole, as in the first embodiment (see FIGS. 12 and 13). The electromagnetic wave barrier is formed so as to surround one semiconductor chip 30. With such a configuration, electromagnetic waves propagating through the insulating layer of the wiring board 2 can be suppressed, so that occurrence of a malfunction of the circuit can be suppressed. As a result, it is possible to provide a module 45 with high reliability against electromagnetic waves.

In the present embodiment, an example has been described in which an electromagnetic wave barrier is provided on the insulating layer of the wiring board 2 to suppress electromagnetic waves propagating through the insulating layer of the wiring board 2, as shown in FIGS. 10 and 11. The thickness t1 of the insulating layer between the fixed-potential planes (gap between the fixed-potential planes) is made smaller than 1/100 of the wavelength of the electromagnetic wave to suppress the electromagnetic wave propagating through the insulating layer of the wiring board 2. Is also good. Also in this case, the module 45 having high reliability against electromagnetic waves is used.
Can be provided.

As described above, the invention made by the present inventor
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

[0073]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

According to the present invention, leakage and intrusion of electromagnetic waves can be suppressed.

According to the present invention, a semiconductor device having high reliability against electromagnetic waves can be provided.

According to the present invention, it is possible to provide an electronic device having high reliability against electromagnetic waves.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view taken along line aa of FIG.

FIG. 3 is a schematic plan view showing a first conductive layer pattern in the wiring board according to the first embodiment.

FIG. 4 is a schematic plan view showing a second conductive layer pattern in the wiring board according to the first embodiment.

FIG. 5 is a schematic plan view showing a third conductive layer pattern in the wiring board according to the first embodiment.

FIG. 6 is a schematic plan view showing a fourth conductive layer pattern in the wiring board according to the first embodiment.

FIG. 7 is a schematic plan view showing a fifth conductive layer pattern in the wiring board according to the first embodiment.

FIG. 8 is a schematic plan view showing a sixth conductive layer pattern in the wiring board according to the first embodiment.

FIG. 9 is a schematic plan view showing a seventh conductive layer pattern in the wiring board according to the first embodiment.

FIG. 10 is a schematic sectional view showing a multilayer state of the wiring board according to the first embodiment.

FIG. 11 is a schematic sectional view showing a multilayer state of the wiring board according to the first embodiment.

FIG. 12 is a schematic plan view showing a wiring pattern of a conductor provided in a via hole of a second insulating layer in the wiring board according to the first embodiment.

FIG. 13 is a schematic cross-sectional view illustrating a multilayer state of the wiring board according to the first embodiment.

FIG. 14 is a schematic cross-sectional view showing a state where the semiconductor device of the first embodiment is mounted on a mounting board.

FIG. 15 is a schematic cross-sectional view for explaining the manufacture of the semiconductor device according to the first embodiment of the present invention.

FIG. 16 is a schematic cross-sectional view for explaining the manufacture of the semiconductor device according to the first embodiment of the present invention.

FIG. 17 is a schematic cross-sectional view showing a multilayer state of a wiring board according to a modification of the first embodiment.

FIG. 18 is a schematic cross-sectional view showing a state where the semiconductor device according to the second embodiment of the present invention is mounted on a mounting board.

FIG. 19 is a schematic bottom view of the wiring board according to the second embodiment.

FIG. 20 is a schematic sectional view illustrating a schematic configuration of a module that is Embodiment 3 of the present invention.

[Explanation of symbols]

1A, 1B: semiconductor device, 2: wiring board, 3A, 3B ...
Electrodes, 4, 7, 10, 13, 16, 19 ... insulating layer, 6
A, 9A, 12A, 15A, 18A ... potential fixing plane, 6B, 9B, 9C, 12B, 12C, 15B, 15
C: opening, 9D, 18D: signal wiring, 30: semiconductor chip, 30A: electrode, 31: conductive bump, 32: resin,
33: protective film, 34: conductive film, 35: ball-shaped bump,
40: mounting board; 45: module.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Teruyoshi Hayashi 6-16-16 Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Hiroshi Kikuchi 6--16 Shinmachi, Ome-shi, Tokyo 3 Hitachi, Ltd. Device Development Center (72) Inventor Norio Nakazato 502, Kandate-cho, Tsuchiura-shi, Ibaraki F-term, Machinery Research Laboratory, Hitachi, Ltd. F-term (reference) 5E321 AA17 AA21 BB23 GG05

Claims (23)

[Claims] A first substrate main surface and a second substrate main surface facing each other; a plurality of first substrate electrodes formed on the first substrate main surface; and a plurality of first substrate electrodes formed on the second substrate main surface. A semiconductor chip having a first chip main surface on which a circuit and a plurality of chip electrodes are formed, and a second chip main surface facing the first chip main surface. The first chip main surface is disposed on the wiring board in a state where the first chip main surface faces the first substrate main surface, and the plurality of chip electrodes are electrically connected to the plurality of first substrate electrodes via connection means. A semiconductor device comprising: a semiconductor chip which is electrically connected; and a conductive film which covers the first substrate main surface, the second chip main surface, and a side surface of the wiring substrate. 2. The semiconductor device according to claim 1, wherein the conductive film is electrically connected to a second substrate electrode supplied with a fixed potential among the plurality of second substrate electrodes. Characteristic semiconductor device. 3. The semiconductor device according to claim 1, wherein the conductive film is formed integrally from the main surface of the first substrate to a side surface of the wiring substrate. 4. The semiconductor device according to claim 1, wherein the wiring substrate has therein a signal wiring, and a fixed potential plane located below the signal wiring and supplied with a fixed potential. Wherein the conductive film covers the same or lower than the fixed potential plane in the thickness direction of the wiring substrate. 5. The semiconductor device according to claim 1, wherein said connection means is a conductive bump. 6. The semiconductor device according to claim 1, wherein a space between the wiring substrate and the semiconductor chip is sealed with a resin. 7. The semiconductor device according to claim 1, further comprising a plurality of conductive bumps respectively connected to the plurality of second substrate electrodes on the second substrate main surface side. . 8. The semiconductor device according to claim 1, wherein a fixed potential of the plurality of second substrate electrodes extends on a side of the second substrate main surface along a peripheral edge of the wiring substrate. A semiconductor device having a conductor electrically connected to a supplied second substrate electrode. 9. A first substrate main surface and a second substrate main surface facing each other, a plurality of first substrate electrodes formed on the first substrate main surface, and a plurality of first substrate electrodes formed on the second substrate main surface. A semiconductor chip having a first chip main surface on which an integrated circuit and a plurality of chip electrodes are formed, and a second chip main surface facing the first chip main surface. And wherein the first chip main surface is disposed on the wiring substrate in a state where the first chip main surface faces the substrate first main surface, and the plurality of chip electrodes are respectively connected to the plurality of first substrate electrodes via connection means. A semiconductor chip that is electrically connected, a resin that seals between the wiring substrate and the semiconductor chip, and a conductive film that covers the first substrate main surface, the second chip main surface, and a side surface of the wiring substrate A method of manufacturing a semiconductor device comprising: The method of manufacturing a semiconductor device characterized by forming the conductive film in a state of covering the second substrate main surface with a protective film. 10. The method for manufacturing a semiconductor device according to claim 9, wherein the conductive film is formed by using any one of a sputtering method, an electroless plating method, a vacuum deposition method, and a chemical vapor deposition method. A method of manufacturing a semiconductor device. 11. A step of attaching the protective film to the main surface of the second substrate before the step of forming the conductive film, and a step of removing the protective film after forming the conductive film. A method for manufacturing a semiconductor device, comprising: 12. The method for manufacturing a semiconductor device according to claim 1, wherein said protective film is made of a silicone resin. 13. A wiring board having a plurality of substrate electrodes on one main surface, and a semiconductor chip having a circuit and a plurality of chip electrodes on one main surface, wherein said one main surface is provided on one main surface of said wiring substrate. A semiconductor chip disposed on the wiring board in a facing state, and wherein the plurality of chip electrodes are electrically connected to the plurality of substrate electrodes via connection means, respectively; Inside, two layers of the first fixed potential plane, two insulating layers formed between the two first fixed potential planes, and a conductive layer between the two insulating layers are formed. The thickness of the insulating layer between the plane for the first fixed potential and the plane for the second fixed potential is 1/100 of the wavelength of the electromagnetic wave. Semiconductor device characterized by being smaller than Place. 14. The semiconductor device according to claim 13, further comprising a conductive film covering one main surface of said wiring board and another main surface facing said one main surface of said semiconductor chip. apparatus. 15. A wiring board having a plurality of substrate electrodes on one main surface, and a semiconductor chip having a circuit and a plurality of chip electrodes on one main surface, wherein said one main surface is one of said main surfaces of said wiring substrate. A semiconductor chip disposed on the wiring board in a facing state, and wherein the plurality of chip electrodes are electrically connected to the plurality of substrate electrodes via connection means, respectively; Inside, two fixed potential planes, two insulating layers formed between the two fixed potential planes, and a signal wiring formed on a conductive layer between the two insulating layers And the thickness of the two insulating layers is 1/100 of the electromagnetic wave wavelength.
A semiconductor device characterized by being smaller than the above. 16. The semiconductor device according to claim 15, further comprising a conductive film covering one main surface of said wiring substrate and another main surface facing said one main surface of said semiconductor chip. apparatus. 17. A wiring board having a plurality of substrate electrodes on one main surface, and a semiconductor chip having a circuit and a plurality of chip electrodes on one main surface, wherein said one main surface is provided on one main surface of said wiring substrate. A semiconductor chip disposed on the wiring board in a facing state, and wherein the plurality of chip electrodes are electrically connected to the plurality of substrate electrodes via connection means, respectively; Inside, two layers of the first fixed potential plane, two insulating layers formed between the two first fixed potential planes, and a conductive layer between the two insulating layers are formed. A signal wiring and a second fixed potential plane provided between the first fixed potential plane and the second fixed potential plane, extending along the periphery of the wiring board, and With an electromagnetic wave barrier supplied with Wherein a. 18. The semiconductor device according to claim 17, wherein said electromagnetic wave barrier is constituted by a conductor formed in a plurality of via holes. 19. The semiconductor device according to claim 18, wherein an interval between the via holes is smaller than 1/100 of an electromagnetic wave wavelength. 20. A semiconductor device, further comprising a conductive film covering one main surface of the wiring substrate and another main surface facing the one main surface of the semiconductor chip. 21. A wiring board having a plurality of substrate electrodes on one main surface, and first and second semiconductor chips having a circuit and a plurality of chip electrodes on one main surface, wherein the one main surface is the wiring substrate Placed on the wiring board in a state facing one main surface,
And a first and a second semiconductor chip in which the plurality of chip electrodes are electrically connected to the plurality of substrate electrodes via connection means, respectively, wherein the first semiconductor chip, the second semiconductor chip, An electronic device, wherein an electromagnetic wave barrier to which a fixed potential is supplied is provided inside the wiring board between the two. 22. The electronic device according to claim 21, wherein the electromagnetic wave barrier is made of a conductor formed in a plurality of via holes. 23. The semiconductor device according to claim 22, wherein an interval between the via holes is smaller than one hundredth of an electromagnetic wave wavelength.