JP4862991B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a wafer level chip scale package type semiconductor device (WL-CSP).

The CSP is a semiconductor device that is equal to or slightly larger than the chip size. Of these, WL-CSP does not mount the chip face-up on a lead frame or the like and wire it from the chip electrode to the frame by wire bonding, but instead of wire bonding, it is wired within the chip. As shown, the silicon layer 12 can be mounted directly on the substrate 14 face down. Accordingly, the area occupied by the WL-CSP on the substrate 14 can be suppressed to the same level as that of the silicon layer 12, so that the WL-CSP greatly contributes to downsizing and high integration of electronic circuits.
The conventional WL-CSP generally has a structure in which the silicon layer is exposed as the back surface of the package. However, when an IC that flows a large current that drops from the back surface of the silicon to the GND is configured as the WL-CSP, In order to obtain a stable operation, it is desirable to cover the silicon layer exposed on the back surface of the package with the metal layer 16 and ground the metal layer 16 to the substrate 14 as in the WL-CSP 10 shown in FIG. However, since the WL-CSP 10 is mounted face down on the substrate, it is structurally impossible to ground the metal layer 16 on the back side of the package to the substrate.

  On the other hand, in the conventional face-down type semiconductor device, as a technology for grounding the metal layer formed on the back side of the package to the base, the periphery of the semiconductor chip is sealed with a polymer layer, and the polymer layer is outside with a conductive plate Has been invented (see Patent Document 1, for example).

Japanese Patent No. 2570499

However, when the method of sealing the semiconductor chip with a polymer layer, further covering with a conductive plate from the outside, and grounding its end to the substrate surface is applied to ground the back metal of the WL-CSP, The area occupied by the WL-CSP 10 on the substrate 14 is increased by the metal, and the advantages of the WL-CSP 10 are impaired. In addition to the WL-CSP 10 mounting process, the metal installation process is necessary, and the filling polymer layer injection process is necessary, so an increase in cost is inevitable.
The present invention has been made in view of the above problems, and its object is to cover the back surface of the package without impairing the advantage of WL-CSP that the occupied area on the substrate can be suppressed to the same level as the chip. An object of the present invention is to manufacture a semiconductor device capable of obtaining a stable operation by grounding a metal layer to a substrate.

In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention includes a wafer level chip scale package type in which a metal layer or wiring on the back surface of a package has a structure that is grounded to a substrate via wiring in the package. The method of manufacturing a semiconductor device according to claim 1, wherein a groove having a V-shaped cross section is formed from a silicon layer surface side of a semiconductor wafer on which a plurality of semiconductor chips are formed so that a bottom portion thereof is positioned on a dicing center line. A step of wiring to the bottom of the groove of the V-shaped cross section, a step of resin-sealing the silicon layer surface side, and forming a groove of the V-shaped cross section on the dicing center line from the back side of the silicon layer A ridge formed by exposing a wiring formed at the bottom of a groove having a V-shaped cross section provided on the surface side of the silicon layer, and chamfering from the front and back surfaces of the peripheral edge of the silicon layer. Forming a metal layer on the entire back side of the silicon layer, and conducting the wiring and the metal layer at a ridge line at the periphery of the silicon layer, along the dicing center line, And a step of dividing each semiconductor chip into individual pieces.

According to the present invention, on the dicing center line of the semiconductor wafer, the wiring formed at the bottom of the groove having the V-shaped cross section provided on the silicon layer surface side and the metal layer formed on the entire back surface side of the silicon layer are provided. It becomes a conductive state. Therefore, the semiconductor device that is divided into individual semiconductor chips along the dicing center line is in the form of a wafer level chip scale package, and the occupied area on the substrate is suppressed to the same level as the chip. In addition, the metal layer on the back surface of the package is grounded to the substrate via the wiring in the package. Moreover, since the grooves formed on the dicing center line from both the front and back sides of the silicon layer are V-shaped cross-section grooves, when forming the wiring and metal layer by sputtering or the like, on the bottom and inclined surfaces of each groove In addition, the conductive material constituting the wiring and the metal layer is securely adhered, and the wiring and the metal layer can be reliably formed without causing partial disconnection.
Further, by covering the back surface of the package with a metal layer, the chipping resistance of the semiconductor device is improved, and the handling of the semiconductor device is improved.

Further, in the present invention, a post may be formed at a predetermined position of the wiring following the process of wiring to the bottom of the groove having the V-shaped cross section.
In this case, when the semiconductor device is mounted on the substrate, the thermal fatigue to the solder can be distributed to the posts by way of the posts, and an improvement in mounting reliability can be expected.

In the present invention, the back side of the silicon layer can be resin-sealed after the step of forming the metal layer on the entire back side of the silicon layer.
According to the present invention, the chipping resistance of the semiconductor device can be further improved by resin-sealing the back surface side of the silicon, and the handling of the semiconductor device becomes better.

Moreover, in this invention, it may replace with the process of forming a metal layer in the whole surface of the said silicon layer back surface side, and may include the process of wiring on the silicon layer back surface side.
In this case, the wiring on the back side of the silicon layer and the wiring formed on the bottom of the groove having the V-shaped cross section provided on the front side of the silicon layer are in a conductive state. Therefore, the semiconductor device that is divided into individual semiconductor chips along the dicing center line is in the form of a wafer level chip scale package, and the occupied area on the substrate is suppressed to the same level as the chip. In addition, the wiring on the back surface of the package is grounded to the substrate via the wiring in the package.
In addition, when the wiring on the back surface of the package is resin-sealed, a plurality of semiconductor devices can be used in a stack structure.

Further, in the present invention, a post may be formed at a predetermined position of the wiring following the step of wiring on the back side of the silicon layer.
Even in such a case, when stacking the semiconductor device, the thermal fatigue to the solder can be dispersed to the post by passing through the post, and improvement in mounting reliability can be expected.

Since the present invention is configured as described above, the metal layer covering the back surface of the package is grounded to the substrate without impairing the advantage of WL-CSP that the occupied area on the substrate can be suppressed to the same level as the chip, and stable operation can be achieved. A semiconductor device that can be obtained can be manufactured .

The best mode for carrying out the present invention will be described below with reference to the accompanying drawings. Here, parts that are the same as or correspond to those in the prior art are denoted by the same reference numerals, and detailed description thereof is omitted.
The WL-CSP 18 according to the embodiment of the present invention includes a flip-chip product. As shown in FIG. 1, the peripheral portion of the silicon layer 12 has a front surface (a surface facing the substrate 14) and a back surface. By chamfering from both surfaces (the surface that does not face the substrate 14), a ridge line 12 a is formed at the peripheral edge of the silicon layer 12. Further, wiring 20 is applied to the surface side SF of the silicon layer 12, and the surface side is sealed with a resin 22. Furthermore, a metal layer 16 is formed on the back surface side BS of the silicon layer 12, and the wiring 20 on the front surface side and the metal layer 16 are electrically connected by a ridge line 12a at the peripheral edge. An aluminum pad 24 and a passivation film 26 are formed on the surface side of the silicon layer 12, and the protective layer 28 is covered except for a part of the aluminum pad 24, and wiring 20 is applied to the surface of the protective layer 28. Has been. A post 30 is formed at a predetermined position of the wiring. Furthermore, a solder terminal 32 is formed on the post 30, and the WL-CSP 18 is directly mounted on the wiring 14 a of the substrate 14 face down through the solder terminal 32.

Here, the manufacturing procedure of the WL-CSP 18 will be described with reference to FIGS.
First, as shown in FIG. 2, a groove 36 having a V-shaped cross section is formed from the silicon layer surface side SF of the semiconductor wafer 34 on which a plurality of semiconductor chips are formed, and its bottom portion 36a is positioned on the dicing center line DC. To be formed. As a method for forming the groove 36 having a V-shaped cross section, a blade dicing method using a blade having the same cross-sectional shape as the groove, a wet etching method, a dry etching method, or the like is used. In the example of FIG. 2, the cross-sectional shape of the groove 36 is symmetrical on both sides of the bottom portion 36 a, which is a plane parallel to the spreading direction of the semiconductor wafer 34, with inclined surfaces 36 b having a constant angle across the dicing center line DC. It is in a connected form.
Next, as shown in FIG. 3, the wiring 20 reaching the bottom of the groove having the V-shaped cross section is performed, and a post 30 is formed at a predetermined position of the wiring 20. Thereafter, the silicon layer surface side SF is sealed with the resin 22.

  Subsequently, as shown in FIG. 4, a groove 38 having a V-shaped cross section is formed on the dicing center line DC from the silicon layer back surface side BS, and a groove 36 having a V-shaped cross section provided on the silicon layer surface side SF is formed. The wiring 20 formed at the bottom of the substrate is exposed. Therefore, the bottom portion 38 a of the groove 38 having a V-shaped cross section provided from the back side BS of the silicon layer is constituted by the wiring 20. At this time, the silicon layer 12 is divided for each semiconductor device. The groove 38 having a V-shaped cross section can be formed by a technique such as a blade dicing method, a wet etching method, or a dry etching method. In the illustrated example, the cross-sectional shape of the groove 38 is the same as the V-shaped cross-sectional groove 36 provided on the silicon layer surface side SF, and the inclination angle of the inclined surface 38b having a constant angle is also V-shaped. Since it is the same as the inclined surface 36b of the groove 36 having a cross section, when the groove is formed by the blade dicing method, the blades forming the groove 36 and the groove 38 can be shared.

Subsequently, as shown in FIG. 5, the metal layer 16 is formed on the entire surface of the silicon layer back surface side BS. The metal layer 16 is also formed on the bottom 38a and the inclined surface 38b of the groove 38 having a V-shaped cross section provided from the back surface BS of the silicon layer 12, and the metal layer 16 is electrically connected to the wiring 20 on the dicing center line DC. It becomes a state. The metal layer is made of Al, Ti, Cu, Ni, Ag, Au, or the like, and is formed on the back surface side of the silicon layer 12 by a technique such as vapor deposition, sputtering, printing, or spin coating.
Finally, as shown in FIG. 6, solder terminals 32 are formed on the posts 30 and further separated into individual semiconductor chips along the dicing center line, as shown in FIG. 7A. WL-CSP 18 is completed. The WL-CSP 18 shown in FIG. 7A is a wiring / post-type WL-CSP. However, when the step of forming the post 30 on the wiring 20 is omitted in the step of FIG. As shown in FIG. 7B, a wiring-type WL-CSP in which solder terminals 32 are directly formed on the wiring 20 can also be used.

According to the embodiment of the present invention having the above-described configuration, the following operational effects can be obtained. First , according to the method for manufacturing a semiconductor device according to the present invention, the peripheral portion of the silicon layer 12 is chamfered from both the front and back surfaces to form a ridge line 12 a, the wiring 20 is applied to the silicon layer surface side SF, and the resin 22 is sealed. Has been. In addition, a metal layer 16 is formed on the back side BS of the silicon layer, and the wiring 20 and the metal layer 16 are electrically connected by a ridge line 12a at the peripheral edge of the silicon layer. That is, the semiconductor device according to the embodiment of the present invention is in the form of WL-CSP, and the metal layer 16 on the back surface BS of the package passes through the wiring 20 in the package as indicated by an arrow in FIG. Thus, the substrate 14 can be grounded. Further, since the package back surface BS is covered with the metal layer 16, the chipping resistance of the semiconductor device is improved and the handling is improved.
Further, since the post 30 is formed at a predetermined position of the wiring 20, thermal fatigue to the solder can be dispersed to the post 30, and improvement in mounting reliability can be expected.
Therefore, the WL-CSP 18 obtained by the method for manufacturing a semiconductor device according to the embodiment of the present invention has a backside of the package without losing the advantage of the WL-CSP that the occupied area on the substrate is suppressed to the same level as the chip. It is possible to obtain a stable operation by grounding the metal layer 16 covering the substrate to the substrate.

Further, according to the method for manufacturing a semiconductor device of the present invention, as shown in FIG. 5, the groove 36 having a V-shaped cross section provided on the silicon layer surface side SF on the dicing center line DC of the semiconductor wafer 34 is formed. The wiring 20 formed on the bottom 36a and the metal layer 16 formed on the entire surface of the silicon layer back surface BS become conductive. Therefore, the semiconductor device formed into individual semiconductor chips along the dicing center line DC by the semiconductor device manufacturing method according to the embodiment of the present invention has a WL-CSP mode, and the back surface of the package. The metal layer 16 is grounded to the substrate 14 via the wiring 20 in the package.
In the embodiment of the present invention, since the grooves formed on the dicing center line DC are the grooves 36 and 38 having a V-shaped cross section, when the wiring 20 and the metal layer 16 are formed by sputtering or the like, The conductive material constituting the wiring 20 and the metal layer 16 is in close contact with the bottoms 36a and 36b and the inclined surfaces 36b and 38b of each groove, and the wiring 20 and the metal layer 16 are surely secured without causing partial disconnection. Can be formed.

FIG. 8 shows an application example of WL-CSP obtained by the semiconductor device manufacturing method according to the embodiment of the present invention. The WL-CSP 40 in FIG. 8 is replaced with a step of forming the grooves 36 and 38 having a V-shaped cross section in FIGS. 2 and 5, and a silicon layer is previously formed inside the dicing line of the silicon layer 12 at the time of the semiconductor wafer. The conductive portion 42 is formed so as to penetrate the front surface side SF and the silicon layer back surface side BS. Therefore, the conductive portion 42 can ensure electrical connection between the metal layer 16 on the back surface of the package and the wiring 20 in the package.

Further, in the WL-CSP 44 according to the application example of FIG. 9, the silicon layer back surface side BS is sealed with the resin 46 after the step of forming the metal layer 16 on the entire surface of the silicon layer back surface side BS shown in FIG. It was obtained by adding the process to do. Therefore, the WL-CSP 44 can further improve the chipping resistance of the semiconductor device by resin-sealing the silicon back surface side BS, thereby improving the handling of the semiconductor device.

In addition, the WL-CSP 48 according to the application example of FIG. 10 replaces the step of forming the metal layer 16 on the entire surface of the silicon layer back surface BS shown in FIG. It is what I did.
In this case, the wiring 50 on the back side BS of the silicon layer and the wiring 20 on the front side of the silicon layer are in a conductive state. Therefore, the semiconductor device formed into individual semiconductor chips along the dicing center line has the form of WS-CSP, similar to the WS-CSP 18 shown in FIG. The substrate is grounded via the wiring 20 in the package. Further, by sealing the wiring 50 on the back surface of the package with the resin 46, it becomes possible to use a plurality of WL-CSPs 18 and 48 in a stack structure as shown in FIGS. Note that the stack structure of the plurality of WL-CSPs 18 and 48 can be stacked in multiple stages as necessary.
Furthermore, if the post 52 is also formed at a predetermined position of the wiring 50, when stacking a plurality of WL-CSPs, the wiring of the overlapping semiconductor devices is connected only to the solder terminals through the posts 30 and 52. Therefore, it is possible to ensure the conduction between the two more reliably than when grounding.

It is sectional drawing which shows the mounting state of WL-CSP manufactured by the manufacturing method which concerns on embodiment of this invention. It is explanatory drawing which shows the manufacturing process of WL-CSP shown by FIG. It is explanatory drawing which shows the manufacturing process following FIG. It is explanatory drawing which shows the manufacturing process following FIG. It is explanatory drawing which shows the manufacturing process following FIG. It is explanatory drawing which shows the manufacturing process following FIG. It is sectional drawing of WL-CSP apparatus manufactured with the manufacturing method which concerns on embodiment of this invention, (a) has shown wiring / post type, (b) has shown wiring type. It is sectional drawing which shows WL-CSP manufactured by the application example of the manufacturing method which concerns on embodiment of this invention. It is sectional drawing which shows WL-CSP manufactured by another application example of the manufacturing method which concerns on embodiment of this invention. It is sectional drawing which shows WL-CSP manufactured by the further another application example of the manufacturing method which concerns on embodiment of this invention. It is a schematic diagram which shows the state which stacked and mounted the WL-CSP of FIG.1 and FIG.10 on the board | substrate. It is a schematic diagram which shows the state which stacked WL-CSP of FIG. 10 in three steps, and was mounted in the board | substrate. It is sectional drawing of WL-CSP for demonstrating the problem of conventional WL-CSP.

  12: Silicon layer, 12a: Ridge line, 14: Substrate, 16: Metal layer, 18, 40, 44, 48: WL-CSP, 20, 50: Wiring, 22, 46: Resin, 30, 52: Post, 32: Solder terminal, 34: semiconductor wafer, 36, 38: groove with V-shaped cross section, 36a, 38a: bottom, 36b, 38b: inclined surface, BS: back side of silicon layer, DC: dicing center line, SF: surface of silicon layer ~ side

Claims (5)

A method of manufacturing a wafer level chip scale package type semiconductor device, wherein a metal layer or wiring on the back surface of a package has a structure in which the metal layer or wiring is grounded to a substrate via wiring in the package ,
Forming a groove having a V-shaped cross section from the silicon layer surface side of the semiconductor wafer on which a plurality of semiconductor chips are formed, so that the bottom thereof is positioned on the dicing center line;
Wiring to the bottom of the groove having the V-shaped cross section;
A step of resin-sealing the silicon layer surface side;
A groove having a V-shaped cross section is formed on the dicing center line from the back surface side of the silicon layer, and the wiring formed at the bottom of the groove having the V-shaped cross section provided on the surface side of the silicon layer is exposed. Forming a ridge line that is chamfered from both the front and back surfaces at the periphery; and
Forming a metal layer on the entire back surface of the silicon layer, and conducting the wiring and the metal layer at a ridgeline at the periphery of the silicon layer;
And a step of dividing the semiconductor chip into individual pieces along the dicing center line. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a post is formed at a predetermined position of the wiring following the step of wiring to the bottom of the groove having the V-shaped cross section. 3. The method of manufacturing a semiconductor device according to claim 1, wherein after the step of forming a metal layer on the entire back surface side of the silicon layer, the back surface side of the silicon layer is resin-sealed. 4. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of performing wiring on the back side of the silicon layer instead of the step of forming a metal layer on the entire back side of the silicon layer. Method. 5. The method of manufacturing a semiconductor device according to claim 4, wherein a post is formed at a predetermined position of the wiring following the step of wiring on the back side of the silicon layer.