JP2012146734A - Semiconductor device, manufacturing method of the same and packaged body - Google Patents

Abstract

PROBLEM TO BE SOLVED: To relax stress applied to a semiconductor substrate included in a semiconductor integrated circuit chip when the semiconductor integrated circuit chip is bonded to a packaging board with an encapsulation resin, thereby reducing variation in semiconductor element characteristics caused by stress and achieving efficient heat radiation during a circuit operation.SOLUTION: A semiconductor device includes a semiconductor circuit formation layer 2 formed on a surface of a semiconductor substrate 1, transistors formed in the semiconductor circuit formation layer 2 and included in a semiconductor circuit, and electrodes 5 formed on the semiconductor circuit formation layer 2 and electrically connected with the semiconductor circuit. Further, the semiconductor device comprises a recess 7 formed on a rear face side of the semiconductor substrate 1 and a metal film 6 formed on the rear face including the recess 7. For example, the electrodes 5 and pad electrodes 9 of a wiring board body 8 are thermal compression bonded and the semiconductor device is bonded to a wiring board with an encapsulation resin 10.

Description

  The present invention relates to a semiconductor device, in particular, a structure of a semiconductor device suitable for miniaturization and high-density mounting, and a method for manufacturing the semiconductor device.

  Recently, electronic products such as mobile phones have become smaller and lighter and more advanced, and the semiconductor integrated circuits mounted in such products can be packaged in a compact and high-density manner. Is strongly demanded. For example, a wafer level CSP (Chip Size Package) is one of the package forms that meet this demand. In this case, the size of the semiconductor chip obtained by cutting the wafer into individual pieces becomes the size of the package as it is, and the thickness can be made very thin. For this reason, the wafer level CSP is suitable for small and high density mounting on a printed circuit board.

  FIG. 10A is a cross-sectional view showing a structure in which a conventional wafer level CSP is mounted on a wiring board. In FIG. 10A, a semiconductor circuit forming layer 51 is formed on the surface of a semiconductor substrate 50 made of Si (GaAs or the like is also possible). Although the internal configuration of the semiconductor circuit formation layer 51 is not shown, transistors and wirings are provided separated by an interlayer insulating film. An electrode pad for inputting and outputting electric signals is formed on the uppermost layer of the wiring. The electrode pad is surrounded by a surface protective film including a polyimide resin layer, and its upper surface is exposed from the surface protective film.

  On the semiconductor circuit formation layer 51, a rewiring layer 52 is provided which is drawn from the electrode pad to the surface protective film. A metal post 53 made of Cu or the like is formed on the terminal forming portion of the rewiring layer 52, and a metal bump 55 made of solder or the like is joined to the top of the post as an external connection terminal. The periphery of the rewiring layer 52 and the metal post 53 and the upper surface of the semiconductor circuit forming layer 51 are covered with a sealing resin layer 54.

  The wafer level CSP has the above structure. On the other hand, a mounting substrate for mounting such a semiconductor integrated circuit has an electrode 57 on a wiring substrate 56. The metal bump 55 and the electrode 57 on the semiconductor integrated circuit device side of the CSP structure are thermocompression bonded to form an electrical connection, and a sealing resin 58 is injected between the semiconductor integrated circuit device and the wiring board 56, and both of them are injected. It is joined.

  The wafer level CSP package structure described above is described in Patent Document 1, for example.

JP 2005-158929 A

  A semiconductor device having a structure like a wafer level CSP is bonded to a wiring substrate 56 for normal mounting by a sealing resin 58 as shown in FIG. This sealing resin is generally called underfill and is required in most cases in order to reinforce the mechanical connection between the metal bump 55 and the electrode 57 on the wiring board side and enhance the reliability. However, the present inventors have found that this conventional structure has the following problems.

  First, the sealing resin 58 is thermally cured at a temperature of a few hundred degrees or more, but the semiconductor substrate 50 (here, the semiconductor wafer is cut into pieces by thermal contraction of the sealing resin at that time). The die or chip) receives a large stress from the sealing resin 58 side, and the stress remains even when the semiconductor substrate 50 returns to room temperature. FIG. 10B is a schematic diagram showing a stress distribution that the surface portion of the semiconductor substrate 50 receives from the sealing resin 58 side, for example. The X axis represents the distance from the center of the semiconductor substrate 50, and the Y axis represents the magnitude of stress. Although stress components act on the surface portion of the semiconductor substrate 50 in three directions along the orthogonal coordinate axes, only the stress component perpendicular to the surface of the semiconductor substrate 50 (Y-axis direction) is the main stress in FIG. 10B. The upward direction (arrow direction) is positive.

  As shown in FIG. 10B, the bonding stress of the sealing resin 58 acts in the direction of pulling up the semiconductor substrate 50 to the sealing resin side, and the magnitude of the stress is due to the material characteristics of the sealing resin 58. Have a distribution within. The stress is large in the central portion of the semiconductor substrate 50 and decreases monotonously toward the peripheral portion as the distance from the central portion increases. Such stress not only generates stress in the semiconductor substrate 50 but also causes variation in characteristics of the transistors constituting the semiconductor integrated circuit. Moreover, since the stress is distributed in the semiconductor substrate as shown in FIG. 10B, the characteristics of the transistor having the same structure vary greatly from the design value in the central portion of the semiconductor substrate 50, and the peripheral It has a distribution that the characteristic change becomes smaller toward the part.

  When the transistor characteristics are distributed on the semiconductor substrate 50 (chip) in this way, the individual transistors operate with different characteristics depending on the formation position on the semiconductor circuit, so that the characteristics of the entire semiconductor integrated circuit device are designed. It becomes the big factor which falls within the tolerance | permissible_range of a specification, and falls a manufacturing yield.

  Secondly, in the mounting form as shown in FIG. 10A, the semiconductor integrated circuit device is mounted on a bare chip with the back surface of the semiconductor substrate 50 exposed, so that it is easy to radiate heat to the outside, but still requires high speed operation. In a high-density fine semiconductor device having a very large number of elements such as a semiconductor device or a transistor, the heat dissipation efficiency of heat generated during operation becomes insufficient, and the temperature of the semiconductor substrate 50 rises and the circuit may malfunction. is expected.

  In view of the above problems, the present invention relaxes stress applied to a semiconductor substrate constituting a semiconductor device from the sealing resin when the semiconductor device is bonded to a mounting substrate using a sealing resin. Semiconductor device capable of reducing stress distribution in substrate and reducing variation in semiconductor element characteristics due to stress distribution, and semiconductor device capable of sufficiently dissipating heat to outside during circuit operation of semiconductor device, and The main object is to provide a method for manufacturing these semiconductor devices.

  A semiconductor device according to the present invention for solving the above problems comprises a semiconductor substrate, a semiconductor circuit forming layer formed on a surface of the semiconductor substrate, and a semiconductor circuit formed in the semiconductor circuit forming layer. A transistor formed on the semiconductor circuit formation layer and electrically connected to the semiconductor circuit, and a recess formed on the back side of the semiconductor substrate.

  In addition to the above configuration, this semiconductor device may have a metal film formed on the back surface of the semiconductor substrate, and the material of the metal film is specifically made of aluminum or aluminum nitride. Can do. In one embodiment of the semiconductor device, the recess is formed by removing a part of the semiconductor substrate. In another embodiment of the semiconductor device, the recess is formed in the metal film.

  Furthermore, it is desirable that the area of the concave portion per unit area on the semiconductor substrate is formed so as to have a distribution in the plane of the semiconductor substrate. Further, in many cases, it is particularly desirable that the area of the concave portion per unit area on the semiconductor substrate is formed so as to decrease from the central portion toward the peripheral portion of the semiconductor substrate.

  In still another embodiment of the semiconductor device according to the present invention, a plug made of a conductive material is formed while penetrating from at least the back surface to the front surface of the semiconductor substrate. When a metal film is formed on the back surface of the semiconductor substrate, the plug is preferably in contact with the metal film.

  Next, a manufacturing method of a semiconductor device according to the present invention for solving the above-described problems includes a step of forming a semiconductor circuit forming layer including a transistor constituting a semiconductor circuit on a surface of a semiconductor substrate, and the semiconductor circuit formation Forming an electrode electrically connected to the semiconductor circuit on the layer; and forming a recess on the back side of the semiconductor substrate.

  This manufacturing method may include a step of forming a metal film on the back surface of the semiconductor substrate. One method for forming the recess is to selectively remove the back surface of the semiconductor substrate. The recess can also be formed in the metal film. In that case, the back surface of the semiconductor substrate is polished, and the semiconductor substrate is thinned. After the thinning of the semiconductor substrate, the metal film is formed on the back surface of the semiconductor substrate. It is desirable to include a step of forming and a step of selectively removing the metal film to form a recess.

  When forming the plug in a semiconductor device, a step of selectively etching at least the semiconductor substrate from the back surface of the semiconductor substrate to form an opening penetrating from the back surface to the surface of the semiconductor substrate; And a step of embedding a conductive material.

  In the semiconductor device according to the present invention, the electrode included in the semiconductor device and a pad electrode formed on the wiring substrate are bonded, and a resin is filled between the semiconductor device and the wiring substrate. And a mounting body to which the wiring board is bonded. At that time, the semiconductor device according to the present invention is particularly effective for solving the above-described problems.

  As described above, the semiconductor device according to the present invention has a recess formed particularly on the back side of the semiconductor substrate. For example, when a semiconductor device is mounted on a wiring board, if a stress is applied to the semiconductor substrate from the resin used to join them, the semiconductor substrate is easily deformed according to the stress because there is a recess. Therefore, the stress is released and reduced.

  Further, the recess according to the present invention is formed such that the area per unit area on the semiconductor substrate has a distribution in the plane of the semiconductor substrate. Therefore, even if there is a distribution of stress from the outside, the distribution of the area of the recesses per unit area on the semiconductor substrate is adjusted according to the magnitude of the stress, and the stress is distributed over the surface of the semiconductor substrate. It can be reduced to be uniform. As described above, according to the present invention, it is possible to suppress a variation in characteristics of semiconductor elements such as a transistor due to an external stress and variations thereof and to prevent malfunction of the semiconductor device.

  Furthermore, the semiconductor device according to the present invention has a metal film on the back surface of the semiconductor substrate. This metal film quickly conducts heat generated in the semiconductor circuit and releases it to the outside. As a result, the temperature rise of the semiconductor device in operation is suppressed to prevent malfunction.

(A) is sectional drawing of the mounting body which joined the semiconductor device which concerns on this invention, and this semiconductor device to the wiring board, (b) is a figure which shows the distribution in the chip | tip of the stress applied to the semiconductor device which concerns on this invention, FIG. 6C is a diagram showing a distribution within a chip of a characteristic variation rate of a transistor formed in a semiconductor device according to the present invention. The figure which shows the cutting line of the chip | tip corresponding to the cross section of Fig.1 (a). The figure which shows the groove-shaped recessed part pattern formed in the semiconductor substrate back surface of the semiconductor device which concerns on this invention. The figure which shows the groove-shaped recessed part pattern formed in the semiconductor substrate back surface of the semiconductor device which concerns on this invention. The figure which shows the groove-shaped recessed part pattern formed in the semiconductor substrate back surface of the semiconductor device which concerns on this invention. The figure which shows the recessed part pattern formed in the semiconductor substrate back surface of the semiconductor device which concerns on this invention. FIG. 10 is a view showing a modification of the cross-sectional structure of the semiconductor device according to the present invention. Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on this invention. The figure which shows the cross-sectional shape of the recessed part formed in the semiconductor substrate back surface of the semiconductor device which concerns on this invention. (A) is sectional drawing when the semiconductor device which has the conventional structure is mounted in a wiring board, (b) is a figure which shows the distribution in a chip | tip of the stress applied to the conventional semiconductor device.

  Hereinafter, the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1A is a cross-sectional view showing a mounting body formed by bonding a semiconductor device according to the present invention to a wiring board. In FIG. 1A, a semiconductor circuit forming layer 2 in which a predetermined semiconductor circuit is formed is provided on the surface of a semiconductor substrate 1 such as a silicon single crystal substrate. Although the internal structure of the semiconductor circuit formation layer 2 is not shown in FIG. 1A, a plurality of semiconductor active elements such as transistors are formed from the lowermost layer of the semiconductor circuit formation layer 2 to the surface portion of the semiconductor substrate 1. . A capacitor element and a resistor element are provided on the upper layer of the transistor as necessary. At the same time, a multilayer wiring structure composed of a metal wiring and an interlayer insulating film is formed above these elements.

  A bonding pad 3 for performing signal input / output with the outside of the semiconductor device is formed on the semiconductor circuit formation layer 2 and is electrically connected to the multilayer wiring, for example, the uppermost metal wiring constituting the semiconductor circuit. Yes. In FIG. 1A, only two bonding pads 3 on the semiconductor substrate 1 are shown. This assumes a semiconductor device in which a plurality of bonding pads 3 are arranged along the peripheral portion on the plane of the semiconductor substrate 1 as shown in FIG. 2, and FIG. It is for showing. The bonding pad 3 is usually made of an Al alloy film. The upper surface of the semiconductor circuit layer 2 is covered with a thick protective film 4 mainly composed of a silicon nitride film formed by, for example, plasma CVD, and the upper surface of the bonding pad 3 is exposed through an opening.

  On the bonding pad 3, a bump 5 having a protruding shape made of, for example, Sn—Ag solder is formed and electrically connected to the bonding pad 3. The material of the bump 5 can be Au, Cu, or the like formed by plating in addition to solder. Furthermore, in the semiconductor device according to the present embodiment, a groove-shaped recess 7 is formed at a predetermined position on the back surface of the semiconductor substrate 1 and a metal film 6 made of aluminum (Al) or aluminum nitride (AlN) is formed. . The thickness of the metal film 6 is set so thin that the inside of the recess 7 is not completely filled and the surface of the metal film 6 has a shape reflecting the cross-sectional shape of the recess 7.

  The above-described portion is the configuration of the semiconductor device according to the present invention, and the semiconductor device shown in FIG. 1A is in a state of one chip (or die) obtained by dividing a wafer into pieces in a dicing process.

  A main component of a wiring board for mounting such a semiconductor device is a wiring board body 8, on which a pad electrode 9 and a copper wiring (not shown) connected to the pad electrode 9 are formed. . Particularly when a large-scale integrated circuit having a large number of semiconductor elements is mounted, a multilayer wiring is also formed inside the wiring board main body 8 (not shown). For example, as shown in FIG. The protruding electrode 11 is provided on the surface opposite to the pad electrode 9. The wiring board is not limited to mounting only one semiconductor device as shown in FIG. 1 (a), and may be mounted with a plurality of semiconductor devices incorporated in packages of different forms.

  Each of the pad electrodes 9 is provided at a position facing the bump 5 of the semiconductor device, and the corresponding two are electrically joined by thermocompression bonding at a temperature of hundreds of degrees or more. Further, a sealing resin (underfill) 10 is filled and bonded between the semiconductor device (semiconductor chip) and the wiring board main body 8 to strengthen the bump connection. As a material for the sealing resin 10, for example, a mixture of a normal epoxy resin, a silicon oxide filler, a coupling agent, a colorant, and the like can be used, and the resin is thermally cured at a temperature of hundreds of degrees or more after filling.

  FIG. 1B is a diagram showing an intra-chip stress distribution applied to the semiconductor substrate 1 in the mounting body (FIG. 1A) according to the present invention. The X axis in the figure indicates the distance from the origin with the center of the semiconductor substrate 1 as the origin, and the Y axis indicates the stress component perpendicular to the surface of the semiconductor substrate 1. The arrow indicates the direction of stress, and the upper direction, that is, the direction from the semiconductor substrate 1 toward the sealing resin 10 is positive. The stress indicated by time 1 (b) is the stress at the surface portion of the semiconductor substrate 1 where the transistor is formed, the level on the line AA ′ of FIG. 1 (a), and the semiconductor substrate region inside the position of the bump 5 The stress in is shown.

  As shown in FIG. 1B, the stress in the direction of the sealing resin 10 is large at the central portion of the semiconductor substrate 1 as in the case of the conventional semiconductor device, and works to decrease from the central portion toward the peripheral portion. (See, for example, FIGS. 10A and 10B). However, the absolute value of the magnitude is considerably reduced as compared with the case of the conventional semiconductor device. Therefore, the stress difference between the central portion and the peripheral portion is also reduced, and the stress distribution is almost uniform. This result is considered to be based on the following reasons.

  After the sealing resin is filled between the semiconductor device and the wiring board, for example, when the resin is heated to a high temperature in order to cure it, the sealing resin contracts, so that a large stress is applied to the surface of the semiconductor substrate in the direction of the sealing resin. Arise. This occurs because the shrinking sealing resin tries to maintain the initial shape so that the semiconductor substrate does not deform itself against the force of pulling up the semiconductor substrate in the direction of the sealing resin. However, in the semiconductor device according to the present invention, since the concave portion is provided on the back surface of the semiconductor substrate, the apparent elastic modulus is reduced although the intrinsic elastic modulus of the semiconductor substrate constituent material (for example, silicon single crystal) is unchanged. When the apparent elastic modulus of the substrate is small, the semiconductor substrate can be easily deformed following the shrinkage deformation of the sealing resin, and the shrinkage stress is released.

  In the present invention, not only the recesses are formed on the back surface of the semiconductor substrate, but also the density of the recesses 7 is increased at the central portion of the semiconductor substrate 1 and decreased at the peripheral portion as shown as an example in FIG. To do. A region having a high density of recesses in the semiconductor substrate has a small apparent elastic modulus and can be easily deformed, and a region having a low density has a large apparent elastic modulus and is difficult to deform. Therefore, if the recesses are arranged at a higher density in a region where the greater stress is to be generated (the central portion of the semiconductor substrate) to increase the degree of stress relaxation, the stress distribution in the semiconductor substrate can be made uniform.

Making the stress distribution applied to the semiconductor substrate uniform improves the uniformity of the distribution in the semiconductor substrate (chip) of the transistor characteristics constituting the semiconductor circuit. FIG. 1C shows the distribution in the semiconductor substrate of the transistor characteristic variation rate (variation value from characteristic reference value / characteristic reference value: unit%) due to stress in the transistor included in the semiconductor device shown in FIG. FIG. The horizontal axis indicates the distance from the center of the semiconductor substrate 1, and the vertical axis indicates the transistor characteristic variation rate, which is the variation rate corresponding to the stress component perpendicular to the surface of the semiconductor substrate. Further, FIG. 1C is a diagram in the case where the semiconductor circuit is composed of a plurality of MOS transistors, and examples of transistor characteristics include carrier channel mobility, drain current, and mutual conductance g _m . FIG. 1C shows a characteristic variation rate distribution (curve a: P channel type, curve b: N channel type) for a semiconductor device according to the present invention and a characteristic variation rate distribution (curve c: P channel type) for a conventional semiconductor device. , Curve d: N channel type).

  Corresponding to the relaxation of the stress applied to the semiconductor device according to the present invention, the characteristic variation rate of the transistor is smaller than that of the conventional semiconductor device, and the uniformity of the distribution is further improved. Therefore, the transistor characteristics vary depending on the position in the semiconductor circuit that occupies almost the entire surface of the semiconductor substrate (chip), preventing the occurrence of defects in which the characteristics of the semiconductor integrated circuit as a whole do not meet the design specification values, and the manufacturing yield is increased. improves. In the P channel type and the N channel type, the direction of variation with respect to the same stress is opposite. In addition, the P-channel type has a smaller characteristic variation rate than the N-channel type. This is considered because the P-channel type transistor is more sensitive to stress parallel to the surface of the semiconductor substrate than to normal stress.

  As shown in FIG. 1A, the semiconductor device according to the present invention includes a metal film 6 together with a recess 7 on the back surface of the semiconductor substrate 1. Since the metal film 6 has a higher thermal conductivity than the semiconductor substrate 1, heat generated during operation of the semiconductor device can be efficiently released to the outside. In particular, the formation of the recess 7 increases the surface area of the metal film 6 and improves the heat dissipation efficiency as compared with the conventional semiconductor device. Therefore, the malfunction of the semiconductor circuit due to the temperature rise can be suppressed.

  The recesses on the back surface of the semiconductor substrate 1 can be formed in various distribution patterns on a plane according to the distribution of the magnitude of stress applied to the semiconductor substrate 1. 3 to 7 are diagrams showing a planar pattern of the recesses formed on the back surface of the semiconductor substrate 1 (chip), and are examples in which the stress is large in the central portion of the semiconductor substrate 1 and small in the peripheral portion. The semiconductor substrate 1 in these drawings shows the shape of the entire chip and is substantially square.

  First, the recesses 21 shown in FIG. 3A are linear grooves extending in parallel with one side of the chip with a narrower pitch at the center of the back surface of the semiconductor substrate 1 and a wider pitch at the peripheral part. The recess can relieve stress distribution in a direction that intersects at least the direction in which the recess 21 extends, for example, a direction perpendicular to the direction of the recess 21. In the recess 22 shown in FIG. 3 (b), a plurality of linear grooves extending from one end to the other end of the chip are formed in parallel with each other at a narrower pitch at the center of the chip and at a wider pitch at the peripheral part. Linear grooves are formed in two different directions and have a pattern that intersects (in the figure, orthogonal to each other).

  The recesses 23 shown in FIG. 4A are formed of linear grooves formed with a narrower pitch at the center of the back side of the chip and a wider pitch at the peripheral part. Further, the linear groove forms a plurality of similar rectangles, and a large number of small-sized rectangles are arranged in the center portion of the chip, and a smaller number of large-sized rectangles are arranged in the peripheral portion than the central portion. The recess 24 shown in FIG. 4B has a pattern obtained by rotating the pattern of the recess 23 shown in FIG.

  The recess 25 shown in FIG. 5A is a linear groove. Specifically, a minimum rectangle formed by the groove-like recess is arranged at the center of the back surface of the chip 1 and surrounds the rectangle toward the outside. Thus, a larger rectangle has a pattern formed concentrically and sequentially. In general, a plurality of rectangular patterns may be drawn in a concave portion formed of a groove, and a large rectangle may be a pattern surrounding a smaller rectangle. The pattern formed by the grooves may be not only a rectangle but also a polygon. The concave portion 26 shown in FIG. 5B is also a linear groove, and has a pattern in which a plurality of circles composed of grooves are arranged concentrically. In the case of FIG. 5B, the center of the smallest circle is arranged so as to coincide with the center of the chip.

  When the groove pattern is formed on the back surface of the semiconductor substrate 1 as shown in FIG. 3A to FIG. 5B, the groove width is specifically set to 10 μm to 100 μm, and the groove depth is set to the depth of the semiconductor substrate 1. The thickness is preferably about 1/30 to 1/3 of the thickness (10 μm to 100 μm if the thickness of the semiconductor substrate 1 is about 300 μm).

  On the back surface of the semiconductor substrate 1 shown in FIG. 6 (a), a plurality of polygonal (octagonal) island-like regions made of the semiconductor substrate 1 itself are formed which are smaller in the center portion of the chip and larger in the peripheral portion. Then, a recess 27 is formed between the island regions. The pattern including the concave portion 28 shown in FIG. 6B is obtained by making the polygon in FIG. 6A into a circle.

  By forming the pattern formed on the back surface of the semiconductor substrate 1 into the patterns shown in FIGS. 3B and 4A to 6B, the area of each concave portion per unit area on the semiconductor substrate 1 ( Or, the area ratio of each recess on the semiconductor substrate 1 is large at the center of the chip and small in any direction toward the periphery. The groove-like recesses such as the recesses 7 in FIG. 1 have been described as “the density of the recesses”, but this is the area of the recesses per unit area on the semiconductor substrate, or Is equivalent to the occupied area ratio. When the stress applied to the semiconductor substrate 1 is centrosymmetric on the semiconductor substrate 1, the concave portions having the patterns shown in the above drawings effectively work to alleviate the stress over the entire chip. The recesses are preferably formed in a pattern that is rotationally symmetric with respect to rotation at a predetermined angle around an axis that passes through this center and is perpendicular to the plane of the chip, with the intersection of the diagonal lines of the semiconductor substrate 1 as the center of the chip. The patterns shown in FIGS. 3B and 4A to 6B are to be rotated by 90 °. When the stress applied to the semiconductor substrate 1 is large in the band-shaped region passing through the center portion of the chip and parallel to the mutually orthogonal sides of the chip, the recess 22 in FIG. When it is large in the band-shaped region including the diagonal line, the stress can be relieved particularly effectively by adopting the concave portion 24 of FIG.

  FIG. 1A shows an example of a semiconductor device according to the present invention, but various other modifications are possible. FIG. 7A is a cross-sectional view showing a first modification of the semiconductor device according to the present invention. This semiconductor device is obtained by forming a plug 30 made of a conductive material in the periphery of the semiconductor substrate 1 (chip) in the semiconductor device described in FIG. The plug 30 is provided so as to penetrate from the upper surface of the semiconductor circuit forming layer 2 to the back surface of the semiconductor substrate 1 and to contact the metal film 6. By providing the plug 30 having such a structure, a part of heat generated from the multilayer wiring layer provided in the semiconductor circuit forming layer 2 or the MOS transistor provided on the surface portion of the semiconductor substrate 1 is thermally conductive. Can be absorbed by the high plug 30 and promptly led to the metal film 6 for heat dissipation.

  The plug 30 in FIG. 7A is formed from the upper surface of the semiconductor circuit formation layer 2, but it is sufficient that it is formed at least from the front surface to the back surface of the semiconductor substrate 1. Further, the planar shape of the plug 30 may be a circle, a rectangle, a band, or a ring around the periphery of the chip. As the conductive material, tungsten, copper, or the like can be used.

  FIG. 7B is a cross-sectional view showing a second modification of the semiconductor device according to the present invention. In this semiconductor device, a metal film 31 thicker than the metal film 6 shown in FIG. 1A is provided on the back surface of the semiconductor substrate 1. On the other hand, the thickness of the mounting body is taken into consideration, for example. Therefore, the thickness of the semiconductor substrate 1 is made thinner than that shown in FIG. Then, the recesses 32 are formed on the surface of the metal film 31 with a density distribution or an area distribution corresponding to the distribution of the magnitude of stress applied to the semiconductor substrate 1 when the semiconductor device is bonded to the wiring board. In the semiconductor device having such a structure, the apparent elastic modulus of the composite substrate of the semiconductor substrate 1 and the metal film 31 can be reduced by the recess 32, and therefore, similar to the semiconductor device shown in FIG. A stress relaxation effect is obtained. Further, since the metal film 31 is thick, there is an advantage that the heat dissipation efficiency is further improved.

(Embodiment 2)
FIG. 8 is a process cross-sectional view illustrating the semiconductor device manufacturing method according to the second embodiment of the present invention. The semiconductor device that is the object of the manufacturing process of FIG. 8 is the semiconductor device shown in FIG. First, as shown in FIG. 8A, a semiconductor circuit formation layer 2 is formed on a semiconductor substrate 1 such as a silicon single crystal substrate by using a diffusion process including normal fine processing. A semiconductor substrate 1 shown in FIG. 8 is a substrate in a wafer state, unlike FIG. As described in the first embodiment, a plurality of semiconductor active elements such as transistors are formed from the lowermost layer of the semiconductor circuit formation layer 2 to the surface portion of the semiconductor substrate 1. A capacitor element and a resistor element are provided on the upper layer of the transistor as necessary. At the same time, a multilayer wiring structure composed of each metal wiring and an interlayer insulating film is formed.

  Next, a bonding pad 3 made of, for example, an Al alloy film is formed on the semiconductor circuit formation layer 2 and electrically connected to the multilayer wiring, for example, the uppermost metal wiring. Thereafter, a thick protective film 4 mainly composed of a silicon nitride film is deposited on the bonding pad 3 and the semiconductor circuit layer 2 by, for example, plasma CVD, and an opening is formed on the upper surface of the bonding pad 3 to expose the surface of the bonding pad 3. Let

  Next, as shown in FIG. 8B, bumps 5 made of, for example, Sn-Ag solder are formed on the bonding pads 3 in order to input / output electric signals to / from the outside. The bump 5 can be an Au bump or a Cu bump in addition to the solder. In the case of using Au or Cu, a resist pattern having an opening is formed on the bonding pad 3, and Au or Cu is selectively deposited in the opening using an electrolytic plating method.

  Thereafter, as shown in FIG. 8C, an adhesive layer 41 is applied to the surface on which the bumps 5 and the protective film 4 are formed, and a support substrate 40 of at least the same size as the semiconductor substrate 1 is pasted via the adhesive layer 41. Align and fix. The support substrate 40 is preferably made of a hard material so that it can withstand mechanical impacts in subsequent processing steps. However, a flexible organic resin tape or the like may be used as the support for the semiconductor substrate 1. Next, the semiconductor substrate 1 is turned upside down so that the back surface of the semiconductor substrate 1 faces upward, and the back surface of the semiconductor substrate 1 is polished and thinned as necessary. This is necessary when the semiconductor device of the form incorporated in the package is mounted on the surface of the wiring board to reduce the mounting volume and reduce the size.

  Next, as shown in FIG. 8D, a resist film having a predetermined opening pattern (not shown) is formed on the back surface. Thereafter, the semiconductor substrate 1 is selectively etched and removed using the resist film pattern as a mask to form a recess 7. For this etching, chemical chemical wet etching or plasma etching is used. Alternatively, when the concave portion is a combination of simple linear patterns as shown in FIGS. 3A and 3B, it is formed by grinding and removing the back surface of the semiconductor substrate 1 using a dicing wheel. You can also.

  The recess 7 is processed into various cross-sectional shapes depending on the purpose. FIG. 9 is a diagram specifically illustrating the cross-sectional shape of the recess. The recess 7a in FIG. 9A has a rectangular cross section, and the apparent elastic modulus of the semiconductor substrate 1 can be greatly reduced, so that it is effective for greatly relieving stress. The recess 7a is formed by anisotropic plasma etching using the resist film 42 formed on the back surface of the semiconductor substrate 1 as a mask. The concave portion 7b in FIG. 9B has a V-shaped cross section, and is effective when it is not necessary to relieve stress so much. Although the recess 7b also depends on the back crystal plane orientation of the semiconductor substrate 1, when the plane orientation is (100), the recess 7b can be easily formed by anisotropic wet etching using the resist film 42 as a mask. The recess 7c in FIG. 9C has a U-shaped cross section, and is effective when stress relaxation about the middle between the recesses 7a and 7b is required. The recess 7c can be formed by isotropic wet etching or isotropic plasma etching using the resist film 42 as a mask.

  FIG. 9 shows a case where a recess is formed in the semiconductor substrate 1, but the cross-sectional shape of the recess 32 formed in the metal film 31 is rectangular, V-shaped, or U-shaped as in the semiconductor device of FIG. It goes without saying that the same effect can be obtained even if it is adopted.

  After forming the recess 7, a metal film 6 such as an alloy film mainly composed of Al or an AlN film is deposited on the back surface of the semiconductor substrate 1 by a sputtering method or the like. The deposited film thickness is set so thin that the shape of the recess 7 is transferred to the surface shape of the metal film 6. In some cases, it is desirable to adjust the temperature of the semiconductor substrate 1 in sputtering, the deposition rate of the film, the Ar gas pressure, etc. in order to reduce the influence of the stress exerted on the surface portion of the semiconductor substrate 1 by the metal film 6. After the metal film 6 is deposited, heat treatment is performed at several hundred degrees or less as necessary.

  Although the subsequent manufacturing steps are not shown, after the metal film 6 is deposited, the semiconductor device in the wafer state is diced together with the support substrate 40 while the support substrate 40 is mounted, and is separated into individual chips. . Next, the adhesive layer 41 is dissolved to separate the support substrate 40, thereby completing the semiconductor device. Further, as shown in FIG. 1A, the bump 5 of the semiconductor device in a chip state and the corresponding pad electrode 9 of the wiring board are thermocompression-bonded, and then sealed between the semiconductor device and the wiring board body 8. The resin 10 is injected in a liquid state and thermally cured to ensure the bonding between the semiconductor device and the wiring board.

  For joining the wiring board and the semiconductor device, first, a sheet-like sealing resin is attached to the entire surface of the wiring board body 8 including the pad electrode 9, and then the bump 5 and the pad electrode 9 of the semiconductor device are thermocompression bonded. You may carry out by the method of melt | dissolving and thermosetting sealing resin.

  The manufacturing method of the present embodiment has been described with reference to the semiconductor device of FIG. However, when manufacturing the semiconductor device of FIG. 7A, for example, after the process of FIG. 8C is completed, a resist film having an opening pattern corresponding to the plug 30 is formed on the back surface of the semiconductor substrate 1, and the resist film is formed. The semiconductor substrate 1 and the semiconductor circuit layer 2 are sequentially and selectively etched from the back surface of the semiconductor substrate 1 as a mask, and an opening penetrating both is formed. Thereafter, the resist film is removed, a conductive material such as W or Cu is embedded in the formed opening, and then the step of FIG.

  When the semiconductor device of FIG. 7B is manufactured, for example, in the step of FIG. 8C, the back surface of the semiconductor substrate 1 is polished to thin the semiconductor substrate 1, and then a relatively thick metal film 31 is deposited. . Subsequently, a groove-like recess 32 may be formed on the surface of the metal film 31 with a dicing wheel, or the recess 32 may be formed by a photolithography process and selective etching.

  In the first and second embodiments, a semiconductor device having an inorganic material protective film 4 mainly composed of a silicon nitride film and a bump formed in an opening of the protective film 4 is directly bonded to a wiring substrate (mounting substrate). An example to do. However, the present invention can also be applied to a semiconductor device having a wafer level CSP structure in which the surface protective film is covered with a sealing resin layer as shown in FIG. In addition to silicon, GaAs may be used as the semiconductor substrate material.

  The present invention is suitable for bonding a semiconductor integrated circuit chip itself from which the semiconductor substrate is exposed or a semiconductor integrated circuit in the form of a small package in which the semiconductor substrate is partially exposed to a mounting substrate via a sealing resin. Further, a MOS type transistor whose gate length is 65 nm or less and whose characteristics are easily affected by stress, a MOS type transistor whose characteristics are controlled by positively applying stress to the channel region, and a high dielectric constant of the Hf oxide film system The present invention is useful when applied to a semiconductor integrated circuit including a MOS transistor having a gate insulating film, and a semiconductor integrated circuit using a mechanically fragile low dielectric constant porous insulating film as an interlayer insulating film for multilayer wiring.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Semiconductor circuit formation layer 3 Bonding pad 4 Protective film 5 Bump 6, 31 Metal film 7, 7a, 7b, 7c, 21, 22, 23, 24, 25, 26, 27, 28, 32 Recessed part 8 Wiring board Main body 9 Pad electrode 10 Sealing resin 11 Protruding electrode 30 Plug 40 Support substrate 41 Adhesive layer 42 Resist film

Claims (15)

A semiconductor substrate;
A semiconductor circuit forming layer formed on the surface of the semiconductor substrate;
A transistor that is formed in the semiconductor circuit formation layer and forms a semiconductor circuit;
An electrode formed on the semiconductor circuit formation layer and electrically connected to the semiconductor circuit;
A semiconductor device comprising: a recess formed on the back side of the semiconductor substrate.   The semiconductor device according to claim 1, wherein a metal film is formed on a back surface of the semiconductor substrate.   The semiconductor device according to claim 1, wherein the recess is formed by removing a part of the semiconductor substrate.   The semiconductor device according to claim 2, wherein the recess is formed in the metal film.   5. The semiconductor device according to claim 1, wherein an area of the concave portion per unit area on the semiconductor substrate is set to have a distribution in a plane of the semiconductor substrate. .   The semiconductor device according to claim 5, wherein an area of the concave portion per unit area on the semiconductor substrate is set so as to decrease from a central portion to a peripheral portion of the semiconductor substrate.   2. The semiconductor device according to claim 1, wherein a plug made of a conductive material is formed while penetrating at least from the back surface to the front surface of the semiconductor substrate.   3. The semiconductor device according to claim 2, wherein a plug made of a conductive material is formed while penetrating at least from the back surface to the front surface of the semiconductor substrate, and the plug is in contact with the metal film.   9. The semiconductor device according to claim 2, wherein the metal film is made of aluminum or aluminum nitride. Forming a semiconductor circuit forming layer including a transistor constituting the semiconductor circuit on the surface of the semiconductor substrate;
Forming an electrode electrically connected to the semiconductor circuit on the semiconductor circuit formation layer;
And a step of forming a recess on the back surface side of the semiconductor substrate.   The method for manufacturing a semiconductor device according to claim 10, further comprising a step of forming a metal film on a back surface of the semiconductor substrate.   12. The step of forming a recess on the back surface side of the semiconductor substrate is a step of selectively removing the back surface portion of the semiconductor substrate to form a recess. Production method.   Polishing the back surface of the semiconductor substrate and thinning the semiconductor substrate; and after thinning the semiconductor substrate, further comprising forming a metal film on the back surface of the semiconductor substrate, The method for manufacturing a semiconductor device according to claim 10, wherein the step of forming a recess on the back surface side is a step of selectively removing the metal film to form a recess.   Selectively etching at least the semiconductor substrate from the back surface of the semiconductor substrate to form an opening penetrating from the back surface to the front surface of the semiconductor substrate; and forming a plug by embedding a conductive material in the opening. The method of manufacturing a semiconductor device according to claim 10, further comprising:   The electrode included in the semiconductor device according to claim 1 and a pad electrode formed on the wiring substrate are bonded, and a resin is filled between the semiconductor device and the wiring substrate. The mounting body, wherein the semiconductor device and the wiring board are joined.

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