JP2007005485A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly precise and reliable semiconductor device with no risk of short-circuiting or disconnection, and to improve the reliability of the semiconductor device especially when taking out it to the outside from the side face. <P>SOLUTION: The semiconductor device is formed with interlayer insulating films and a wiring layer on the semiconductor substrate surface in which an element region is formed. Among the interlayer insulating films, an interlayer insulating film containing impurities is removed which abuts on the wiring layer at least at the edge of the semiconductor substrate. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a chip peripheral portion wiring structure effective for a chip size package (CSP) type solid-state imaging device.

  Solid-state imaging devices including a CCD (Charge Coupled Device) are increasingly required to be miniaturized due to the necessity of application to mobile phones and digital cameras. As one of them, a CSP type solid-state imaging device in which a microlens is provided in a light receiving area of a semiconductor chip has been proposed. (Patent Document 1).

According to the CSP type solid-state imaging device, the mounting area can be reduced, and optical components such as a filter, a lens, and a prism can be bonded to the surface of the hermetic sealing portion. It is possible to reduce the mounting size without reducing the light collecting ability.
However, when mounting such a solid-state imaging device, it is necessary to mount the signal on the support substrate on which the solid-state imaging device is mounted, to make electrical connection and to perform sealing by a method such as bonding, when taking out the signal to the outside. Since there are many man-hours, there is a problem that a lot of time is required for mounting.

JP-A-7-202152

  Therefore, in recent years, a method has been proposed in which dicing is performed so as to include the wiring region of the semiconductor substrate, and external extraction is performed from the side surface of the substrate. An example of this is shown in FIGS. 10 (a) and 10 (b). As is apparent from this figure, a wiring layer 11 made of an aluminum layer is formed on a BPSG film 10 as a planarizing film, and an upper layer thereof is covered with a protective film 8 to form a wiring structure. When the semiconductor substrate is divided by DL, the BPSG film 10 is exposed. At this time, since the BPSG film contains impurities such as boron B and phosphorus P, it easily takes in moisture, becomes an acid due to reaction with this moisture, becomes easy to conduct, and there is a risk of short circuit. Further, when an easily oxidized material such as aluminum is used for the wiring, it is likely to cause disconnection.

  Furthermore, although a color filter is formed in the upper layer, there is a problem that uneven coating due to a step is likely to occur if the peripheral edge is high at this time.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a highly accurate and highly reliable semiconductor device without fear of a short circuit or disconnection.
In particular, the object is to improve the reliability of the semiconductor device when performing external extraction from the side.

  Accordingly, in the present invention, there is provided a semiconductor device including an interlayer insulating film and a wiring layer for external extraction on the surface of a semiconductor substrate on which an element region is formed, and the semiconductor substrate edge portion of the interlayer insulating film. The interlayer insulating film containing impurities at least in contact with the wiring layer is removed.

  With this configuration, an interlayer insulating film containing impurities such as a BPSG (boro phospho silicate glass) film is not exposed in the cross section, so that even if it is exposed to air, moisture in the air is taken in and wiring is not short-circuited. Further, the deterioration of the wiring can be prevented, and the bonding failure can be suppressed.

  According to the present invention, in the above semiconductor device, the interlayer insulating film containing the impurity is a BPSG film or a PSG film.

  According to the present invention, the semiconductor device includes a stopper insulating film having an etching selectivity with respect to the interlayer insulating film below the interlayer insulating film.

  With this configuration, since the stopper insulating film is provided, the insulation with the lower layer is good, and the field oxide film can be formed without etching, so that the reliability can be improved.

  In the present invention, the semiconductor device includes one in which the stopper insulating film is silicon nitride.

  With this configuration, the insulating property is good, and the portion without the flattening film is composed of a laminated film of silicon nitride and silicon oxide of the field oxide film, so that the insulating property and moisture resistance are also good.

  According to the present invention, the semiconductor device includes the semiconductor device from which the impurity-containing interlayer insulating film is removed over the entire periphery of the semiconductor substrate.

  With this configuration, the step at the peripheral edge can be reduced, so that uneven application can be prevented when the filter material is applied when forming the color filter.

  According to the present invention, in the semiconductor device, the wiring layer is exposed to a peripheral portion of the semiconductor substrate and externally connected via a wiring lead formed on a side surface of the semiconductor substrate.

  With this configuration, it is possible to efficiently shorten the wiring length, to reduce the wiring resistance, and to provide a semiconductor device with good characteristics.

  According to the present invention, in the semiconductor device, the wiring layer includes a metal layer.

  In the present invention, the semiconductor device includes one in which the metal layer is aluminum or an aluminum alloy.

  When exposed in the air together with impurity ions, there is a problem that aluminum is easily oxidized and easily broken, but this configuration can improve reliability.

  In the present invention, the semiconductor device includes a semiconductor device that is a solid-state image sensor and constitutes a chip size package.

  With this configuration, the size can be further reduced.

  The method of the present invention is a method for manufacturing a semiconductor device comprising an interlayer insulating film and a wiring layer for external extraction on the surface of a semiconductor substrate on which an element region is formed, and at least the wiring among the interlayer insulating films The method includes a step of selectively removing an interlayer insulating film containing an impurity in contact with a layer at an end portion of the semiconductor substrate.

  By this method, a wiring structure in which an interlayer insulating film containing impurities such as a BPSG (borophosphosilicate glass) film is not exposed to a chip or a cross section without increasing the number of steps only by changing a mask pattern at the time of patterning the interlayer insulating film. Therefore, even if the air is touched, the moisture in the air is taken in so that the wiring can be prevented from being short-circuited.

  The present invention also includes a step of forming a stopper insulating film having an etching rate different from that of the interlayer insulating film prior to the formation of the interlayer insulating film in the above method. Including a step of selectively removing the interlayer insulating film.

  With this configuration, the interlayer insulating film can be removed safely without removing the lower layer.

  Further, the present invention includes the above method, wherein the stopper insulating film is formed in the same process as the gate oxide film having the ONO structure.

  With this configuration, when the interlayer insulating film is removed, it can be safely removed only by changing the mask pattern in the patterning of the gate oxide film without adding a new process. In addition, since the silicon nitride is dense and has high moisture resistance, there is no risk of short circuit.

  According to the present invention, in the above method, the stopper insulating film is formed in the same process as the antireflection film.

  With this configuration, when the interlayer insulating film is removed, it can be safely removed by simply changing the mask pattern in the patterning of the antireflection film without adding a new process.

  According to the present invention, in the above method, the stopper insulating film is a laminated film of a silicon nitride film formed in the same process as the gate oxide film of the ONO structure and a silicon nitride formed in the same process as the antireflection film. Including things.

  With this configuration, when removing the interlayer insulating film, it can be safely removed by simply changing the mask pattern in the patterning of the gate oxide film and the antireflection film without adding a new process, and a more reliable passivation effect. Can be obtained.

  According to another aspect of the present invention, in the above method, the step of forming a plurality of solid-state imaging elements on the surface of the semiconductor substrate, and bonding a translucent member to the surface of the semiconductor substrate so as to face each light receiving region of the solid-state imaging element A step of dicing the semiconductor substrate so that a part of the wiring layer of the semiconductor substrate is exposed on the side surface, and forming an external connection terminal on the side surface of the semiconductor substrate corresponding to the solid-state imaging device And a step of separating the joined body formed in the joining step and having the external connection terminal formed for each solid-state imaging device.

  By this method, positioning is performed at the wafer level and integrated by mounting in a lump, and then separated for each solid-state imaging device, so that a solid-state imaging device that is easy to manufacture and highly reliable is formed. It becomes possible. From the viewpoint of light receiving efficiency, the translucent member is preferably formed to have a gap facing each light receiving region.

  According to the present invention, in the above method, the step of forming the external connection terminal includes a step of forming a terminal pattern by an ink jet method so as to contact the side surface of the wiring layer on the side surface of the semiconductor substrate.

  By this method, a highly accurate pattern can be formed efficiently, and it is possible to take out the electrode with high reliability.

As described above, according to the present invention, by removing the interlayer insulating film such as the BPSG film that causes the abnormality without affecting the device, it is possible to prevent a short circuit due to the penetration of moisture. The improvement of sex can be achieved. Further, by reducing the level difference due to the wiring, it is possible to suppress uneven resist application in the subsequent process.
Further, according to the method of the present invention, it is possible to form a solid-state imaging device with high reliability only by changing the pattern without requiring any additional process.

Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
First, an example in which the external extraction structure of the semiconductor device of the present invention is used for a solid-state imaging device will be described. As shown in the cross-sectional views of FIGS. 1A and 1B, this solid-state imaging device has an end face of a wiring structure formed on the surface of the silicon substrate 1 on which the photoelectric conversion portion (photodiode) and the charge transfer portion are formed. The BPSG film 10 (interlayer insulating film) as a reflow film for flattening formed under the aluminum wiring layer 11 is removed sufficiently from the inside to the edge of the dicing line. . The side (part) where there is no wiring may be left as it is, but in this embodiment, the interlayer insulating film is removed from the periphery of the silicon substrate (each chip) 1 over the entire circumference. This upper layer is covered with a protective film 8 made of a silicon nitride film formed by plasma CVD. FIG. 1A shows a cross-sectional view of a portion with wiring, and FIG. 1B shows a cross-sectional view of a portion without wiring. Here, it is assumed that the BPSG film 10 as the interlayer insulating film is removed in the region between the dicing line DL and the line L0 as shown in FIG. 2 illustrating the semiconductor wafer before being divided into chips.

According to this configuration, it is possible to prevent a short circuit caused by impurity ions in the BPSG film 10 or deterioration of the aluminum wiring layer due to the incorporation of moisture into the acid ions. In addition, according to this configuration, not only the reliability of the wiring is improved, but also the peripheral portion can be prevented from becoming high and a step can be prevented. Therefore, even when applying the color filter, uneven coating due to the step is eliminated. Can be eliminated.
The solid-state imaging device is cut by a dicing line DL and formed such that an aluminum wiring layer is exposed on the side surface, that is, the cut surface, and is configured to be taken out from the side surface.

  When mounting, it is formed so as to have a CSP structure by mounting and dividing at the wafer level. FIG. 3 is a schematic explanatory view showing a mounting structure using this solid-state image sensor. A sealing cover glass 201 is formed opposite to the light receiving region of the solid-state imaging device 100 formed on the silicon substrate 1, and a back cover glass 301 having a wiring pattern is formed on the back side. It is configured to have a moisture-resistant structure.

  That is, a spacer (not shown) is provided on the surface of the solid-state image pickup device substrate made of the silicon substrate 1 as a semiconductor substrate on which the solid-state image pickup device 100 is formed so as to have a gap corresponding to the light receiving region of the solid-state image pickup device. Thus, a glass substrate 201 as a translucent member constituting the sealing cover glass is bonded. These are bonded at a wafer level so that a plurality of elements are collectively mounted, and the periphery of the silicon substrate 1 is individually separated by dicing, and is formed on the back surface side through the side surface of the back cover glass 301 from the side wall of the silicon substrate. The wiring leads 302 formed on the bumps 305 are electrically connected via the bonding pads 304. Surface mounting is performed on the mounting substrate via the bumps 305. Reference numeral 303 denotes a passivation film.

  Here, the solid-state image pickup device substrate has a conventional structure, but the solid-state image pickup device is formed on the surface as shown in FIG. The silicon substrate 1 is arranged and formed with RGB color filters 50 (50G, 50B, 50R) and a microlens 60 formed thereon.

  Photodiodes 30 serving as photoelectric conversion units are arrayed on the surface of the n-type silicon substrate 1, and a charge transfer unit for transferring signal charges generated by the photodiodes 30 in the column direction (Y direction in FIG. 5). 40 is formed by meandering between a plurality of photodiode columns made up of a plurality of photodiodes 30 arranged in the column direction. Then, the odd-numbered photodiode rows are formed so as to be shifted in the direction of approximately half the array pitch of the photodiodes 30 arranged in the column direction with respect to the even-numbered photodiode rows.

  The charge transfer unit 40 includes a plurality of charge transfer channels 33 formed in the column direction of the surface portion of the silicon substrate 1 corresponding to each of the plurality of photodiode columns, and a charge transfer formed in the upper layer of the charge transfer channel 33. It includes an electrode 3 (first layer electrode 3a, second layer electrode 3b) and a charge readout region 34 for reading out charges generated in the photodiode 30 to the charge transfer channel 33. The charge transfer electrode 3 has a meandering shape extending in the row direction (X direction in FIG. 5) as a whole between a plurality of photodiode rows composed of a plurality of photodiodes 30 arranged in the row direction. . Here, the charge transfer electrode 3 has a single layer electrode structure in which a second layer electrode is formed on the first layer electrode via an interelectrode insulating film and is flattened by CMP, but is not limited to a single layer electrode structure. A two-layer electrode structure in which a part of the first layer electrode is covered with the second layer electrode may be used.

  As shown in FIG. 4, a p well layer 1P is formed on the surface of the silicon substrate 1, an n region 30b for forming a pn junction is formed in the p well layer 1P, and a p region 30a is formed on the surface. The photodiode 30 is configured, and the signal charge generated in the photodiode 30 is accumulated in the n region 30b.

  On the right side of the photodiode 30, a charge transfer channel 33 composed of an n region is formed with a slight distance. A charge readout region 34 is formed in the p-well layer 1P between the n region 30b and the charge transfer channel 33.

A gate oxide film 2 is formed on the surface of the silicon substrate 1, and a first electrode 3 a and a second electrode 3 b are formed on the charge readout region 34 and the charge transfer channel 33 via the gate oxide film 2. The An interelectrode insulating film 5 is formed between the first electrode 3a and the second electrode 3b. A channel stop 32 made of a p ⁺ region is provided on the right side of the vertical transfer channel 33, and is separated from the adjacent photodiode 30.

  An insulating film 6 such as a silicon oxide film and an antireflection layer 7 are formed on the charge transfer electrode 3, and an intermediate layer 70 is further formed thereon. Of the intermediate layer 70, 71 is a light shielding film, 10 is an interlayer insulating film made of BPSG (borophosphosilicate glass), 8 is an insulating film (passivation film) made of P-SiN, and 74 is flattened under a filter made of transparent resin or the like. It is a membrane. The light shielding film 71 is provided except for the opening of the photodiode 30. A color filter and a microlens 60 are provided above the intermediate layer 70. Between the color filter 50 and the micro lens 60, an on-filter flattening film 61 made of an insulating transparent resin or the like is formed.

  In the solid-state imaging device according to the present embodiment, signal charges generated in the photodiode 30 are accumulated in the n region 30b, and the accumulated signal charges are transferred in the column direction by the charge transfer channel 33, and the transferred signals are transferred. The charge is transferred in the row direction by a horizontal charge transfer path (HCCD) (not shown), and a color signal corresponding to the transferred signal charge is output from an amplifier (not shown). In other words, on the silicon substrate 1, a solid-state imaging device unit that is a region including a photoelectric conversion unit, a charge transfer unit, an HCCD, and an amplifier, and a peripheral circuit that is a region where peripheral circuits (PAD unit and the like) of the solid-state imaging device are formed. Are formed to constitute a solid-state imaging device.

Next, the manufacturing process of this solid-state imaging device will be described. First, the manufacturing process of a solid-state image sensor will be described. The photoelectric conversion portion and the charge transfer electrode of the solid-state imaging device are formed by a usual method, but here, the formation of the wiring layer, particularly the substrate peripheral portion, will be described, focusing on the substrate peripheral portion. 6A to 6F are cross-sectional views of a portion having wiring, and FIGS. 7A to 7F are cross-sectional views of a portion having no wiring. FIGS. (F) corresponds to each.
First, an n-type silicon substrate 1 is prepared, a field oxide film 9 is formed, and a gate oxide film 2 is formed on the surface of the n-type silicon substrate 1 on which a charge transfer channel, a channel stop region, and a charge readout region are formed. Form.

  Subsequently, a charge transfer electrode made of a phosphorus-doped doped amorphous silicon film 3, peripheral circuit wiring, and an evaluation pad are formed on the gate oxide film 2. Although not shown, the charge transfer electrode is patterned at the center of the substrate (FIGS. 6A and 7A). An insulating film such as a silicon oxide film or a silicon nitride film is formed on the charge transfer electrode by a usual method. At this time, the silicon nitride film 9N is left on the outer end portion of the field insulating film 9 at the peripheral edge (FIGS. 6B and 7B). This silicon nitride film 9N may be used as an antireflection film, leaving it at the periphery.

  Then, a TiN layer as an adhesive layer and a light shielding film (not shown: W layer) are sequentially formed on this upper layer by CVD.

  Next, a resist is applied and photolithography is performed to pattern the light shielding film.

Then, a BPSG film 10 is deposited by CVD, and the surface is flattened by reflow ((FIG. 6C, FIG. 7C)) and reflowed by high-temperature heat treatment at 800 to 900 ° C. as necessary. Thereafter, the BPSG film 10 is patterned by photolithography at the peripheral edge of the substrate (FIGS. 6D and 7D) At this time, an opening O for forming an evaluation pad is formed. Here, the silicon nitride film 9N is used as an etching stop layer.
Here, when forming the optical waveguide structure, it is preferable to form the opening O at the same time in an etching process for forming a columnar high refractive material layer to be an optical waveguide.

  A wiring layer 11 made of an aluminum layer is formed on the upper layer (FIGS. 6E and 7E). Then, a silicon nitride film 8 as a protective film is formed by plasma CVD, and is formed so as to cover the edge of the wiring layer 11 at the peripheral edge of the substrate (FIGS. 6 (f) and 7 (f)).

  Then, the silicon nitride film is etched and exposed to expose the aluminum layer in the bonding pad area, and then subjected to sintering in an inert gas atmosphere containing hydrogen, and is made of a transparent resin film (under the filter) and flattened. A film 74 (see FIG. 4) is formed.

Using the silicon wafer in which the solid-state image sensor is built in this way, positioning is performed at the wafer level and integrated by mounting in a lump, and then separated for each solid-state image sensor along the dicing line DL by dicing. Mounting is performed based on the so-called wafer level CSP method (see FIG. 3).
In this way, it is possible to form a solid-state imaging device very easily with good workability. As described above, according to the present invention, since positioning is performed at the wafer level and integrated by batch mounting and then separated for each solid-state imaging device, manufacture is easy and highly reliable. A solid-state imaging device can be formed. In addition, individual solid-state imaging devices can be formed by simply separating or polishing while the element formation surface is sealed in the gap by bonding, so there is little damage to the elements and there is no risk of dust contamination A highly reliable solid-state imaging device can be provided.
In the above embodiment, the BPSG film is removed over the entire periphery of the substrate. However, it is not always necessary to remove the entire periphery, and the interlayer insulating film is removed at the periphery only in a portion where there is no fear of a short circuit or the like. May be.

(Embodiment 2)
Next, a second embodiment of the present invention will be described. As shown in FIG. 8, the present embodiment is characterized in that an ONO film 2 that is a gate oxide film is used as an etching stopper when the BPSG film 10 is patterned. Other parts are the same as those in the first embodiment.
With this configuration, it is possible to form a solid-state imaging device with high reliability only by changing the pattern without requiring any additional process.

(Embodiment 3)
Next, a third embodiment of the present invention will be described. In this embodiment, as shown in FIG. 9, a laminated structure of an ONO film 2 as a gate oxide film and a silicon nitride film 9N formed in the same process as an antireflection film is used for patterning the BPSG film 10. It is characterized by being used. Other parts are the same as those in the first embodiment.
With this configuration, it is possible to form a solid-state imaging device with high reliability only by changing the pattern without requiring any additional process.

In the above embodiment, the wiring layer including the bonding pad is composed of an aluminum layer. However, the present invention is not limited to the aluminum layer, but may be other metal such as gold or another conductor layer such as silicide. Nor.
In forming the wiring lead, an ink jet method, supply with a dispenser, screen printing, stamp transfer, or the like can be selected as appropriate.
Furthermore, although the solid-state imaging device has been described in the above embodiment, it is needless to say that the present invention is not limited to the solid-state imaging device and can be applied to a normal semiconductor device such as an LSI constituting a logic circuit or the like. Absent.

  According to this configuration, it is possible to reduce the size, and it is useful as a solid-state imaging device in an electronic device such as a mobile phone. In addition, it is easy to manufacture and reliable because it is positioned at the wafer level and integrated into a single package, including the formation of electrode terminals for external extraction, and then separated into individual elements. A high semiconductor device can be formed.

It is principal part explanatory drawing which shows the solid-state image sensor of Embodiment 1 of this invention. It is a perspective view which shows the wafer which mounts the solid-state image sensor of Embodiment 1 of this invention. It is a figure which shows the mounting structure of the solid-state image sensor of Embodiment 1 of this invention. It is principal part sectional drawing of the solid-state image sensor of Embodiment 1 of this invention. It is a top view of the solid-state image sensor of Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is sectional drawing which shows the solid-state image sensor of Embodiment 2 of this invention. It is sectional drawing which shows the solid-state image sensor of Embodiment 3 of this invention. It is principal part explanatory drawing of the solid-state image sensor of a prior art example.

Explanation of symbols

1 Silicon substrate 2 Gate oxide film 3 Charge transfer electrode (doped amorphous silicon layer)
4 Silicon oxide film 5 Silicon nitride film 6 Insulating film 7 Silicon oxide film 8 Protective film 9 Field oxide film 10 Interlayer insulating film (BPSG film)
11 Aluminum wiring layer 50 Color filter 60 Microlens 70 Intermediate layer 71 Light-shielding film 74 Filter flattening film

Claims (16)

A semiconductor device having an interlayer insulating film and a wiring layer for external extraction on the surface of a semiconductor substrate in which an element region is formed,
A semiconductor device in which an interlayer insulating film containing impurities at least in contact with the wiring layer is removed at an edge portion of the semiconductor substrate in the interlayer insulating film. The semiconductor device according to claim 1,
The semiconductor device in which the interlayer insulating film containing impurities is a BPSG film or a PSG film. The semiconductor device according to claim 1, wherein
A semiconductor device comprising a stopper insulating film having an etching selectivity with respect to the interlayer insulating film under the interlayer insulating film. The semiconductor device according to claim 3,
A semiconductor device in which the stopper insulating film is silicon nitride. The semiconductor device according to claim 1,
A semiconductor device in which an interlayer insulating film containing the impurities is removed over the entire periphery of the semiconductor substrate. A semiconductor device according to claim 1,
The wiring layer is exposed to a peripheral portion of the semiconductor substrate, and is externally connected via a wiring lead formed on a side surface of the semiconductor substrate. A semiconductor device according to claim 1,
The wiring layer is a semiconductor device composed of a metal layer. The semiconductor device according to claim 7,
The semiconductor device, wherein the metal layer is aluminum or an aluminum alloy. A semiconductor device according to claim 1,
The semiconductor device is a solid-state imaging device, and constitutes a chip size package. A method for manufacturing a semiconductor device comprising an interlayer insulating film and a wiring layer for external extraction on the surface of a semiconductor substrate in which an element region is formed,
A method of manufacturing a semiconductor device, comprising: a step of selectively removing an interlayer insulating film containing impurities, which is in contact with at least the wiring layer among the interlayer insulating films, at an end portion of the semiconductor substrate. A method of manufacturing a semiconductor device according to claim 10,
Prior to the formation of the interlayer insulating film, including a step of forming a stopper insulating film having a different etching rate from the interlayer insulating film,
The removing step includes a step of selectively removing the interlayer insulating film using the stopper insulating film as a stopper. A method for manufacturing a semiconductor device according to claim 11, comprising:
The stopper insulating film is a method for manufacturing a semiconductor device, wherein the stopper insulating film is formed in the same process as a gate oxide film having an ONO structure. A method for manufacturing a semiconductor device according to claim 11, comprising:
The stopper insulating film is a method for manufacturing a semiconductor device, which is formed in the same process as the antireflection film. A method for manufacturing a semiconductor device according to claim 11, comprising:
The method of manufacturing a semiconductor device, wherein the stopper insulating film is a laminated film of a silicon nitride film formed in the same process as a gate oxide film having an ONO structure and a silicon nitride formed in the same process as an antireflection film. A method for manufacturing a semiconductor device according to claim 11, comprising:
Forming a plurality of solid-state imaging elements on the surface of the semiconductor substrate;
Bonding a translucent member to the surface of the semiconductor substrate so as to face each light receiving region of the solid-state imaging device;
Dicing the semiconductor substrate such that a part of the wiring layer of the semiconductor substrate is exposed on a side surface;
Forming an external connection terminal on a side surface of the semiconductor substrate corresponding to the solid-state imaging device;
A method of manufacturing a solid-state image pickup device, comprising: a step of separating, for each solid-state image pickup device, a joined body joined in the joining step and having external connection terminals formed thereon. A method for manufacturing a semiconductor device according to claim 11, comprising:
The step of forming the external connection terminal includes:
A method for manufacturing a semiconductor device, comprising: forming a terminal pattern so as to abut on a side surface of the wiring layer on a side surface of the semiconductor substrate by an inkjet method.

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