JP2006523059A5 - - Google Patents

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Publication number
JP2006523059A5
JP2006523059A5 JP2006506442A JP2006506442A JP2006523059A5 JP 2006523059 A5 JP2006523059 A5 JP 2006523059A5 JP 2006506442 A JP2006506442 A JP 2006506442A JP 2006506442 A JP2006506442 A JP 2006506442A JP 2006523059 A5 JP2006523059 A5 JP 2006523059A5
Authority
JP
Japan
Prior art keywords
demodulated signal
offset voltage
signal
subtracting
uncorrected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2006506442A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006523059A (ja
Filing date
Publication date
Priority claimed from GBGB0308168.4A external-priority patent/GB0308168D0/en
Application filed filed Critical
Publication of JP2006523059A publication Critical patent/JP2006523059A/ja
Publication of JP2006523059A5 publication Critical patent/JP2006523059A5/ja
Withdrawn legal-status Critical Current

Links

JP2006506442A 2003-04-09 2004-03-30 直流オフセット電圧補正部を有する受信機 Withdrawn JP2006523059A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0308168.4A GB0308168D0 (en) 2003-04-09 2003-04-09 Receiver having DC offset voltage correction
PCT/IB2004/001045 WO2004091160A1 (en) 2003-04-09 2004-03-30 Receiver having dc offset voltage correction

Publications (2)

Publication Number Publication Date
JP2006523059A JP2006523059A (ja) 2006-10-05
JP2006523059A5 true JP2006523059A5 (https=) 2007-03-01

Family

ID=9956462

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006506442A Withdrawn JP2006523059A (ja) 2003-04-09 2004-03-30 直流オフセット電圧補正部を有する受信機

Country Status (8)

Country Link
US (1) US20070177692A1 (https=)
EP (1) EP1616421A1 (https=)
JP (1) JP2006523059A (https=)
KR (1) KR20060002953A (https=)
CN (1) CN1768515A (https=)
GB (1) GB0308168D0 (https=)
TW (1) TW200501602A (https=)
WO (1) WO2004091160A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8195096B2 (en) 2006-07-13 2012-06-05 Mediatek Inc. Apparatus and method for enhancing DC offset correction speed of a radio device
TWI330026B (en) * 2007-04-02 2010-09-01 Realtek Semiconductor Corp Receiving system and related method for calibrating dc offset
CN101453229B (zh) * 2007-11-28 2013-07-03 瑞昱半导体股份有限公司 用以校正直流偏移的接收系统及其相关方法
JP2013222402A (ja) * 2012-04-18 2013-10-28 Nippon Reliance Kk オフセット調整回路及びプログラム
JP6939660B2 (ja) * 2018-03-13 2021-09-22 トヨタ自動車株式会社 車両走行制御システム

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0503728B1 (en) * 1991-03-15 1997-08-27 Koninklijke Philips Electronics N.V. Data receiver comprising a control loop with reduced sampling frequency
GB2274759B (en) * 1993-02-02 1996-11-13 Nokia Mobile Phones Ltd Correction of D.C offset in received and demodulated radio signals
US5724653A (en) * 1994-12-20 1998-03-03 Lucent Technologies Inc. Radio receiver with DC offset correction circuit
EP0863606B1 (en) * 1997-03-05 2003-09-24 Nec Corporation Direct conversion receiver capable of cancelling DC offset voltages
TW405314B (en) * 1998-08-28 2000-09-11 Ind Tech Res Inst Device for eliminating DC offset utilizing noise regulation technique and its method
GB2349313A (en) * 1999-04-21 2000-10-25 Ericsson Telefon Ab L M Radio receiver
US6275087B1 (en) * 1999-11-16 2001-08-14 Lsi Logic Corporation Adaptive cancellation of time variant DC offset
GB0100202D0 (en) * 2001-01-04 2001-02-14 Koninkl Philips Electronics Nv Receiver having a variable threshold slicer stage and a method of updating the threshold levels of the slicer stage
DE10251288B4 (de) * 2002-11-04 2005-08-11 Advanced Micro Devices, Inc., Sunnyvale Equalizerschaltung mit Kerbkompensation für einen Direktmischempfänger

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