JP2006344714A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing a charge leak of a capacitor provided at a memory cell, and also, capable of increasing the effective area of the capacitor while suppressing a variations in the capacity value of the capacitor. <P>SOLUTION: A separation trench 40 is formed on an SOI layer 3. A separation insulating film 4 is formed in the separation trench 40. An opening 41 for exposing the inner wall of the separation trench 40 is formed at the separation insulating film 4. The opening 41 reaches an insulating layer 2. A lower electrode (an impurity diffused layer 24) and a dielectric layer 21 of a capacitor 102 are extended to the inner wall of the separation trench 40 exposed to the opening 41. At least a part of an upper electrode 22 is embedded into the opening 41. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a capacitor such as a DRAM (Dynamic Random Access Memory).

  As a conventional semiconductor memory device, a DRAM cell is known which includes a MOS (Metal-Oxide Semiconductor) transistor and a capacitor having an impurity diffusion layer connected to the source / drain region of the MOS transistor as a lower electrode ( For example, Patent Document 1). In the DRAM cell of Patent Document 1, a recess (cavity) in which a side wall portion of the semiconductor substrate is exposed is formed on an upper portion of the isolation insulating film (field insulating film) disposed on the upper surface of the semiconductor substrate. The capacitor of the DRAM cell has a three-dimensional structure that extends to the side wall portion exposed in the recess, thereby increasing the effective area of the capacitor and increasing the capacitance.

JP-T-2004-527901

  In the DRAM cell as described above, the depth of the recess in which the capacitor is formed is conventionally about half the depth of the isolation trench. That is, an isolation insulating film having a predetermined thickness (about 50 to 200 nm) is left under the recess. The deeper the recess, the larger the effective area of the capacitor. However, if the depth is increased too much, the isolation insulating film becomes thin, and a parasitic MOS transistor is formed under the isolation insulating film (that is, between adjacent cells). As a result, the separation function is impaired. If a parasitic MOS transistor is formed between adjacent cells, a charge leak occurs through the parasitic MOS transistor, and the reliability of the DRAM cell is lowered. For this reason, the depth of the recess is limited, and there is a limit to the increase in capacitance of the capacitor.

  Further, in the above DRAM cell structure, since the capacitance value of the capacitor depends on the depth of the recess, if the depth varies during the formation of the recess, the capacitance value of the capacitor varies, leading to a decrease in the reliability of the DRAM cell. End up.

  The present invention has been made in order to solve the above-described problems. In a semiconductor device including a capacitor such as a DRAM cell, the present invention suppresses charge leakage of the capacitor and increases the effective area of the capacitor and its capacitance value. It aims at suppressing the dispersion | variation of.

  A semiconductor device according to the present invention is defined by an insulating layer formed on a support substrate, a semiconductor layer formed on the insulating layer, a trench formed in the semiconductor layer, and the trench in the semiconductor layer. An active region, an isolation insulating film formed in the trench, a first electrode that is an impurity diffusion layer formed in the active region, a dielectric layer formed on a surface of the impurity diffusion layer, and the dielectric A capacitor comprising a second electrode formed on the body layer, wherein in the capacitor formation region, the trench reaches the insulating layer, and the second electrode is in the trench. It is buried and reaches the insulating layer.

  According to the present invention, since the opening formed in the isolation insulating film reaches the insulating layer and the capacitor reaches the insulating layer, the effective area of the capacitor is increased. That is, the capacitance of the capacitor can be increased without increasing the formation area. Further, since the semiconductor layer is removed under the opening, a parasitic MOS transistor is not formed under the opening. Therefore, it is possible to prevent charge leakage of the capacitor. Furthermore, since the area of the capacitor is determined by the thickness of the semiconductor layer and does not depend on the depth of the opening, variation in capacitance value is suppressed. For example, by applying the capacitor to a DRAM cell, it is possible to contribute to reduction of the cell formation area and improvement of reliability.

<Embodiment 1>
FIG. 1A is a circuit diagram of a general DRAM cell. The DRAM cell 100 includes a P-channel MOS transistor 101 that is a transfer gate for writing, refreshing, and reading data, and a capacitor 102 that accumulates charges corresponding to data. The gate terminal of the MOS transistor 101 is connected to the word line WL, one of the source / drain terminals is connected to the bit line BL, and the other is connected to one terminal of the capacitor 102. The other terminal of the capacitor 102 is connected to a predetermined power source.

  In recent years, as a DRAM cell, a twin-cell type DRAM cell (hereinafter sometimes simply referred to as “twin cell”) in which two DRAM cells 100 are used per bit has been attracting attention (FIG. 1B). As shown in FIG. 1B, one twin cell 200 is composed of two DRAM cells 100 sharing a word line WL. The two DRAM cells 100 operate so as to read and write data signals complementary to each other. That is, complementary data signals are input / output to / from the pair of bit lines BL0 and BL1 to which the twin cell 200 is connected. According to the twin cell 200, the amplitude of the read signal can be doubled that of the normal DRAM cell 100 (hereinafter also referred to as “single cell”) in FIG. 1A, and the two DRAM cells 100 are complementary. Since the noise is canceled by performing the operation, high-speed operation becomes possible.

  Since two general cells may be used as the two single cells constituting the twin cell, the twin cell DRAM can be formed by a manufacturing process similar to that of the single cell DRAM. A twin-cell DRAM can achieve a higher degree of integration than an SRAM, and therefore can be expected to have high cost performance. The present invention described below can be applied to both single-cell and twin-cell DRAMs. However, for the sake of simplicity, the following description will be mainly given as a single-cell DRAM.

  2 and FIGS. 3A and 3B are diagrams showing the configuration of the semiconductor memory device according to the first embodiment. More specifically, FIG. 2 is a top view of a DRAM cell array included in the semiconductor memory device, and FIGS. 3A and 3B are taken along lines AA and BB in FIG. 2, respectively. It is sectional drawing. In these drawings, the same symbols are attached to the same elements.

  FIG. 3A shows a cross section of two DRAM cells adjacent in the extending direction of the bit line BL (the AA line direction in FIG. 2). That is, FIG. 3A shows two DRAM cells 100 each composed of a MOS transistor 101 and a capacitor 102. FIG. 3B shows a cross section of an element isolation region between DRAM cells adjacent to each other in the extending direction of a word line WL (corresponding to a gate electrode 12 described later).

  In the case of a twin cell, since it is necessary to supply the same signal to the word line corresponding to the paired DRAM cell 100, for example, in the layout of FIG. 2, the extension of the word line WL (gate electrode 12) The DRAM cells adjacent in the direction may be paired.

  As shown in FIG. 3A, the DRAM cell 100 according to the present embodiment is formed on a so-called SOI substrate including a silicon support substrate 1, an insulating layer 2, and an SOI (Silicon-On-Insulator) layer 3. An isolation trench 40 is formed in the SOI layer 3, and an isolation insulating film 4 is formed in the isolation trench 40. This isolation trench 40 (isolation insulating film 4) is also formed in a peripheral circuit region (not shown) other than the DRAM cell region, and defines an active region 5 in which each semiconductor element is formed. For example, a high density plasma (HDP: High Density Plasma) oxide film is used for the isolation insulating film 4.

  The MOS transistor 101 of the DRAM cell 100 includes a gate oxide film 11 formed on the upper surface of the N-type SOI layer 3, a polysilicon gate electrode 12 formed thereon, and a sidewall formed on the side surface of the gate electrode 12. 13, source / drain regions 14 and 15 which are P-type impurity diffusion layers formed on both sides of the gate electrode 12 on the upper surface of the SOI layer 3. The source / drain region 14 is connected to a contact 16 (hereinafter referred to as “bit line contact 16”) connected to the bit line BL. As shown in FIG. 3A, the bit line contact 16 is shared by the DRAM cells 100 on both sides. If necessary, silicide layers may be formed on the gate electrode 12 and the source / drain regions 14 and 15, respectively.

  On the other hand, the capacitor 102 of the DRAM cell 100 is formed on a lower electrode (hereinafter referred to as “lower diffusion layer 24”) which is a P-type impurity diffusion layer 24 formed in the SOI layer 3 and on the surface of the lower diffusion layer 24. And the upper electrode 22 formed on the dielectric layer 21. If necessary, a silicide layer may be formed on the upper electrode 22. The lower diffusion layer 24 is connected to the source / drain region 15 of the MOS transistor 101. That is, the lower diffusion layer 24 functions as an electrode (storage node) on the side connected to the MOS transistor 101 in the capacitor 102 of the circuit of FIG. Although not shown, a DRAM cell 100 similar to that shown in FIG. 3A is formed on the outside of FIG. 3A, and the upper electrode 22 is shared by the DRAM cells 100 on both sides.

  In the present embodiment, as shown in FIGS. 3A and 3B, an opening 41 is provided below the upper electrode 22 in the isolation insulating film 4. The opening 41 exposes the inner wall of the isolation trench 40 (side wall of the active region 5) and penetrates the SOI layer 3 to reach the insulating layer 2 therebelow. In the cross section of FIG. 3A, the entire isolation trench 40 corresponds to the opening 41, so that the isolation insulating film 4 is completely removed.

  In each DRAM cell 100, the dielectric layer 21 and the lower diffusion layer 24 of the capacitor 102 extend from the upper surface of the SOI layer 3 to the inner wall of the isolation trench 40 (the inner wall of the opening 41), and a part of the upper electrode 22 is formed. It is embedded in the opening 41. With this configuration, the sidewall of the isolation trench 40 together with the upper surface of the SOI layer 3 also contributes as the effective area of the capacitor 102, and the capacitance value increases.

  Further, as shown in FIG. 3B, the opening 41 is also formed below the upper electrode 22 between the DRAM cells 100 adjacent to each other in the extending direction of the gate electrode 12, and the inner wall of the isolation trench 40 (FIG. 3B). (Not shown in FIG. 2 and indicated by reference numeral 50 in FIG. 2). The lower diffusion layer 24 and the dielectric layer 21 shown in FIG. 3A are also formed on the inner wall 50 side. Therefore, the inner wall 50 also contributes to the effective area of the capacitor 102, and the capacitance of the capacitor 102 further increases.

  In particular, in the present embodiment, the opening 41 reaches the insulating layer 2 below the SOI layer 3, and therefore, as shown in FIG. 3A, the dielectric layer 21, the lower diffusion layer 24, and the upper electrode 22 ( That is, the capacitor 102) can be formed to reach the insulating layer 2, and the effective area of the capacitor 102 can be increased. That is, the capacitance of the capacitor 102 can be increased without increasing the formation area, and as a result, it can contribute to the reduction of the DRAM cell.

  Further, since the bottom of the upper electrode 22 reaches the insulating layer 2, no parasitic MOS transistor is formed below the upper electrode 22 (that is, between adjacent cells across the upper electrode 22). Therefore, charge leakage between adjacent cells can be prevented, good separation characteristics between cells can be obtained, and the reliability of the DRAM cell 100 is improved.

  Since the opening 41 penetrates the SOI layer 3, the area of the inner wall (that is, the side surface of the active region 5) of the isolation trench 40 exposed in the opening 41 is determined by the thickness of the SOI layer 3. It does not depend on the depth. Therefore, when the thickness of the SOI layer 3 is uniform, the effective area of the capacitor 102 is substantially constant, and variation in the capacitance value is suppressed.

  As described above, according to the present embodiment, it is possible to obtain a DRAM having a large capacity and a stable capacitance value while suppressing a formation area. As described above, the present invention can also be applied to a twin-cell DRAM. A twin-cell DRAM requires two single cells per bit and requires a relatively large formation area. However, application of the present invention can suppress an increase in formation area.

  Next, a method for manufacturing the semiconductor memory device according to the present embodiment will be described. 4 to 12 are process diagrams for explaining the manufacturing method. Each figure (a) corresponds to the cross section shown in FIG. 3 (a), and each figure (b) corresponds to the cross section shown in FIG. 3 (b).

  First, an SOI substrate including a support substrate 1, an insulating layer 2, and an SOI layer 3 is prepared, and a silicon oxide film 51 and a silicon nitride film 52 are sequentially formed on the SOI layer 3. Further thereon, a resist pattern 53 opened in the pattern of the isolation trench 40 is formed (FIGS. 4A and 4B). Then, the silicon nitride film 52, the silicon oxide film 51, and the SOI layer 3 are etched using the resist pattern 53 as a mask to form an isolation trench 40 that reaches the insulating layer 2 (FIGS. 5A and 5B). That is, the depth of the isolation trench 40 formed at this time is not less than the thickness of the SOI layer 3 (for example, about 200 nm to 400 nm).

  Thereafter, the inner wall of the isolation trench 40 is oxidized to form a silicon oxide film having a thickness of about 20 nm, and then an HDP oxide film is deposited on the entire surface to fill the isolation trench 40, and the excess HDP oxide film is removed by CMP. An isolation insulating film 4 is formed in the trench 40 (FIGS. 6A and 6B). Thereafter, the silicon nitride film 52 and the silicon oxide film 51 are also removed by wet etching.

  Next, a resist pattern 54 opened in the pattern of the opening 41 is formed. Then, by selectively removing the isolation insulating film 4 by anisotropic dry etching using the resist pattern 54 as a mask, an opening 41 reaching the insulating layer 2 is formed (FIGS. 7A and 7B). )). Although the width of the opening of the resist pattern 54 is wider than the width of the isolation trench 40 in the cross section of FIG. 7A, this etching process has high selectivity between the isolation insulating film 4 and the SOI layer 3. By using the obtained etching technique, only the isolation insulating film 4 is selectively removed, and the upper surface of the SOI layer 3 is hardly removed.

  Subsequently, P-type ions such as boron ions are implanted using the resist pattern 54 as a mask to form the lower diffusion layer 24 (FIGS. 8A and 8B). At this time, P-type ions are also implanted into the inner wall portion of the isolation trench 40 exposed at the opening 41.

  After removing the resist pattern 54, the surface of the SOI layer 3 including the inside of the opening 41 is oxidized to form a silicon oxide film 55 of about 2 nm, and a polysilicon film 56 of about 100 nm to 200 nm is further formed on the entire surface ( FIG. 9 (a), (b)). Next, a resist pattern 57 of an electrode pattern is formed on the polysilicon film 56 (FIGS. 10A and 10B), and the silicon oxide film 55 and the polysilicon film 56 are patterned by dry etching using the resist pattern 57 as a mask. Thereby, the gate oxide film 11 and the gate electrode 12, and the dielectric layer 21 and the upper electrode 22 are formed (FIGS. 11A and 11B).

  Then, an LDD (Lightly Doped Drain) layer is formed on both sides of the gate electrode 12 by ion implantation, and a silicon nitride film is deposited on the entire surface and etched back to form sidewalls on the side surfaces of the gate electrode 12 and the upper electrode 22, respectively. After forming 13 and 23, further ion implantation is performed to form source / drain regions 14 and 15 (FIGS. 12A and 12B). Thereby, DRAM cell 100 including MOS transistor 101 and capacitor 102 is formed. At this time, a silicide layer may be formed on the upper surfaces of the gate electrode 12, the source / drain regions 14, 15 and the upper electrode 22 as necessary.

  Thereafter, a silicon oxide film is deposited by an ordinary method to form an interlayer insulating film 6, a bit line contact 16 is formed therein, and a bit line BL is disposed on the interlayer insulating film 6. At the same time, a word line contact for connecting the gate electrode 12 to the metal word line WL, a contact (cell plate contact) for connecting the upper electrode 22 and the like are also formed. Through the above steps, the semiconductor memory device shown in FIGS. 3A and 3B is formed.

<Embodiment 2>
13A and 13B are diagrams showing the configuration of the semiconductor memory device according to the second embodiment, and are cross sections taken along lines AA and BB of the DRAM cell array shown in FIG. 2, respectively. It corresponds to. In FIGS. 13A and 13B, elements having the same functions as those in FIGS. 3A and 3B are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the semiconductor memory device according to the second embodiment, as shown in FIGS. 13A and 13B, the opening 41 penetrates the SOI layer 3 and penetrates into the insulating layer 2. The opening 41 is wide in the lateral direction inside the insulating layer 2 in the cross section of FIG. 13A, and part of the bottom surface of the SOI layer 3 (indicated by reference numeral 58 in FIG. 13A). Is exposed. The lower diffusion layer 24 and the dielectric layer 21 are formed so as to extend also to the bottom surface 58.

  According to the present embodiment, the opening 41 enters the insulating layer 2 so as to expose the bottom surface 58 of the SOI layer 3, and the dielectric layer 21, the lower diffusion layer 24, and the upper electrode 22 (that is, the capacitor 102). Therefore, the bottom surface 58 also contributes to the effective area of the capacitor 102, so that the capacitance of the capacitor 102 can be further increased as compared with the first embodiment. Therefore, the formation area of the DRAM cell 100 can be further reduced.

  Further, since the bottom of the upper electrode 22 enters the insulating layer 2, no parasitic MOS transistor is formed under the upper electrode 22 (between adjacent cells). Therefore, as in the first embodiment, charge leakage between adjacent cells can be prevented, and good separation characteristics between cells can be obtained. Further, as in the first embodiment, the effective area of the capacitor 102 does not depend on the depth of the opening 41, so that variation in capacitance value is suppressed. Therefore, the reliability of the DRAM cell 100 is improved.

  In the example of FIGS. 13A and 13B, the opening 41 penetrates through the insulating layer 2 and reaches the support substrate 1. Therefore, the upper electrode 22 embedded in the opening 41 also reaches the support substrate 1. If the upper electrode 22 is electrically connected to the silicon support substrate 1, there is a concern about problems such as leakage current through the support substrate 1, but the oxide film 61 is formed at the boundary portion of the support substrate 1 with the upper electrode 22. Since these are formed, both are electrically separated. However, in the present embodiment, the opening 41 does not necessarily reach the support substrate 1, and in that case, the oxide film 61 may be omitted.

  A method for manufacturing the semiconductor memory device according to the present embodiment will be described. 14 to 19 are process diagrams for explaining the manufacturing method. In these figures, each figure (a) corresponds to the cross section shown in FIG. 13 (a), and each figure (b) corresponds to the cross section shown in FIG. 13 (b).

  First, in the same manner as in the first embodiment, the isolation trench 40 reaching the insulating layer 2 is formed in the SOI layer 3, and the isolation insulating film 4 is formed therein (FIGS. 6A and 6B). Then, a resist pattern 54 opened in the pattern of the opening 41 is formed, and the opening 41 reaching the insulating layer 2 is formed in the isolation insulating film 4 by anisotropic dry etching using the resist pattern 54 as a mask. (FIGS. 7A and 7B).

  In the present embodiment, the insulating layer 2 is further etched thereafter to further deepen the opening 41. However, in this step, isotropic wet etching that can selectively remove only the isolation insulating film 4 from the SOI layer 3 is used. Therefore, in the etching process, the side surface (side surface of the active region 5) of the SOI layer 3 exposed to the opening 41 is not etched, and the opening 41 not only digs down at the bottom but also spreads in the lateral direction. As a result, the SOI layer 3 overhangs in the opening 41 as shown in FIG. That is, the bottom surface 58 of the insulating layer 2 is exposed in the opening 41. In this example, the upper surface of the support substrate 1 is exposed at the bottom of the opening 41.

  Subsequently, the lower diffusion layer 24 is formed by implanting P-type ions such as boron ions using the resist pattern 54 as a mask (FIGS. 15A and 15B). At this time, the lower diffusion layer 24 is formed deep so as to extend not only to the inner wall portion of the isolation trench 40 exposed to the opening 41 but also to the bottom surface 58.

  After removing the resist pattern 54, the surface of the SOI layer 3 including the bottom surface 58 is oxidized to form a silicon oxide film 55. At this time, the surface of the support substrate 1 exposed at the bottom of the opening 41 is also oxidized, and an oxide film 61 is formed. Thereafter, a polysilicon film 56 is formed on the entire surface including the inside of the opening 41 (FIGS. 16A and 16B). At this time, since the SOI layer 3 is overhanging in the opening 41, for example, by using a technique having excellent coverage such as a CVD (Chemical Vapor Deposition) method, the area near the bottom surface 58 in the polysilicon film 56 is used. It is desirable to prevent the generation of voids.

  Then, a resist pattern 57 of an electrode pattern is formed (FIGS. 17A and 17B), and the silicon oxide film 55 and the polysilicon film 56 are patterned by dry etching using the resist pattern 57 as a mask, and the gate oxide film 11 and The gate electrode 12, and the dielectric layer 21 and the upper electrode 22 are formed (FIGS. 18A and 18B).

  Thereafter, as in the first embodiment, sidewalls 13 and 23 and source / drain regions 14 and 15 are formed, thereby forming DRAM cell 100 including MOS transistor 101 and capacitor 102 (FIG. 19A). , (B)). Then, by forming the interlayer insulating film 6, the bit line contact 16, the bit line BL, etc., the semiconductor memory device according to the present embodiment shown in FIGS. 13A and 13B is formed.

<Embodiment 3>
20A and 20B are diagrams showing a configuration of the semiconductor memory device according to the third embodiment, and correspond to cross sections taken along the lines AA and BB in FIG. 2, respectively. . 20 (a) and 20 (b), elements having the same functions as those in FIGS. 3 (a) and 3 (b) are denoted by the same reference numerals, and detailed description thereof is omitted. .

  As shown in FIGS. 20A and 20B, in the semiconductor memory device according to the third embodiment, the opening 41 penetrates the SOI layer 3 and reaches the insulating layer 2 as in the first embodiment. However, as shown in FIG. 20B, the isolation insulating film 4 does not reach the insulating layer 2 except in the region where the opening 41 is formed, and the SOI layer 3 is not between the isolation insulating film 4 and the insulating layer 2. Remains. That is, in the present embodiment, the isolation insulating film 4 between cells adjacent in the extending direction of the word line WL (gate electrode 12) is a so-called “partial isolation (PTI: Partial Trench Isolation)”. .

  According to the present embodiment, since the isolation insulating film 4 between adjacent cells is partial isolation, the cell potential (body potential) is set via the SOI layer 3 remaining under the isolation insulating film 4. Is possible. Therefore, the degree of freedom of cell layout is increased, and the electrical characteristics of the device can be improved.

  Also in the present embodiment, since the opening 41 where the capacitor 102 is formed reaches the insulating layer 2 below the SOI layer 3, the same effect as in the first embodiment can be obtained. That is, since the capacitance can be increased without increasing the formation area of the capacitor 102, it can contribute to the reduction of the DRAM cell. Further, no parasitic MOS transistor is formed under the upper electrode 22, and charge leakage can be prevented. Furthermore, since the effective area of the capacitor 102 does not depend on the depth of the opening 41, variation in capacitance value is suppressed.

  That is, according to the present embodiment, in addition to the same effect as that of the first embodiment, an effect that a DRAM cell having further excellent electrical characteristics can be obtained.

  In the present embodiment, the upper electrode 22 is in contact with the SOI layer 3 below the isolation insulating film 4 as shown in FIG. 20B. However, a dielectric portion is formed at the boundary between the SOI layer 3 and the upper electrode 22. Since the body layer 21 extends, both are electrically separated. Further, since the opening 41 reaches the insulating layer 2, it functions as a so-called “Full Trench Isolation (FTI)”. That is, the DRAM cell according to the present embodiment has a “hybrid trench isolation (HTI) structure” in which the isolation trench 40 includes both a partial isolation region and a complete isolation region. .

  A method for manufacturing the semiconductor memory device according to the present embodiment will be described. 21 to 30 are process diagrams for explaining the manufacturing method. In these figures, each figure (a) corresponds to the cross section shown in FIG. 20 (a), and each figure (b) corresponds to the cross section shown in FIG. 20 (b).

  First, similarly to the first embodiment, a silicon oxide film 51 and a silicon nitride film 52 are sequentially formed on the SOI layer 3, and a resist pattern 53 having an opening in the pattern of the isolation trench 40 is formed thereon (FIG. 4 ( a), (b)). Then, the isolation trench 40 is formed by etching the silicon nitride film 52, the silicon oxide film 51, and the SOI layer 3 using the resist pattern 53 as a mask. However, in this step, the etching is stopped before the isolation trench 40 reaches the insulating layer 2, and the SOI layer 3 is left at the bottom of the isolation trench 40 as shown in FIGS. That is, the depth of the isolation trench 40 formed at this time is less than the thickness of the SOI layer 3 (for example, if the SOI layer 3 is about 200 nm to 400 nm, the depth of the isolation trench 40 after this step is 50 About 150 nm).

  Then, a resist pattern 63 is embedded in a region to be partially separated in the isolation trench 40. In the DRAM cell of the present embodiment, as shown in FIGS. 20A and 20B, the region of the opening 41 where the capacitor 102 is formed is completely separated, and the other region is partially separated. Therefore, as shown in FIGS. 22A and 22B, a resist pattern 63 in which the formation region of the opening 41 is opened is formed in the isolation trench 40.

  Thereafter, the SOI layer 3 is etched again using the silicon nitride film 52 and the resist pattern 63 as a mask, so that the isolation trench 40 is further dug down to reach the insulating layer 2 (FIGS. 23A and 23B).

  After removing the resist pattern 63 and oxidizing the inner wall of the isolation trench 40 to form a silicon oxide film having a thickness of about 20 nm, an HDP oxide film is deposited on the entire surface to fill the isolation trench 40, and an excess HDP oxide film is formed by CMP. By removing, the isolation insulating film 4 is formed in the isolation trench 40 (FIGS. 24A and 24B). Thereafter, the silicon nitride film 52 and the silicon oxide film 51 are also removed by wet etching.

  Then, a resist pattern 54 opened in the pattern of the opening 41 is formed on the SOI layer 3, and the opening 41 reaching the insulating layer 2 is formed by anisotropic dry etching using the resist pattern 54 as a mask ( FIG. 25 (a), (b)). Subsequently, the lower diffusion layer 24 is formed by implanting P-type ions such as boron ions using the resist pattern 54 as a mask (FIGS. 26A and 26B).

  After removing the resist pattern 54, the surface of the SOI layer 3 including the inner wall of the opening 41 is oxidized to form a silicon oxide film 55. Thereafter, a polysilicon film 56 is formed on the entire surface (FIGS. 27A and 27B), and an electrode pattern 57 is formed thereon (FIGS. 28A and 28B). Then, the silicon oxide film 55 and the polysilicon film 56 are patterned by dry etching using the resist pattern 57 as a mask to form the gate oxide film 11 and the gate electrode 12, and the dielectric layer 21 and the upper electrode 22 (FIG. 29 (a), (b)).

  Thereafter, as in the first embodiment, sidewalls 13 and 23 and source / drain regions 14 and 15 are formed, thereby forming DRAM cell 100 including MOS transistor 101 and capacitor 102 (FIG. 30A). , (B)). Then, by forming the interlayer insulating film 6, the bit line contact 16, the bit line BL, etc., the semiconductor memory device according to the present embodiment shown in FIGS. 20A and 20B is formed.

  In the present embodiment, in the isolation trench 40, it is possible to selectively use partial isolation and complete isolation. As described above, the isolation trench 40 is also formed in a peripheral circuit region (not shown) other than the DRAM cell region. However, according to the present embodiment, the isolation trench 40 in the peripheral circuit region is also completely isolated. And partial separation can be used properly. That is, in the steps described with reference to FIGS. 22A and 22B, the resist pattern 63 may be formed in a region to be partially separated in the peripheral circuit region.

  In other words, according to the present embodiment, the body potential can be set through the SOI layer 3 under partial isolation also in the peripheral circuit region, so that the degree of freedom in circuit layout increases and the device The effect that the electrical characteristics can be improved can be obtained.

  In the present embodiment, as shown in FIGS. 20A and 20B, the structure in which the opening 41 reaches the upper surface of the insulating layer 2 is shown, but the second embodiment is applied. It is also possible. That is, the opening 41 may be formed so as to enter the inside of the insulating layer 2 so that a part of the bottom surface of the SOI layer 3 is exposed in the opening 41, and the capacitor 102 may be extended to the bottom surface. . Thereby, the effective area of capacitor 102 according to the third embodiment can be further increased. In that case, the insulating layer 2 at the bottom of the opening 41 may be removed by isotropic wet etching after the steps described with reference to FIGS. 25A and 25B in the manufacturing method of the present embodiment described above. .

It is a circuit diagram of a general DRAM cell. 2 is a top view of the DRAM cell array according to the first embodiment. FIG. 1 is a cross-sectional view of a DRAM cell included in a semiconductor memory device according to a first embodiment. FIG. 6 is a process diagram illustrating the method for manufacturing the DRAM cell according to the first embodiment. FIG. 6 is a process diagram illustrating the method for manufacturing the DRAM cell according to the first embodiment. FIG. 6 is a process diagram illustrating the method for manufacturing the DRAM cell according to the first embodiment. FIG. 6 is a process diagram illustrating the method for manufacturing the DRAM cell according to the first embodiment. FIG. 6 is a process diagram illustrating the method for manufacturing the DRAM cell according to the first embodiment. FIG. 6 is a process diagram illustrating the method for manufacturing the DRAM cell according to the first embodiment. FIG. 6 is a process diagram illustrating the method for manufacturing the DRAM cell according to the first embodiment. FIG. 6 is a process diagram illustrating the method for manufacturing the DRAM cell according to the first embodiment. FIG. 6 is a process diagram illustrating the method for manufacturing the DRAM cell according to the first embodiment. FIG. 6 is a cross-sectional view of a DRAM cell included in a semiconductor memory device according to a second embodiment. FIG. 10 is a process diagram illustrating a method of manufacturing a DRAM cell according to a second embodiment. FIG. 10 is a process diagram illustrating a method of manufacturing a DRAM cell according to a second embodiment. FIG. 10 is a process diagram illustrating a method of manufacturing a DRAM cell according to a second embodiment. FIG. 10 is a process diagram illustrating a method of manufacturing a DRAM cell according to a second embodiment. FIG. 10 is a process diagram illustrating a method of manufacturing a DRAM cell according to a second embodiment. FIG. 10 is a process diagram illustrating a method of manufacturing a DRAM cell according to a second embodiment. FIG. 6 is a cross-sectional view of a DRAM cell included in a semiconductor memory device according to a third embodiment. FIG. 10 is a process diagram illustrating a method of manufacturing a DRAM cell according to a third embodiment. FIG. 10 is a process diagram illustrating a method of manufacturing a DRAM cell according to a third embodiment. FIG. 10 is a process diagram illustrating a method of manufacturing a DRAM cell according to a third embodiment. FIG. 10 is a process diagram illustrating a method of manufacturing a DRAM cell according to a third embodiment. FIG. 10 is a process diagram illustrating a method of manufacturing a DRAM cell according to a third embodiment. FIG. 10 is a process diagram illustrating a method of manufacturing a DRAM cell according to a third embodiment. FIG. 10 is a process diagram illustrating a method of manufacturing a DRAM cell according to a third embodiment. FIG. 10 is a process diagram illustrating a method of manufacturing a DRAM cell according to a third embodiment. FIG. 10 is a process diagram illustrating a method of manufacturing a DRAM cell according to a third embodiment. FIG. 10 is a process diagram illustrating a method of manufacturing a DRAM cell according to a third embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Support substrate, 2 Insulating layer, 3 SOI layer, 4 Isolation insulating film, 5 Active region, 6 Interlayer insulating film, 11 Gate oxide film, 12 Gate electrode, 13 Side wall, 14, 15 Source / drain region, 16 Bit line Contacts 16, 21 Dielectric layer, 22 Upper electrode, 23 Side wall, 24 Lower diffusion layer, 40 Isolation trench, 41 Opening.

Claims (5)

An insulating layer formed on the support substrate;
A semiconductor layer formed on the insulating layer;
A trench formed in the semiconductor layer;
An active region defined by the trench in the semiconductor layer;
An isolation insulating film formed in the trench;
A semiconductor comprising: a first electrode that is an impurity diffusion layer formed in the active region; a dielectric layer formed on a surface of the impurity diffusion layer; and a capacitor comprising a second electrode formed on the dielectric layer A device,
In the capacitor formation region, the trench reaches the insulating layer,
The semiconductor device, wherein the second electrode is embedded in the trench and reaches the insulating layer. The semiconductor device according to claim 1,
The impurity diffusion layer and the dielectric layer extend from the upper surface of the active region to the inner wall of the trench,
A part of said 2nd electrode is extended on the said dielectric material layer on the said active region, The semiconductor device characterized by the above-mentioned. A semiconductor device according to claim 1 or 2, wherein
A portion of the second electrode penetrates under a portion of the bottom surface of the semiconductor layer;
The semiconductor device, wherein the impurity diffusion layer and the dielectric layer also extend to part of the bottom surface of the semiconductor layer. A semiconductor device according to any one of claims 1 to 3,
A semiconductor device comprising the semiconductor layer between the isolation insulating film and the insulating layer. The semiconductor device according to claim 1, wherein:
A gate insulating film formed in the active region;
A gate electrode formed on the gate insulating film;
A MOS transistor having a first conductivity type impurity diffusion layer formed on both sides of the gate electrode;
The impurity diffusion layer of the first conductivity type of the MOS transistor is electrically connected to the impurity diffusion layer of the first conductivity type that is the first electrode;
The semiconductor device, wherein the MOS transistor constitutes a memory cell together with the capacitor.

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