JP2006337910A - Reticle - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the number of chips laid on a wafer without requiring a new facility in order to reduce a chip unit cost. <P>SOLUTION: A reticle G to transfer a circuit pattern onto a semiconductor wafer has a chip layout F formed in a layout available region E where circuit patterns can be laid by arranging a plurality of minimum unit chips of the circuit pattern, while a space H, I larger than one chip is formed in an area between the outer peripheral edge of the chip layout and the outer peripheral edge of the layout available region. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a glass mask (hereinafter referred to as “reticle”) for transferring a pattern onto a wafer used in a reduction type projection apparatus (hereinafter referred to as “stepper”).

  FIG. 11 is a schematic view of a stepper. The stepper performs reduction projection exposure of a circuit pattern 2 drawn on a reticle 1 onto a wafer 4 through optical means 3. The wafer 4 is held on an XY table 5 that can move in the X direction and a Y direction orthogonal to the X direction.

  Usually, when an integrated circuit (hereinafter referred to as “IC”) is laid out on a reticle, the IC layout (hereinafter referred to as “chip layout”) is set in an area where chip layout can be determined for each reticle. One IC chip (hereinafter referred to as “chip”) is determined to be the maximum number.

  This is to maximize the number of ICs that the stepper can expose at one time (hereinafter referred to as “the number of chips”) and to increase productivity.

  Productivity according to the present invention is productivity in a stepper, and is the number of wafers processed per unit time (hereinafter referred to as “throughput”).

According to the description of Patent Document 1 (Japanese Patent Laid-Open No. 2003-142388), the throughput is as follows.
“Throughput (wph) = 3600 ÷ (wafer supply time + alignment time + exposure processing time + wafer recovery time)”
It is represented by

  Since the wafer supply time, alignment time, and wafer recovery time are unique to the apparatus and can be considered as constants, improvement in throughput is determined by exposure processing time. The exposure processing time depends on the number of drawing (hereinafter referred to as “shot”) and the arrangement of drawing (hereinafter referred to as “shot layout”).

  Here, for convenience of later explanation, a non-shot area (hereinafter referred to as “shot invalid area”) and a focus invalid area on the wafer will be described.

As an explanation of the shot invalid area, for example, when a reticle having a chip layout of 120 mm in the X direction of a plurality of chips is shot with a 5: 1 stepper in the X direction at the center of a 5-inch (= 127 mm) wafer, the following calculation is performed. Consider the formula:
{127 mm- (3 mm × 2)} / (120 mm / 5) = 5 shots + 1 mm
Thus, a 1 mm shot invalid area exists. Assuming that both the area where the wafer chip cannot be taken and the focus invalid area are 3 mm from the wafer periphery.

Next, the focus invalid area will be described.
Normally, in order to shot a reticle pattern on a wafer with a stepper, it is necessary to focus the reticle and the wafer. The focal point is adjusted on the wafer surface with the position (in many cases the reticle center) where the reticle is focused. Therefore, the reticle pattern cannot be shot on the wafer unless the position where the reticle is focused is within the range where the wafer surface is focused. This area that cannot be shot is called a focus invalid area.

  Therefore, in the case of an apparatus for focusing on the reticle center and the wafer surface in the stepper, the shot on the wafer is ineffective area that is half the length of the plurality of chips on the reticle in the X direction or Y direction at the maximum. Can exist.

  In recent years, in the field of semiconductor chip manufacturing, there is an increasing demand for a reduction in chip unit price from the market. For this reason, efforts have been made from various angles such as reducing the IC size (hereinafter referred to as “chip size”) by increasing the diameter of the wafer, reviewing the circuit, and reducing the cost of raw materials.

  However, these efforts often require new capital investment and labor costs, and it took a long time and cost to lower the chip unit price.

For example, in the prior art described in Patent Document 2 (Japanese Patent Laid-Open No. 2003-158067), a reduction in chip acquisition is suppressed by using a stepper masking blade device.
JP 2003-142388 A JP 2003-158067 A

  In the prior art described in Patent Document 2, it is necessary to control the masking blade in the stepper with very high accuracy. However, many of the steppers have a problem that the control accuracy of the masking blade is lower than that of the stage.

  Therefore, an object of the present invention is to increase the number of chips on a wafer without requiring new equipment in order to reduce the unit price of the chip.

  In order to achieve the above object, the present invention has taken the following measures. That is, the present invention is characterized in that, in a reticle for transferring a circuit pattern onto a semiconductor wafer, a plurality of chips each having a minimum unit of the circuit pattern are arranged in a layoutable area where the circuit pattern can be arranged. A layout is formed, and an interval of one chip or more is formed between the outer peripheral edge of the chip layout and the outer peripheral edge of the layable area.

  It is preferable that the outer periphery of the layoutable area and the outer periphery of the chip layout have a quadrangular shape having an X direction side and a Y direction side orthogonal to each other, and the interval is formed in the X or Y direction.

  The wafer is preferably circular or square, and the outer periphery of the chip layout is preferably square.

  The interval is preferably set so as to obtain an optimized chip layout by matching the position where the reticle is focused with the position of the center of the chip layout.

  Alternatively, the interval can be set so as to achieve an optimized chip layout by matching the wafer center with the position on the reticle for focusing.

  According to the present invention configured as described above, the number of chips mounted on the wafer can be increased without requiring new equipment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Since the reticle of the present invention is used in the stepper shown in FIG. 11, reference numeral 1 in the figure corresponds to reference numeral G described below.

  FIG. 1 shows a reticle G according to an embodiment of the present invention. FIG. 6 shows an example of a shot layout on the wafer when the reticle of FIG. 1 is used.

  For comparison, FIG. 5 shows a conventional reticle. FIG. 10 shows an example of a shot layout when a conventional reticle is used.

  In the embodiment of the present invention shown in FIG. 1, a reticle G for transferring a circuit pattern onto a semiconductor wafer has a plurality of chips each having a minimum unit of the circuit pattern arranged in a layoutable area E where the circuit pattern can be arranged. Thus, a chip layout F is formed. Between the outer periphery (thick line in FIG. 1) of the chip layout F (hereinafter also referred to as a chip pattern) and the outer periphery of the layable area E, intervals (tolerances) H and I of one chip or more are formed. ing.

  In the wafer shown in FIG. 6, a portion indicated by a thick line is a one-shot layout and corresponds to the chip layout F on the reticle G. In the figure, C is the center of the reticle, and D is the center position of the wafer.

  In FIG. 1, the outer peripheral edge of the layable area on the reticle G and the outer peripheral edge of the chip layout have a quadrangular shape having X-direction sides and Y-direction sides orthogonal to each other, and the interval is formed in the X or Y direction. ing. That is, in FIG. 1, the tolerance in the X direction is indicated by H, and the tolerance in the Y direction is indicated by I.

  The region E on the reticle G where the chip can be arranged is uniquely determined by the reticle G used by each stepper.

  The reticle G of the above embodiment is laid out with tolerances H and I of one or more chips in the X or Y direction with respect to the region E where the chip pattern F can be laid out. In FIG. 1, as an example, margins for one row in the X direction (indicated by H in FIG. 1) and for three columns in the Y direction (indicated by I in FIG. 1) are set. It may be set arbitrarily. Further, from the viewpoint of productivity, it is preferable that the margin is less if it is one chip or more in the X direction or the Y direction. When giving priority to the cost of the wafer over productivity, the margin is preferably as much as possible, and the setting of placing one chip on the reticle maximizes the number of chips on the wafer.

  As can be seen by comparing FIG. 6 and FIG. 10, in FIG. 6, it can be seen that a shot has been made up to the wafer periphery due to the effect of the present invention.

  As a result, the number of invalid areas that cannot be shot on the wafer is reduced, and the chip layout F on the reticle G can be increased to the maximum number of chips on the area E where the chip layout is possible as in the conventional case. Can do. Therefore, the shot invalid area on the wafer can be reduced and the number of chips can be increased.

The same applies to an apparatus that does not focus on the reticle center in the stepper.
Moreover, since this embodiment does not require new equipment, an increase in manufacturing cost can be suppressed.

  In the above embodiment, the shot layout on the wafer is changed and the number of shots is likely to increase as compared with the conventional example, and in this case, the throughput decreases.

  As an example, in the case of a normal reticle, an example of the throughput of (2) when 85-shot reticle (1) is increased to 87 shots according to the present invention will be given. This calculation quotes what is described in JP2003-142388A below.

The wafer supply time is 5.0 seconds, the alignment time is 10.0 seconds, and the wafer recovery time is 5.0 seconds.
(1) In the case of 85 shots, the exposure processing time is the sum of stage movement time (X-direction movement time × number of movements + Y-direction movement time × number of movements) and exposure time (exposure time per shot × number of shots). Become. In the case of 85 shots, the movement time in the X direction is 0.172 seconds, the number of movements is 75 times, the movement time in the Y direction is 0.18 seconds, the number of movements is 9, and the exposure time per shot is 0. If it is 1 second, the exposure processing time is 23.02 seconds.
“3600 ÷ (5.0 + 10.0 + 23.2 + 5.0) = 83.68 WPH”
It becomes.
(2) In the case of 87 shots Since the number of shots is changed by the same calculation method as in (1), the exposure processing time is calculated with 77 movements in the X direction and 9 movements in the Y direction. 56 seconds. From this result, calculating the throughput,
“3600 ÷ (5.0 + 10.0 + 23.56 + 5.0) = 82.63 WPH”
It becomes.

  Therefore, in this case, the throughput is reduced by about 1.3%, but considering that the number of shots has increased by about 2.4%, the number of shots increases and the number of chips increases by the amount of shots. In this case, the effect of the present invention can be said to be great.

  Therefore, in the chip layout process, the shot layout is determined by arbitrarily setting the margin from the chip layout on the reticle and the effective exposure area on the wafer, and multiple layouts on the reticle are created to select the optimal reticle. It is desirable to use it.

  Specifically, the interval formed between the outer peripheral edge of the chip layout F and the outer peripheral edge of the layable area E is optimized by matching the position where the reticle is focused with the position of the chip layout center. The chip layout is set to be the same.

This optimization is performed by the following procedure.
S1. Create a chip layout to which the present invention is applied.
S2. Create shot layout from chip layout.
S3. Repeat S1 and S2 to create multiple chip layouts.
S4. Determine the optimal chip layout and shot layout.
S5. Throughput is calculated from the number of shots and shot layout.

  FIG. 2 shows a reticle according to another embodiment of the present invention. FIG. 7 shows an example of a shot layout on a wafer using the reticle of FIG. 2 indicates the center position of the chip layout F, and B indicates the center position of the reticle.

  The reticle of this embodiment has a semiconductor manufacturing process for transferring a reticle pattern to a circular or square wafer, and in the reticle chip layout, the sum of the X and Y directions of a plurality of chips is substantially the same. The degree is set. This indicates that the chip layout F on the reticle G is close to a square.

  As shown in FIG. 7, since the wafer is often circular or square, the shot layout on the wafer (thick line in the figure is a one-shot layout) becomes circular or square when the chip layout is close to square. Optimized. As a result, the shot invalid area can be reduced and the number of chips can be increased.

  In this embodiment, in the above-described reticle chip layout, a tolerance is set such that the sum of the X and Y directions of a plurality of chips is substantially the same.

  In FIG. 2, as an example, margins for three columns are set in the Y direction. From the viewpoint of productivity, it is preferable that the margin is less if it is one chip or more in the X direction or the Y direction.

  Regarding the shot layout, compared to the conventional example of FIG. 10, in FIG. 7, the shot layout is close to the wafer shape (circular), and the shot layout is optimized.

  FIG. 3 shows a reticle according to another embodiment of the present invention. FIG. 8 shows an example of a shot layout when the reticle of FIG. 3 is used. As an example, the position of focusing on the reticle is the position of the reticle center. That is, the center position A of the chip layout F and the center position B of the reticle G are matched.

  Thereby, the margin of the chip layout according to the present embodiment is evenly arranged on the chip layout and further on the shot layout, so that the present invention can be used most effectively.

  In this embodiment, the reticle center position (indicated by B in FIGS. 2 and 3) and the chip layout center position (indicated by A in FIGS. 2 and 3) are laid out.

FIG. 3 shows optimization of the chip layout in the reticle of FIG. 2 as an example.
When compared using the shot layouts of FIG. 7 and FIG. 8, it can be seen that the shots have been made more effective and the wafer periphery has been shot.

  4 and 9 show a reticle and shot layout of another embodiment of the present invention. As an example, the position of focusing on the reticle is the position of the reticle center.

  In this embodiment, a shot layout in which the position of focusing on the reticle at the time of shot with the wafer center is optimized.

  Thereby, since an optimal shot layout can be selected, the effect of the present invention can be exhibited in any environment.

  In the embodiment of the present invention, the position of the wafer center (indicated by D in FIGS. 6 and 9) and the position of the reticle center at the time of shot (indicated by C in FIGS. 4, 6, and 9). Optimized layout by adjusting.

  FIG. 9 shows, as an example, a shot layout in which the wafer center position and the reticle center positions C and D in FIG.

  The wafer shown in FIGS. 6 to 9 is manufactured using the reticle shown in FIGS. Compared with the wafer produced by the prior art of FIG. 10, since the shot invalid area is small and the number of chips is large, the chip unit price can be reduced.

  Comparing using the shot layouts of FIG. 6 and FIG. 9, it can be seen that the present invention is more effective, and the shot can be made to the wafer peripheral portion.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention is applicable to the semiconductor device manufacturing industry.

It is a top view of the reticle which shows one Embodiment of this invention. It is a top view of the reticle which shows one Embodiment of this invention. It is a top view of the reticle which shows one Embodiment of this invention. It is a top view of the reticle which shows one Embodiment of this invention. It is a top view of the conventional reticle. It is a top view which shows an example of the shot layout using the reticle of FIG. FIG. 3 is a plan view showing an example of a shot layout using the reticle of FIG. 2. It is a top view which shows an example of the shot layout using the reticle of FIG. FIG. 5 is a plan view showing an example of a shot layout using the reticle of FIG. 4. It is a top view which shows an example of the shot layout using the conventional reticle of FIG. It is the schematic of a stepper.

Explanation of symbols

  A Chip layout center position, B Reticle center position, C Chip center position, D Wafer center position, E Reticle chip layout area, F Reticle chip pattern, G reticle, H Reticle chip layout area X direction Tolerance, I Y direction tolerance of the chip layout possible area on the reticle.

Claims (5)

In a reticle for transferring a circuit pattern onto a semiconductor wafer,
A chip layout is formed by arranging a plurality of chips of the minimum unit of the circuit pattern in the layout possible area where the circuit pattern can be arranged,
A reticle having an interval of one chip or more is formed between an outer peripheral edge of the chip layout and an outer peripheral edge of the layable area.   The layoutable region outer periphery and the chip layout outer periphery have a quadrangular shape having an X direction side and a Y direction side orthogonal to each other, and the interval is formed in the X or Y direction. Item 14. The reticle according to Item 1.   3. The reticle according to claim 1, wherein the wafer is circular or square, and the outer periphery of the chip layout is square.   The interval is set so as to obtain an optimized chip layout by matching a position where the reticle is focused and a position of the center of the chip layout. The described reticle.   4. The interval is set so as to achieve an optimized chip layout by matching a wafer center with a focus position on a reticle when shot. The reticle described in 1.

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