JP2006324265A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2006324265A
JP2006324265A JP2005143347A JP2005143347A JP2006324265A JP 2006324265 A JP2006324265 A JP 2006324265A JP 2005143347 A JP2005143347 A JP 2005143347A JP 2005143347 A JP2005143347 A JP 2005143347A JP 2006324265 A JP2006324265 A JP 2006324265A
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interlayer insulating
insulating film
conductive layer
layer wiring
pad
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Shigeru Oki
滋 大木
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To improve crack resistance against a shock that a part just below a pad undergoes by a semiconductor assembly process. <P>SOLUTION: A plurality of conductive layer wiring metals 3 and interlayer insulating films 2 and 4 are alternately laminated just below a pad 7. The upper and lower conductive layer wiring metals 3 arranged across the interlayer insulating films 2 and 4 are connected through vias 5 and 15. The via 15 formed in the upper interlayer insulating film of an interface where a material of the interlayer insulating film changes is thickly arranged, and it becomes strong to stress in a shear direction on the interlayer insulating film. Thus, crack resistance of the conductive layer wiring metal and the interlayer insulating film against the shock of a wire bond and a probe, and damage resistance when a transistor is formed just below the pad can be improved. The insulating film with low mechanical strength can be adopted to the interlayer insulating film by easing stress just below the pad as a pad structure. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明は、パッド直下に導電層配線メタルが層間絶縁膜を挟んで複数層形成された半導体装置に関するものである。   The present invention relates to a semiconductor device in which a plurality of conductive layer wiring metals are formed directly below a pad with an interlayer insulating film interposed therebetween.

近年、情報技術の広がりとともにコンピューター、携帯電話など電子機器の能力として高速化の要求は高まっている。それに伴い、電子機器の性能に大きく影響するシステムＬＳＩに代表される半導体装置の性能として、更なる高速化が必然的に求められている。しかし、半導体装置の高速化に大きな妨げになるのが、ＭＯＳトランジスタ自体の遅延とその上層にある配線遅延である。従来は、ゲート長を短くする微細化技術によりＭＯＳトランジスタ自体の遅延を低減してきた。しかしながら、微細化技術の進展によるＭＯＳトランジスタ自体の遅延が小さくなるに従い配線遅延の問題が顕著になってきた。そこで、配線間遅延を小さくするため配線間に挟まれている絶縁膜に誘電率の低い絶縁膜（低誘電率膜）を採用しようとしている。   In recent years, with the spread of information technology, there is an increasing demand for higher speed as the capability of electronic devices such as computers and mobile phones. Along with this, a further increase in speed is inevitable as a performance of a semiconductor device represented by a system LSI that greatly affects the performance of an electronic device. However, it is the delay of the MOS transistor itself and the wiring delay above it that greatly hinders the speeding up of the semiconductor device. Conventionally, the delay of the MOS transistor itself has been reduced by a miniaturization technique for shortening the gate length. However, the problem of wiring delay has become more prominent as the delay of the MOS transistor itself due to the progress of miniaturization technology becomes smaller. Therefore, in order to reduce the delay between wirings, an insulating film (low dielectric constant film) having a low dielectric constant is being adopted as the insulating film sandwiched between the wirings.

しかしながら、誘電率が３．０以下を実現する低誘電率膜は、従来から採用されていたシリコン酸化膜よりも機械的強度が大きく低下する。これは、半導体装置の回路形成を担う拡散工程が完了した後の半導体装置のパッケージングを担う組み立て工程で問題となる。具体的には次のようなことである。層間絶縁膜の機械的強度が十分でないため半導体装置に搭載されているパッド上にワイヤボンドを行うと、ワイヤボンドの衝撃荷重がパッドを通じてパッド直下の層間絶縁膜に伝わり、それが層間絶縁膜を大きく変形させる。その変形が層間絶縁膜にクラックを発生させ、パッド剥がれや層間はく離による信頼性不良の原因となる。さらに、近年は、半導体素子の寸法を縮小してコストを低減することを目的に、トランジスタ上にパッドを設置した半導体素子が開発されている。このとき、配線間及び層間絶縁膜に機械的強度の低い低誘電率膜を用いると、ワイヤボンドの衝撃により低誘電率膜が変形し、トランジスタに衝撃が伝わりやすくなることでトランジスタへダメージを与えてしまい品質不良を引き起こしてしまう。   However, a low dielectric constant film that achieves a dielectric constant of 3.0 or less has a mechanical strength that is significantly lower than that of a silicon oxide film that has been conventionally employed. This becomes a problem in an assembly process for packaging a semiconductor device after a diffusion process for forming a circuit of the semiconductor device is completed. Specifically, this is as follows. Since the mechanical strength of the interlayer insulating film is not sufficient, when wire bonding is performed on a pad mounted on a semiconductor device, the impact load of the wire bond is transmitted to the interlayer insulating film immediately below the pad through the pad, which causes the interlayer insulating film to pass through. Deform it greatly. The deformation causes a crack in the interlayer insulating film, and causes a reliability failure due to peeling of the pad or peeling of the interlayer. Furthermore, in recent years, a semiconductor element in which a pad is provided on a transistor has been developed for the purpose of reducing the cost by reducing the size of the semiconductor element. At this time, if a low dielectric constant film having low mechanical strength is used between the wirings and the interlayer insulating film, the low dielectric constant film is deformed by the impact of wire bonding, and the transistor is damaged by being easily transmitted to the transistor. Will cause quality defects.

そこで、図５の従来の半導体装置におけるパッド周辺部の構造を説明する断面図に示すように、従来は、パッド（外部端子）７直下に、層間絶縁膜４を挟んで複数の導電層配線メタル３を形成し、その導電層配線メタル３間をビア５で接続することで、ワイヤボンドにより層間絶縁膜４へ与えられる衝撃をメタル３が受け止め、さらに衝撃でメタル３が衝撃の印加方向へ変形しようとするのをビア５が支えるようになり、パッド７直下に成膜された層間絶縁膜４の機械的強度を補うようなパッド構造を形成している（例えば、特許文献１）。その結果、ワイヤボンドによるトランジスタへのダメージが抑制できる。   Therefore, as shown in a cross-sectional view illustrating the structure of the pad periphery in the conventional semiconductor device of FIG. 5, conventionally, a plurality of conductive layer wiring metals are sandwiched immediately below the pad (external terminal) 7 with the interlayer insulating film 4 interposed therebetween. 3 and the conductive layer wiring metal 3 are connected by vias 5 so that the metal 3 receives the impact applied to the interlayer insulating film 4 by wire bonding, and the metal 3 is deformed in the direction of the impact by the impact. The via 5 supports the attempt, and a pad structure is formed so as to supplement the mechanical strength of the interlayer insulating film 4 formed immediately below the pad 7 (for example, Patent Document 1). As a result, damage to the transistor due to wire bonding can be suppressed.

ここで、従来は図５に示すように機械的強度の低い層間絶縁膜２は、配線密度の高いファイン層１でのみ使われ、比較的配線密度の低いセミファイン層８では、比較的機械的強度が高い層間絶縁膜４が使われる。これにより、メタル直下の衝撃は、比較的強度の高いセミファイン層８で軽減することで全体の機械的強度を保っている。また、ファイン層１で使われるビア５の形状は、どれも同じで、特に機械的強度に関する考慮がされていない。
特開２０００−１１４３０９号公報 Here, as shown in FIG. 5, the interlayer insulating film 2 having a low mechanical strength is conventionally used only in the fine layer 1 having a high wiring density, and the semi-fine layer 8 having a relatively low wiring density is relatively mechanical. The interlayer insulating film 4 having high strength is used. Thereby, the impact directly under the metal is reduced by the semi-fine layer 8 having a relatively high strength, thereby maintaining the overall mechanical strength. In addition, the vias 5 used in the fine layer 1 have the same shape, and no special consideration is given to mechanical strength.
JP 2000-114309 A

しかしながら、上記のパッド構造では下記のような問題がある。
図６に示すパッド直下の層間絶縁膜界面の応力を説明する図において、配線密度が高く配線ルールの細かいファイン層１と比較的配線密度が低く、配線ルールが太くなるセミファイン層８では層間絶縁膜（４と２）として異なる材料が使われる。それは、配線密度が高いほど低誘電率の層間絶縁膜２を利用しないと電気的特性（電気的結合によるノイズ）を維持できないためである。しかし、異種材料を層間絶縁膜に利用することで、組み立て時のさまざまな方向からかかる応力に対し、材料固有の特性をもつ剛性（ヤング率）や線膨張係数の違いで層間絶縁膜２と層間絶縁膜４の界面９につよい応力がせん断方向に発生する。図６のように金バンプ１１接合時に荷重１０と超音波（振動）１２をかけると界面９の波線で描かれた部分に応力が集中し、層間絶縁膜２と層間絶縁膜４間での亀裂・破壊発生の原因となる。従来のビア構成では、ファイン層１では、同じ径のビア５を構成しているため、亀裂・破壊箇所が等しく、機械的強度を考慮したビア構成となっていない課題が露呈している。 However, the above pad structure has the following problems.
In the diagram for explaining the stress at the interface of the interlayer insulating film immediately below the pad shown in FIG. 6, the interlayer insulation is used in the fine layer 1 having a high wiring density and a fine wiring rule and the semi-fine layer 8 having a relatively low wiring density and a thick wiring rule. Different materials are used for the membranes (4 and 2). This is because the electrical characteristics (noise due to electrical coupling) cannot be maintained unless the interlayer insulating film 2 having a low dielectric constant is used as the wiring density increases. However, by using different materials for the interlayer insulating film, the interlayer insulating film 2 and the interlayer are different due to differences in rigidity (Young's modulus) and linear expansion coefficient that are characteristic of the material against stress applied from various directions during assembly. A strong stress is generated in the shear direction at the interface 9 of the insulating film 4. As shown in FIG. 6, when a load 10 and ultrasonic waves (vibration) 12 are applied at the time of bonding the gold bump 11, stress concentrates on the portion drawn by the wavy line of the interface 9, and a crack is generated between the interlayer insulating film 2 and the interlayer insulating film 4.・ It may cause destruction. In the conventional via configuration, since the fine layer 1 includes the vias 5 having the same diameter, there is a problem that cracks and breakage portions are equal and the via configuration considering the mechanical strength is not provided.

図３は、パッド直下の応力分布を測定した結果を示す図であり、２種類の層間絶縁膜（４と２）を用い、ファイン層１とセミファイン層８からなる層構成を有する半導体装置の組み立て時の応力計算（ＦＥＭ）を行った時の層間絶縁膜での応力分布を示したものである。１３が具体的な応力値を示している。単位は圧力値（Ｐａ）を示している。領域１４の部分に応力が集中しており、これは層間絶縁膜が変化している前後であることが理解でき、物理解析で破壊を特定した箇所と一致している。従って、層間絶縁膜でのビア構成は、応力分布を考慮し、構成する必要が存在する。   FIG. 3 is a diagram showing the result of measuring the stress distribution directly under the pad. A semiconductor device having a layer structure composed of a fine layer 1 and a semi-fine layer 8 using two types of interlayer insulating films (4 and 2). The stress distribution in the interlayer insulating film when the stress calculation (FEM) at the time of assembly is performed is shown. Reference numeral 13 denotes a specific stress value. The unit indicates a pressure value (Pa). It can be understood that the stress is concentrated in the region 14, which is before and after the change of the interlayer insulating film, and is consistent with the location where the breakdown is specified by physical analysis. Therefore, it is necessary to configure the via configuration in the interlayer insulating film in consideration of the stress distribution.

したがって、この発明の目的は、上記従来の課題を解決するもので、半導体組み立てプロセスの工程において、パッド直下が受ける衝撃、すなわちパッド直下の層間絶縁膜およびトランジスタ等に対しワイヤボンドや封止時によるダメージを防止し、耐クラック性を向上させることである。   Therefore, the object of the present invention is to solve the above-mentioned conventional problems, and in the process of the semiconductor assembly process, the impact received directly under the pad, that is, the time when wire bonding or sealing is performed on the interlayer insulating film and transistor, etc. immediately below the pad. It is to prevent damage and improve crack resistance.

上記目的を達成するために、この発明の請求項１記載の半導体装置は、パッド直下に導電層配線メタルと層間絶縁膜が交互に複数積層され、前記層間絶縁膜を挟んで隣り合う導電層配線メタルがビアを介して接続され、前記積層された層が層間絶縁膜の材料が異なる複数のファイン層に分割され、前記材料の異なる層間絶縁膜間の界面の上層に形成された層間絶縁膜に形成されたビアの径が他のビアの径より太いことを特徴とする。   In order to achieve the above object, according to a first aspect of the present invention, a plurality of conductive layer wiring metals and interlayer insulating films are alternately stacked immediately below a pad, and adjacent conductive layer wirings sandwiching the interlayer insulating film. Metal is connected through vias, and the stacked layer is divided into a plurality of fine layers made of different materials for the interlayer insulating film, and the interlayer insulating film formed on the interface between the interlayer insulating films of different materials The diameter of the formed via is larger than the diameter of other vias.

請求項２記載の半導体装置は、パッド直下に導電層配線メタルと層間絶縁膜が交互に複数積層され、前記層間絶縁膜を挟んで隣り合う導電層配線メタルがビアを介して接続され、前記積層された層が層間絶縁膜の材料が異なる複数のファイン層に分割され、前記材料の異なる層間絶縁膜間の界面の上層に形成された層間絶縁膜に形成されたビア断面のアスペクト比が２．０以上であることを特徴とする。   3. The semiconductor device according to claim 2, wherein a plurality of conductive layer wiring metals and interlayer insulating films are alternately stacked immediately below the pads, and adjacent conductive layer wiring metals are connected via vias, with the interlayer insulating film interposed therebetween. The formed layer is divided into a plurality of fine layers having different materials for the interlayer insulating film, and the aspect ratio of the cross section of the via formed in the interlayer insulating film formed in the upper layer of the interface between the interlayer insulating films of different materials is 2. It is 0 or more.

請求項３記載の半導体装置は、パッド直下に導電層配線メタルと層間絶縁膜が交互に複数積層され、前記層間絶縁膜を挟んで隣り合う導電層配線メタルがビアを介して接続され、前記積層された層が層間絶縁膜の材料が異なる複数のファイン層に分割され、前記材料の異なる層間絶縁膜間の界面の上層に形成された層間絶縁膜に複数のビアを形成して合計の断面積を他のビアの断面積より大きくすることを特徴とする。   The semiconductor device according to claim 3, wherein a plurality of conductive layer wiring metals and interlayer insulating films are alternately stacked immediately below the pads, and adjacent conductive layer wiring metals are connected via vias, with the interlayer insulating film interposed therebetween. The divided layer is divided into a plurality of fine layers made of different materials for the interlayer insulation film, and a plurality of vias are formed in the interlayer insulation film formed on the upper layer of the interface between the interlayer insulation films made of the different materials. Is larger than the cross-sectional area of other vias.

請求項４記載の半導体装置は、パッド直下に導電層配線メタルと様々な厚みの層間絶縁膜が交互に複数積層され、前記層間絶縁膜を挟んで隣り合う導電層配線メタルがビアを介して接続され、最も厚みの薄い層間絶縁膜間の上下の層に形成された層間絶縁膜に形成されたビアの径が他のビアの径より太いことを特徴とする。   5. The semiconductor device according to claim 4, wherein a plurality of conductive layer wiring metals and interlayer insulating films of various thicknesses are alternately stacked immediately below the pads, and adjacent conductive layer wiring metals are connected via vias with the interlayer insulating film interposed therebetween. In addition, the diameter of the via formed in the interlayer insulating film formed in the upper and lower layers between the thinnest interlayer insulating films is larger than the diameters of the other vias.

請求項５記載の半導体装置は、パッド直下に導電層配線メタルと様々な厚みの層間絶縁膜が交互に複数積層され、前記層間絶縁膜を挟んで隣り合う導電層配線メタルがビアを介して接続され、最も厚みの薄い層間絶縁膜間の上下の層に形成された層間絶縁膜に形成されたビア断面のアスペクト比が２．０以上であることを特徴とする。   6. The semiconductor device according to claim 5, wherein a plurality of conductive layer wiring metals and interlayer insulating films of various thicknesses are alternately stacked immediately below the pads, and adjacent conductive layer wiring metals are connected via vias with the interlayer insulating film interposed therebetween. The aspect ratio of the via cross section formed in the interlayer insulating film formed in the upper and lower layers between the thinnest interlayer insulating films is 2.0 or more.

請求項６記載の半導体装置は、パッド直下に導電層配線メタルと様々な厚みの層間絶縁膜が交互に複数積層され、前記層間絶縁膜を挟んで隣り合う導電層配線メタルがビアを介して接続され、最も厚みの薄い層間絶縁膜間の上下の層に形成された層間絶縁膜に複数のビアを形成して合計の断面積を他のビアの断面積より大きくすることを特徴とする。   7. The semiconductor device according to claim 6, wherein a plurality of conductive layer wiring metals and interlayer insulating films of various thicknesses are alternately stacked immediately below the pads, and adjacent conductive layer wiring metals are connected via vias with the interlayer insulating film interposed therebetween. A plurality of vias are formed in the interlayer insulating films formed in the upper and lower layers between the thinnest interlayer insulating films, and the total cross-sectional area is made larger than the cross-sectional areas of the other vias.

請求項７記載の半導体装置は、請求項１または請求項２または請求項３または請求項４または請求項５または請求項６のいずれかに記載の半導体装置において、前記導電層配線メタルは銅からなり、前記パッドはアルミニウムからなることを特徴とする。   The semiconductor device according to claim 7 is the semiconductor device according to claim 1, claim 2, claim 3, claim 4, claim 5, or claim 6, wherein the conductive layer wiring metal is made of copper. The pad is made of aluminum.

請求項８記載の半導体装置は、請求項１または請求項２または請求項３または請求項４または請求項５または請求項６のいずれかに記載の半導体装置において、前記層間絶縁膜は、低誘電材料からなることを特徴とする。   The semiconductor device according to claim 8 is the semiconductor device according to claim 1, claim 2, claim 3, claim 4, claim 5, or claim 6, wherein the interlayer insulating film has a low dielectric constant. It is made of a material.

以上により、半導体組み立てプロセスの工程において、パッド直下が受ける衝撃、すなわちパッド直下の層間絶縁膜およびトランジスタ等に対しワイヤボンドや封止時によるダメージを防止し、耐クラック性を向上させることができる。   As described above, in the process of the semiconductor assembly process, the impact received immediately below the pad, that is, damage to the interlayer insulating film and transistor immediately below the pad due to wire bonding or sealing can be prevented, and crack resistance can be improved.

以上のように、外部接続電極直下に導電層配線メタルと層間絶縁膜が交互に複数積層され、層間絶縁膜を挟んで配置された上下の導電層配線メタルがビアを介して接続され、かつ層間絶縁膜の材料が変化する上の層間絶縁膜のビアを太く配置することにより、層間絶縁膜にかかるせん断方向の応力に対して強くなる。従って、組み立て時のワイヤボンドやプローブの衝撃に対し配線及び層間絶縁膜の耐クラック性と、パッド直下にトランジスタが形成される場合にはその耐ダメージ性の向上を図ることができる。また、パッド構造としてパッド直下の応力を緩和することにより層間絶縁膜には機械的強度が低い絶縁膜を採用できる。すなわち、配線間遅延を小さくするため、配線間に挟まれている絶縁膜に機械的強度が低い低誘電率膜を採用することができ、低誘電率膜の塑性変形またはクラック発生を防ぐため、ビアの径を太くすることで、構造上強化可能となる。これは建物における柱を太くすることで耐震性を向上させるのと同様の効果を持つ。   As described above, a plurality of conductive layer wiring metals and interlayer insulating films are alternately stacked directly under the external connection electrodes, and the upper and lower conductive layer wiring metals arranged with the interlayer insulating film interposed therebetween are connected via vias, and the interlayer By thickly arranging the vias of the upper interlayer insulating film where the material of the insulating film changes, it becomes stronger against the stress in the shear direction applied to the interlayer insulating film. Therefore, it is possible to improve the crack resistance of the wiring and the interlayer insulating film against the impact of the wire bond and the probe during assembly, and the damage resistance when the transistor is formed directly under the pad. In addition, an insulating film having low mechanical strength can be adopted as the interlayer insulating film by relaxing the stress directly under the pad as the pad structure. That is, in order to reduce the delay between the wirings, it is possible to employ a low dielectric constant film having a low mechanical strength for the insulating film sandwiched between the wirings, in order to prevent plastic deformation or crack occurrence of the low dielectric constant film, By increasing the via diameter, the structure can be strengthened. This has the same effect as improving the earthquake resistance by thickening the pillars in the building.

この発明の実施の形態１を図１，図３，図４に基づいて説明する。
図１は実施の形態１の半導体装置におけるパッド周辺部の構造を説明する断面図であり、図１（ａ）はパッド周辺部の半導体装置の積層構造を示す断面図、図１（ｂ）は図１（ａ）のＡ−Ａ’部分の平面構造を表す断面図である。 A first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a cross-sectional view illustrating the structure of a pad peripheral portion in the semiconductor device of the first embodiment. FIG. 1A is a cross-sectional view illustrating a stacked structure of the semiconductor device in the pad peripheral portion, and FIG. It is sectional drawing showing the planar structure of the AA 'part of Fig.1 (a).

図１において、１はファイン層、２は層間絶縁膜、３は導電層配線メタル、４は層間絶縁膜、５，１５はビア、６は保護膜、７は最上層メタルからなるパッド（外部接続電極）、８はセミファイン層を示す。   In FIG. 1, 1 is a fine layer, 2 is an interlayer insulating film, 3 is a conductive layer wiring metal, 4 is an interlayer insulating film, 5 and 15 are vias, 6 is a protective film, and 7 is a pad made of the uppermost metal (external connection). Electrode), 8 represents a semi-fine layer.

図１に示すとおり、パッド７直下に導電層配線メタル３と層間絶縁膜４が交互に複数積層され、層間絶縁膜４を挟んで配置された上下の導電層配線メタル３がビア５を介して接続され、特に層間絶縁膜が２種類の材料（２と４）から構成され、材料が変化する直前のビア１５が特に太く構成されていることを特徴とする。   As shown in FIG. 1, a plurality of conductive layer wiring metals 3 and interlayer insulating films 4 are alternately stacked immediately below the pad 7, and the upper and lower conductive layer wiring metals 3 arranged with the interlayer insulating film 4 interposed therebetween via vias 5. In particular, the interlayer insulating film is composed of two kinds of materials (2 and 4), and the via 15 immediately before the material changes is particularly thick.

ここで、導電層配線メタル３は銅からなり、パッド７はアルミニウムからなることが、組み立て時の外部配線（例えばワイヤボンド等）との接合強度を高めるために望ましい。また、層間絶縁膜２，層間絶縁膜４は、材質の異なる層間絶縁膜から構成されている。   Here, it is desirable that the conductive layer wiring metal 3 is made of copper and the pad 7 is made of aluminum in order to increase the bonding strength with an external wiring (for example, a wire bond) during assembly. The interlayer insulating film 2 and the interlayer insulating film 4 are composed of interlayer insulating films made of different materials.

この場合、パッド構造は、配線間絶縁膜２、配線間絶縁膜４に埋め込まれた複数の導電層配線メタル３をビア５またはビア１５で接続したものである。このパッド構造において、ワイヤボンドやプローブの衝撃がパッド７と最上層の導電層配線メタル３を通して層間絶縁膜２、層間絶縁膜４に伝わるが、層間絶縁膜の材料が変化する境界の上層の層間絶縁膜に形成されたビア１５において、ビア径を他のビア５と比べて特に太くすることで、層間絶縁膜２、層間絶縁膜４間に集中する応力に対する剛性を増すことができる。つまり、ビア構造が一定の径であると層間絶縁膜２，層間絶縁膜４の剛性（ヤング率）や線膨張係数差でせん断方向に大きな応力が発生し、亀裂／破棄の原因となるが、例え、層間絶縁膜に剛性の低い低誘電材料を用いたとしても、応力が集中する領域である異なる材料で形成された層間絶縁膜の境界上層の層間絶縁膜に形成されたビア１５の径を太くすることにより集中する応力を緩和することができる。ビア径を太くすることは、家屋において柱を太くすることと同様な効果で、せん断方向に対する応力に強く、耐クラック性を向上させる。   In this case, the pad structure is a structure in which a plurality of conductive layer wiring metals 3 embedded in the inter-wiring insulating film 2 and the inter-wiring insulating film 4 are connected by vias 5 or vias 15. In this pad structure, the impact of the wire bond or the probe is transmitted to the interlayer insulating film 2 and the interlayer insulating film 4 through the pad 7 and the uppermost conductive layer wiring metal 3, but the upper layer of the boundary where the material of the interlayer insulating film changes. In the via 15 formed in the insulating film, by making the via diameter particularly thick compared to the other vias 5, rigidity against stress concentrated between the interlayer insulating film 2 and the interlayer insulating film 4 can be increased. In other words, if the via structure has a constant diameter, a large stress is generated in the shear direction due to the difference in rigidity (Young's modulus) and the linear expansion coefficient of the interlayer insulating film 2 and the interlayer insulating film 4, which causes cracking / discarding. For example, even if a low dielectric material with low rigidity is used for the interlayer insulating film, the diameter of the via 15 formed in the interlayer insulating film on the upper boundary of the interlayer insulating film formed of a different material, which is a region where stress is concentrated, By increasing the thickness, the concentrated stress can be relaxed. Increasing the via diameter is the same effect as increasing the thickness of the pillar in the house, and is resistant to stress in the shear direction and improves crack resistance.

図４はビア径と層間絶縁膜に集中する応力の関係を示す図であり、ビア径と層間絶縁膜に集中する応力の関係を表わした計算結果である。これによりビア径を太く、例えばアスペクト比を高めることで応力が緩和できることを理解できる。   FIG. 4 is a diagram showing the relationship between the via diameter and the stress concentrated on the interlayer insulating film, and is a calculation result showing the relationship between the via diameter and the stress concentrated on the interlayer insulating film. Thus, it can be understood that the stress can be relieved by increasing the via diameter, for example, by increasing the aspect ratio.

図４は、図３と同じく２種類の層間絶縁膜からなる層構成に対する計算結果であり、層間絶縁膜での材料が変化する直前の層のビア径を変化させた時のＦＥＭでの計算結果である。ビア径のアスペクト比（横寸法／縦寸法）を０．６７から２．０にすることで、層間絶縁膜に集中する応力値を２０％削減可能なことが計算結果から推測される。ビア径のアスペクト比を２．０以上にする根拠として、層間絶縁膜での破壊強度に起因する。特に脆弱な層間絶縁膜では、剛性（ヤング率）４ＧＰａとなり、従来のＳｉＯ２に比較して半分程度の剛性であり、降伏応力は、約その１／１０程度である。これより、降伏応力４００ＭＰａと推定するとアスペクト比が２．０以上必要となる。 FIG. 4 shows the calculation results for the layer structure composed of two types of interlayer insulating films as in FIG. 3, and the FEM calculation results when the via diameter of the layer just before the material change in the interlayer insulating film is changed. It is. From the calculation results, it is estimated that the stress value concentrated on the interlayer insulating film can be reduced by 20% by changing the aspect ratio of the via diameter (horizontal dimension / vertical dimension) from 0.67 to 2.0. The reason why the aspect ratio of the via diameter is 2.0 or more is due to the breakdown strength in the interlayer insulating film. In particular, a weak interlayer insulating film has a rigidity (Young's modulus) of 4 GPa, about half that of conventional SiO 2 , and a yield stress of about 1/10. From this, when it is estimated that the yield stress is 400 MPa, the aspect ratio is 2.0 or more.

以上のように本実施の形態によれば、ワイヤボンドやプローブの組み立て時の衝撃によりパッド直下の配線間及び層間の絶縁膜に採用される低誘電率膜の塑性変形またはクラック発生を防ぐため、パッド直下に導電層配線メタルと層間絶縁膜が交互に複数積層され、層間絶縁膜を挟んで配置された上下の導電層配線メタルがビアを介して接続され、かつ層間絶縁膜の材料が変化する上の層間絶縁膜のビアを太く配置することにより、層間絶縁膜にかかるせん断方向の応力に対する剛性を確保できる。このパッド構造を有することにより、ワイヤボンドやプローブの衝撃に対し、柱効果でビアにかかる応力を緩和する。その結果、パッド直下の層間絶縁膜、つまり低誘電率膜に伝わるワイヤボンドやプローブの衝撃は抑えられ低誘電率膜の塑性変形及びクラックを防ぐことができる。   As described above, according to this embodiment, in order to prevent plastic deformation or crack generation of the low dielectric constant film employed in the insulating film between the wirings immediately below the pads and between the layers due to the impact at the time of assembling the wire bond or the probe, A plurality of conductive layer wiring metals and interlayer insulating films are alternately stacked directly under the pad, and the upper and lower conductive layer wiring metals arranged across the interlayer insulating film are connected via vias, and the material of the interlayer insulating film changes. By arranging a thick via in the upper interlayer insulating film, it is possible to ensure rigidity against stress in the shear direction applied to the interlayer insulating film. By having this pad structure, the stress applied to the via is relieved by the column effect against the impact of a wire bond or a probe. As a result, the impact of the wire bond and the probe transmitted to the interlayer insulating film immediately below the pad, that is, the low dielectric constant film can be suppressed, and plastic deformation and cracking of the low dielectric constant film can be prevented.

ここでは、ビア１５の径をビア５に比べて太くする場合について説明したが、ビア径にかかわらず、応力が集中する領域である異なる材料で形成された層間絶縁膜の境界上層の層間絶縁膜に形成されたビア１５の数を増やすことにより、同様の効果を奏することができる。つまり、ビア径は同じサイズであるが、ビア面積率を高くすることで、ビア径を太くすることと同様の効果をもたらすことができる。   Here, the case where the diameter of the via 15 is made larger than that of the via 5 has been described. However, regardless of the via diameter, the interlayer insulating film on the boundary layer of the interlayer insulating film formed of a different material which is a region where stress is concentrated. By increasing the number of vias 15 formed in the same manner, the same effect can be obtained. That is, although the via diameter is the same size, increasing the via area ratio can provide the same effect as increasing the via diameter.

図２は実施の形態２の半導体装置におけるパッド周辺部の構造を説明する断面図であり、図２（ａ）はパッド周辺部の半導体装置の積層構造を示す断面図、図２（ｂ）は図２（ａ）のＡ−Ａ’部分の平面構造を表す断面図である。   2 is a cross-sectional view illustrating the structure of the pad peripheral portion in the semiconductor device of the second embodiment. FIG. 2A is a cross-sectional view illustrating the stacked structure of the semiconductor device in the pad peripheral portion, and FIG. It is sectional drawing showing the planar structure of the AA 'part of Fig.2 (a).

図２において、２は層間絶縁膜、３は導電層配線メタル、５，１５はビア、６は保護膜、７は最上層導電層配線メタルからなるパッド（外部接続電極）を示す。
図２に示すとおり、パッド７直下に導電層配線メタル３と層間絶縁膜４が交互に複数積層され、層間絶縁膜４を挟んで配置された上下の導電層配線メタル３がビアを介して接続され、特に、層間絶縁膜の厚みが変化する上下層のビア１５が特に太く構成されていることを特徴とする。 In FIG. 2, 2 is an interlayer insulating film, 3 is a conductive layer wiring metal, 5 and 15 are vias, 6 is a protective film, and 7 is a pad (external connection electrode) made of the uppermost conductive layer wiring metal.
As shown in FIG. 2, a plurality of conductive layer wiring metals 3 and interlayer insulating films 4 are alternately stacked immediately below the pad 7, and the upper and lower conductive layer wiring metals 3 arranged with the interlayer insulating film 4 interposed therebetween are connected via vias. In particular, the upper and lower vias 15 in which the thickness of the interlayer insulating film varies are particularly thick.

ここで、導電層配線メタル３は銅からなり、パッド７はアルミニウムからなることが、組み立て時の外部配線（例えばワイヤボンド等）との接合強度を高めるために望ましい。
図２に示すように、層間絶縁膜での厚みが変化する界面でも、実施の形態１における材料の変化する界面と同様に層間絶縁膜に集中する応力が高くなり、その間の層間絶縁膜で亀裂／破壊が起りやすい。これにおいても、実施の形態１と同様に層間絶縁膜の変化する上下層の層間絶縁膜に形成されたビア径を太くすることで、例え、層間絶縁膜に剛性の低い低誘電材料を用いたとしても、層間絶縁膜での亀裂／破壊を防止する。 Here, it is desirable that the conductive layer wiring metal 3 is made of copper and the pad 7 is made of aluminum in order to increase the bonding strength with an external wiring (for example, a wire bond) during assembly.
As shown in FIG. 2, even at the interface where the thickness of the interlayer insulating film changes, the stress concentrated on the interlayer insulating film is increased similarly to the interface where the material changes in the first embodiment. / Prone to destruction. In this case as well, for example, a low dielectric material having low rigidity is used for the interlayer insulating film by increasing the diameter of the via formed in the upper and lower interlayer insulating films where the interlayer insulating film changes as in the first embodiment. However, it prevents cracks / breakage in the interlayer insulating film.

実施の形態２の構成においても実施の形態１と同様に、アスペクト比を２．０以上に高くすることで、同様の効果をもたらすものである。同じく、複数のビアを形成することもできる。   Also in the configuration of the second embodiment, as in the first embodiment, the same effect is brought about by increasing the aspect ratio to 2.0 or more. Similarly, a plurality of vias can be formed.

本発明は、半導体組み立てプロセスの工程において、パッド直下が受ける衝撃、すなわちパッド直下の層間絶縁膜およびトランジスタ等に対しワイヤボンドや封止時によるダメージを防止し、耐クラック性を向上させることができ、パッド直下に導電層配線メタルが層間絶縁膜を挟んで複数層形成された半導体装置等に有用である。   The present invention can improve the resistance to cracks by preventing the impact received directly under the pad in the process of the semiconductor assembly process, that is, damage to the interlayer insulating film and transistor immediately below the pad due to wire bonding or sealing. It is useful for a semiconductor device or the like in which a plurality of conductive layer wiring metals are formed directly below the pad with an interlayer insulating film interposed therebetween.

実施の形態１の半導体装置におけるパッド周辺部の構造を説明する断面図Sectional drawing explaining the structure of the pad periphery part in the semiconductor device of Embodiment 1 実施の形態２の半導体装置におけるパッド周辺部の構造を説明する断面図Sectional drawing explaining the structure of the pad periphery part in the semiconductor device of Embodiment 2 パッド直下の応力分布を測定した結果を示す図The figure which shows the result of measuring the stress distribution right under the pad ビア径と層間絶縁膜に集中する応力の関係を示す図Diagram showing the relationship between via diameter and stress concentrated on interlayer insulation film 従来の半導体装置におけるパッド周辺部の構造を説明する断面図Sectional drawing explaining the structure of the pad peripheral part in the conventional semiconductor device パッド直下の層間絶縁膜界面の応力を説明する図Diagram explaining the stress at the interface of the interlayer insulating film directly under the pad

符号の説明Explanation of symbols

１ ファイン層
２ 層間絶縁膜
３ メタル
４ 層間絶縁膜
５ ビア
６ 保護膜
７ パッド
８ セミファイン層
９ 部分
１０ 荷重
１１ 金バンプ
１２ 超音波振動
１３ 圧力値
１４ 領域
１５ ビア DESCRIPTION OF SYMBOLS 1 Fine layer 2 Interlayer insulating film 3 Metal 4 Interlayer insulating film 5 Via 6 Protective film 7 Pad 8 Semi fine layer 9 Part 10 Load 11 Gold bump 12 Ultrasonic vibration 13 Pressure value 14 Area 15 Via

Claims (8)

パッド直下に導電層配線メタルと層間絶縁膜が交互に複数積層され、前記層間絶縁膜を挟んで隣り合う導電層配線メタルがビアを介して接続され、前記積層された層が層間絶縁膜の材料が異なる複数のファイン層に分割され、前記材料の異なる層間絶縁膜間の界面の上層に形成された層間絶縁膜に形成されたビアの径が他のビアの径より太いことを特徴とする半導体装置。   A plurality of conductive layer wiring metals and interlayer insulating films are alternately stacked immediately below the pads, adjacent conductive layer wiring metals are connected via vias, and the stacked layers are materials for the interlayer insulating film. The semiconductor is characterized in that the diameter of the via formed in the interlayer insulating film formed in the upper layer of the interface between the interlayer insulating films of different materials is thicker than the diameter of the other vias, which are divided into a plurality of fine layers different from each other apparatus. パッド直下に導電層配線メタルと層間絶縁膜が交互に複数積層され、前記層間絶縁膜を挟んで隣り合う導電層配線メタルがビアを介して接続され、前記積層された層が層間絶縁膜の材料が異なる複数のファイン層に分割され、前記材料の異なる層間絶縁膜間の界面の上層に形成された層間絶縁膜に形成されたビア断面のアスペクト比が２．０以上であることを特徴とする半導体装置。   A plurality of conductive layer wiring metals and interlayer insulating films are alternately stacked immediately below the pads, adjacent conductive layer wiring metals are connected via vias, and the stacked layers are materials for the interlayer insulating film. Is divided into a plurality of different fine layers, and the aspect ratio of the cross section of the via formed in the interlayer insulating film formed in the upper layer of the interface between the interlayer insulating films of different materials is 2.0 or more Semiconductor device. パッド直下に導電層配線メタルと層間絶縁膜が交互に複数積層され、前記層間絶縁膜を挟んで隣り合う導電層配線メタルがビアを介して接続され、前記積層された層が層間絶縁膜の材料が異なる複数のファイン層に分割され、前記材料の異なる層間絶縁膜間の界面の上層に形成された層間絶縁膜に複数のビアを形成して合計の断面積を他のビアの断面積より大きくすることを特徴とする半導体装置。   A plurality of conductive layer wiring metals and interlayer insulating films are alternately stacked immediately below the pads, adjacent conductive layer wiring metals are connected via vias, and the stacked layers are materials for the interlayer insulating film. Are divided into a plurality of different fine layers, and a plurality of vias are formed in the interlayer insulating film formed above the interface between the interlayer insulating films of different materials to make the total cross-sectional area larger than the cross-sectional area of the other vias A semiconductor device comprising: パッド直下に導電層配線メタルと様々な厚みの層間絶縁膜が交互に複数積層され、前記層間絶縁膜を挟んで隣り合う導電層配線メタルがビアを介して接続され、最も厚みの薄い層間絶縁膜間の上下の層に形成された層間絶縁膜に形成されたビアの径が他のビアの径より太いことを特徴とする半導体装置。   A conductive layer wiring metal and a plurality of interlayer insulating films of various thicknesses are alternately stacked immediately below the pad, and adjacent conductive layer wiring metals are connected via vias, with the interlayer insulating film being the thinnest. A semiconductor device characterized in that a diameter of a via formed in an interlayer insulating film formed between upper and lower layers is larger than a diameter of another via. パッド直下に導電層配線メタルと様々な厚みの層間絶縁膜が交互に複数積層され、前記層間絶縁膜を挟んで隣り合う導電層配線メタルがビアを介して接続され、最も厚みの薄い層間絶縁膜間の上下の層に形成された層間絶縁膜に形成されたビア断面のアスペクト比が２．０以上であることを特徴とする半導体装置。   A conductive layer wiring metal and a plurality of interlayer insulating films of various thicknesses are alternately stacked immediately below the pad, and adjacent conductive layer wiring metals are connected via vias, with the interlayer insulating film being the thinnest. An aspect ratio of a via cross section formed in an interlayer insulating film formed between upper and lower layers is 2.0 or more. パッド直下に導電層配線メタルと様々な厚みの層間絶縁膜が交互に複数積層され、前記層間絶縁膜を挟んで隣り合う導電層配線メタルがビアを介して接続され、最も厚みの薄い層間絶縁膜間の上下の層に形成された層間絶縁膜に複数のビアを形成して合計の断面積を他のビアの断面積より大きくすることを特徴とする半導体装置。   A conductive layer wiring metal and a plurality of interlayer insulating films of various thicknesses are alternately stacked immediately below the pad, and adjacent conductive layer wiring metals are connected via vias, with the interlayer insulating film being the thinnest. A semiconductor device characterized in that a plurality of vias are formed in an interlayer insulating film formed between upper and lower layers so that the total cross-sectional area is larger than the cross-sectional areas of other vias. 前記導電層配線メタルは銅からなり、前記パッドはアルミニウムからなることを特徴とする請求項１または請求項２または請求項３または請求項４または請求項５または請求項６のいずれかに記載の半導体装置。   The said conductive layer wiring metal consists of copper, and the said pad consists of aluminum, Claim 3 or Claim 3 or Claim 4 or Claim 5 or Claim 6 characterized by the above-mentioned. Semiconductor device. 前記層間絶縁膜は、低誘電材料からなることを特徴とする請求項１または請求項２または請求項３または請求項４または請求項５または請求項６のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the interlayer insulating film is made of a low dielectric material.
JP2005143347A 2005-05-17 2005-05-17 Semiconductor device Pending JP2006324265A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009283858A (en) * 2008-05-26 2009-12-03 Oki Semiconductor Co Ltd Semiconductor device
DE112009004978T5 (en) 2009-04-28 2012-09-06 Mitsubishi Electric Corp. Power semiconductor device
JP2012194080A (en) * 2011-03-17 2012-10-11 Nec Corp Bolometer type thz wave detector
US9620460B2 (en) 2014-07-02 2017-04-11 Samsung Electronics Co., Ltd. Semiconductor chip, semiconductor package and fabricating method thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009283858A (en) * 2008-05-26 2009-12-03 Oki Semiconductor Co Ltd Semiconductor device
US8513778B2 (en) 2008-05-26 2013-08-20 Oki Semiconductor Co., Ltd. Semiconductor device
DE112009004978T5 (en) 2009-04-28 2012-09-06 Mitsubishi Electric Corp. Power semiconductor device
US8450796B2 (en) 2009-04-28 2013-05-28 Mitsubishi Electric Corporation Power semiconductor device
DE112009004978B4 (en) 2009-04-28 2020-06-04 Mitsubishi Electric Corp. Power semiconductor device
JP2012194080A (en) * 2011-03-17 2012-10-11 Nec Corp Bolometer type thz wave detector
US9620460B2 (en) 2014-07-02 2017-04-11 Samsung Electronics Co., Ltd. Semiconductor chip, semiconductor package and fabricating method thereof

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