JP2006310519A - Heterojunction bipolar transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a heterojunction transistor whose reliability is more improved without sacrificing its high-frequency performance. <P>SOLUTION: The heterojunction bipolar transistor is equipped with an n<SP>-</SP>-type InGaAs collector layer 3, a p<SP>+</SP>-type InGaAs base layer 4, an n-type InP emitter layer 5 having a mesa shape, and a successively laminated n<SP>+</SP>-type InGaAs emitter cap layer 6. A ledge structure 12 is formed around an emitter mesa, a base electrode 8 is formed directly on the upper surface of the base layer 4, the upper surface of the ledge structure 12 is covered with an insulating protective film 13 as a first insulating protective film which has an advantage of electrically inactivating the surface of a semiconductor, and the side wall surface of the ledge structure 12 and the upper surface of the base layer 4 are covered with an insulating protective film 10 as a second insulating protective film which is formed of materials different from those of the first insulating protective film and introduces defects little into the surface of the semiconductor. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to heterojunction bipolar transistors.

  The present invention relates to high reliability of a heterojunction bipolar transistor (HBT) useful for realizing an ultrahigh-speed integrated circuit. Here, an npn type InP / InGaAs-based HBT that is industrially important will be described as an example.

  An HBT is an element expected to be applied to an ultra-high-speed integrated circuit, but its practical use is required to have little characteristic variation and deterioration with time even if it is operated for a long time like other devices. A decrease in current gain has been reported as the degradation of HBT over time, and this is due to the occurrence of crystal defects and the like due to current injection, resulting in an increase in recombination current (for example, Non-Patent Document 1 below, 2).

FIG. 5 shows a cross-sectional view of a basic HBT structure. In the figure, 1 is a semi-insulating InP substrate, 2 is an n ⁺ type InP subcollector layer, 3 is an n ⁻ type InGaAs collector layer, 4 is a p ⁺ type InGaAs base layer, 5 is an n type InP emitter layer, and 6 is An n ⁺ -type InGaAs emitter cap layer, 7 is a collector electrode, 8 is a base electrode, and 9 is an emitter electrode. Reference numeral 10 denotes an insulating protective film that protects the surface of the HBT element, such as BCB and polyimide, and introduces fewer defects to the semiconductor surface. Reference numeral 11 denotes a wiring layer connected to the emitter electrode.

FIG. 6 shows an enlarged view of the emitter mesa and the base layer 4 in the vicinity of the external base region (not in contact with the emitter layer 5) where the recombination current is generated. In the figure, the insulating protective film 10 has a role of ensuring electrical insulation between the wiring layer 11 and the HBT element and protecting the surface of the HBT element. As a material for the insulating protective film 10, BCB (benzocyclobutene), polyimide, SiN (silicon nitride), SiO ₂ or the like is generally used. Among these, BCB and polyimide can be formed by a spin coating method, and damage to the element surface can be minimized. Therefore, the recombination current generated at the interface between the semiconductor surface and the insulating protective film can be sufficiently reduced. On the other hand, SiN and SiO ₂ are generally formed by chemical vapor deposition (CVD) or sputtering. When these insulating protective films are used, dangling bonds and carrier trap levels on the semiconductor surface can be terminated more effectively than BCB and polyimide, and the semiconductor surface can be electrically deactivated. Is possible. However, on the other hand, depending on the formation conditions and the type of semiconductor to be coated, a large amount of crystal defects and accompanying interface states are introduced, and Fermi level pinning on the device surface is performed. Sometimes. In this case, the carrier concentration on the surface of the element does not depend on the voltage application condition, so that in a sense, a stable state is realized. However, the current gain of the HBT is equal to the surface Fermi level. Care must be taken because it is strongly influenced by the energy position. For example, regarding the emitter mesa surface of an npn type HBT, when the Fermi level is pinned to (appropriate position) the valence band edge side, a surface depletion layer is formed, and the electron concentration on the emitter mesa surface is drastically reduced. As a result, a state in which recombination current hardly occurs is realized because the carriers themselves are depleted in spite of the presence of interface states. On the other hand, when the Fermi level is pinned to the conduction band edge side, on the contrary, an electron accumulation layer is generated in the vicinity of the emitter mesa surface, and the surface electron concentration increases drastically. As a result, the recombination current increases near the surface of the outer base layer where a large amount of holes exist, that is, at the emitter mesa wrinkles. Also, if the Fermi level on the surface of the outer base layer is pinned to the conduction band edge side, recombination with many holes existing in the base neutral region is remarkably promoted, which is fatal. Current gain degradation may occur.

In short, an insulating protective film such as BCB or polyimide does not damage the crystal surface, but it is difficult to effectively inactivate the surface. On the other hand, SiN and SiO ₂ can effectively inactivate the crystal surface, but depending on the case, a large amount of defects and interface states may be generated.

In InP / InGaAs-based HBTs, it has been reported that when a simple mesa structure as shown in FIG. 6 is used, if an insulating protective film such as SiN or SiO ₂ is used, the current gain is significantly reduced (for example, Non-patent document 3 below). This is because a narrow bandgap material such as InGaAs used for the base layer generally tends to introduce defects and interface states, and the Fermi level tends to be pinned to the conduction band edge side. It is. For this reason, not only a large amount of recombination centers are generated on the surface of the external base layer, but also the electron storage layer is formed, resulting in an increase in recombination current. In a severe case, the surface potential at the emitter mesa wrinkles may change in a complicated manner, and a surface leak channel may be formed. In this case, a large number of electrons are directly injected from the emitter neutral region to the external base surface, resulting in fatal current gain degradation. For this reason, in a simple mesa structure as shown in FIG. 6, BCB, polyimide, or the like that causes little damage to the element surface is often used as an insulating protective film.

  However, even with such an HBT, it has been reported that when an energization stress test is performed, the current gain decreases rapidly with time (see, for example, Non-Patent Document 2 below).

FIG. 7 shows the result of an energization stress test conducted by the present inventors using the HBT structure shown in FIG. The vertical axis shows the relative change in the current gain measured at room temperature, and the horizontal axis shows the stress elapsed time in logarithmic display. The energization stress conditions were an environmental temperature of 175 ° C., an injection current density of 1 mA / μm ² , and the current gain of the tested HBT in the initial state was 36.5 (average value) ± 2.1 (standard deviation). The current gain is a value when the collector current density is 1 mA / μm ² . From the figure, it can be seen that the current gain suddenly decreases in several tens of hours and once the deterioration is saturated, but gradually decreases again after several hundred hours. This phenomenon is due to the fact that (electrically neutral) trap levels and defect precursors already exist on the emitter mesa surface and the external base layer surface, and new defects are formed by applying electric charges. Suggests that. Further, the surface recombination itself may generate new recombination centers (occurrence of recombination promoting defects). In any case, in the HBT structure shown in FIG. 5, it is difficult to obtain a highly reliable element with little deterioration with time.

  In order to prevent the current gain deterioration described above, it is important to sufficiently reduce the interface states and recombination centers at the interface between the emitter mesa surface and the insulating protective film, or their defect precursors. Alternatively, when it is difficult to remove interface states, recombination centers, and defect precursors, it is necessary to devise measures so that the carriers themselves involved in recombination do not approach such defects. As a method for realizing this, in the late 1980s, a surface passivation structure was devised in which a part of the emitter layer was left on the periphery of the emitter mesa (see, for example, Non-Patent Document 4 below). In the 1990s, it was proved by many research institutions that this passivation structure is extremely effective for improving initial characteristics and preventing deterioration of energization stress (for example, Non-Patent Document 5 below, 6). Initially, this passivation structure was called "guard ring structure", and the technology for forming such a structure was called "Emitter Edge Thinning". Recently, the remaining emitter layer is often referred to as “Ledge”.

FIG. 8 shows a typical emitter mesa structure having a ledge. As a result of covering the p ⁺ -type InGaAs base layer 4 with the InP ledge structure 12 made of an epitaxial layer, the recombination current on the surface of the base layer 4 is greatly reduced. Further, since a certain amount of surface depletion layer is generated in the ledge structure 12, resistance is generated against lateral diffusion of electrons. For this reason, electron injection from the emitter neutral region to the ledge and from the ledge to the external base layer surface is also suppressed. As a result, it is possible to remarkably reduce electron accumulation and recombination on the ledge surface and the surface of the external base layer not covered with the ledge. That is, an environment in which crystal deterioration on the element surface is less likely to occur is realized.

FIG. 9 shows another form of the guard ring structure (a similar structure can be found in Non-Patent Document 7 below, for example). In this structure, the base electrode 8 is formed on the ledge structure 12, and the surface of the base layer 4 is completely covered with the ledge layer (12). Here, the contact from the base electrode 8 to the base layer 4 is realized by performing a thermal diffusion treatment or the like. This structure has an advantage that the recombination current on the surface of the external base layer can be completely removed because there is no region where the surface of the external base layer is exposed to the insulating protective film. However, if the ledge layer is not completely depleted, there is a risk that electrons directly flow from the emitter layer 5 to the base electrode 8 via the ledge structure 12. Therefore, in such a structure, the surface of the ledge structure 12 is electrically inactivated or the surface Fermi level is pinned to the valence band edge side to stably maintain the depletion of the ledge structure 12. Care must be taken to keep them. For this reason, it is considered that an insulating protective film such as SiN or SiO ₂ that is advantageous for electrical inactivation of the semiconductor surface is suitable as the insulating protective film 13.

  Furthermore, there is a structure similar to that shown in FIG. 9 as shown in FIG. 10 (see, for example, Non-Patent Document 8 below). This structure has an advantage in manufacturing that the emitter layer 5 itself is thin (about 10 nm), and it is not necessary to thin the emitter layer 5 in the outer periphery of the emitter mesa.

“Reliability and failure criteria for AlInAs / GaInAs / InP HBTs,” K. Kiziloglu, S. Thomas, F. Williams, Jr, BMPaine, Conference Proceedings of 2000 International Conference on Indium Phosphide and Related Materials (14-18May2000), pp .294-297. “Initial degradation of base-emitter junction in carbon-doped InP / InGaAs HBTs under bias and temperature stress,” K. Kurishima, S. Yamahata, H. Nakajima, H. Ito, N. Watanabe, IEEE Electron Device Letters, Volume 19, pp.303-305,1998. “Passivation of InP-based HBTs for high bit rate circuit applications,” D.Caffin, L.Bricard, JLCourant, LSHow Kee Chun, B.Lescaut, AMDuchenois, M.Meghelli, JLBenchimol, P.Launay, Conference Proceedings of 1977 International Conference on Indium Phosphide and Related Materials (11-15May1997), pp.637-640. “Super-gain AlGaAs / GaAs heterojunction bipolar transistors using an emitter edge-thinning design,” H.H.Lin, S.C.Lee, Applied Physics Letters, Volume 47, pp. 839-841, 1985. “Submicron-square emitter AlGaAs / GaAs HBTs with AlGaAs Hetero-guardring,” Y. Ueda, N. Hayama, K. Honjo, IEEE Electron Device Letters, Volume 15, pp. 66-68, 1994. “High performance InGaP / GaAs HBTs with AlGaAs / InGaP emitter passivated ledges for reliable power applications,” WLChen, TSKim, HFChau, T. Henderson, Conference Proceedings of 1997 International Conference on Indium Phosphide and Related Materials (11-15May1997) pp.361-364. “InAlAs / InP / InGaAs / InP DHBTs with a novel composite-emitter design,” R.Driad, WRMcKinnon, SPMcAlister, A.Renaud, T.Garanzotis, AJSpringthorpe, Conference Proceedings of 1999 International Conference on Indium Phosphide and Related Materials (16-20May1999), pp.435-438. “Reliability of InGaAs / InP HBTs with InP passivation structure,” R. Yamabi, K. Kotani, T. Kawasaki, M. Yanagisawa, S. Yaegashi, H. Yano, Conference Proceedings of 2003 International Conference on Indium Phosphide and Related Materials ( 12-16 May2003), pp.122-125.

  It has been reported that the use of the emitter mesa structure shown in FIG. 8 to FIG. However, such a conventional structure has the following problems and there is still room for improvement. Solving these problems and further improving the reliability of the HBT is extremely important in terms of expanding the practical application area of this device.

The conventional structure described above can be divided into those having a region where the surface of the external base layer is exposed (structure shown in FIG. 8) and those having no region (structure shown in FIGS. 9 and 10). First, a problem will be pointed out with respect to what has a region where the surface of the outer base layer is exposed (structure shown in FIG. 8). The important point in this structure is that there are still areas where the surface of the InP ledge structure 12 and the surface of the InGaAs external base layer are adjacent (ledge wrinkles) and areas where the surface of the external base layer is exposed. Therefore, similarly to the emitter mesa structure shown in FIG. 6, when an insulating protective film such as SiN or SiO ₂ is used, not only recombination centers are introduced in these regions but also an electron storage layer involved in recombination is formed. There is a risk that. That is, recombination is promoted by the ledge, and the meaning of forming the ledge itself is lost. Therefore, in the structure shown in FIG. 8, an insulating protective film such as BCB or polyimide that hardly introduces crystal defects is often used as in the structure shown in FIG. However, with such an insulating protective film, it is difficult to electrically inactivate the semiconductor surface, and it is difficult to stably deplete the ledge. As a result, when energization stress is applied, electron injection from the emitter to the ledge proceeds slowly, though slowly. In the long term, electron capture or the like occurs on the surface of the ledge, and accompanying this, surface degradation of the ledge layer or surface potential modulation occurs. Such changes increase the recombination current near the surface, leading to long-term degradation.

  On the other hand, in the structure where there is no region where the surface of the external base layer is exposed (the structure shown in FIGS. 9 and 10), there is no need to jeopardize the deterioration of crystallinity on the surface of the external base layer. However, care must be taken because the ledge layer itself will act as a surface leak channel unless the ledge layer surface is depleted reliably. Moreover, in such a structure, since the base electrode 8 is formed on the ledge layer (12), the base contact resistance is high. Therefore, there is a concern that the high-frequency performance of the HBT will deteriorate. In order to lower the base contact resistance, the ledge layer thickness can be reduced, but in this case, damage introduced during the formation of the insulating protective film may invade the base layer, which may impair the crystal quality of the base layer itself. . If this happens, the recombination current in the neutral base region increases, leading to a decrease in current gain. Therefore, when using such a structure, it is necessary to pay particular attention to the conditions for forming the insulating protective film. Further, since there is a limit even if the ledge layer is made thin, the base contact resistance is inevitably increased as compared with the structure shown in FIG. Further, in the structure shown in FIG. 10, since the emitter layer itself is thin, the emitter junction capacitance is also increased, and the high-frequency performance of the HBT is also impaired. In summary, even if high reliability can be achieved, it can be said that it is necessary to sacrifice high-frequency characteristics to some extent.

  The problem to be solved by the present invention is to provide a heterojunction bipolar transistor in which higher reliability is achieved without sacrificing high-frequency performance by improving the problems of the conventional structure shown in FIG. There is to do.

In order to solve the above problems, in the present invention, as described in claim 1,
In a heterojunction bipolar transistor in which a subcollector layer, a collector layer, a base layer, an emitter layer having a mesa shape, and an emitter cap layer are sequentially stacked in this order on a semiconductor substrate, a mesa peripheral portion of the emitter layer A ledge structure is formed, a base electrode is directly formed on the upper surface of the base layer, the upper surface of the ledge structure is covered with a first insulating protective film, and the sidewall surface of the ledge structure; A heterojunction bipolar characterized in that an upper surface of the base layer not contacting the emitter layer and the ledge structure is covered with a second insulating protective film made of a material different from the first insulating protective film. A transistor is formed.

In the present invention, as described in claim 2,
2. The heterojunction bipolar transistor according to claim 1, wherein any of InP, InAlP, InGaP, InGaAsP, InAlAs, and InAlGaAs is used as the material of the emitter layer, and InGaAs, InGaAsP, InAlGaAs, and GaAsSb are used as the material of the base layer. , InGaAsSb, or AlGaAsSb is used, SiN or SiO ₂ is used as the material of the first insulating protective film, and BCB or polyimide is used as the material of the second insulating protective film. Is used to form a heterojunction bipolar transistor.

  By implementing the present invention, it is possible to provide a heterojunction bipolar transistor in which higher reliability is achieved without sacrificing high-frequency performance.

In the present invention, it is proposed to form optimum insulating protective films on the upper surface of the ledge, the surface of the ledge side wall and the surface of the external base layer, respectively. That is, the semiconductor surface can be electrically inactivated on the upper surface of the ledge, or an interface state can be formed on the valence band edge side to stably deplete the ledge, such as SiN or SiO ₂ The insulating protective film is used. On the other hand, an insulating protective film such as BCB or polyimide that hardly introduces crystal defects and interface states is used on the ledge sidewalls and the surface of the external base layer that are vulnerable to damage. As described above, by selectively applying the insulating protective film, it is possible to stably maintain depletion of the surface of the ledge layer while avoiding crease and crystal deterioration on the surface of the external base layer. As a result, electron injection into the ledge is inhibited even for a long time, and crystal deterioration on the ledge surface can be avoided.

One embodiment of the structure of the HBT according to the present invention is shown in FIG. This HBT is formed on a subcollector layer (not shown) formed on an InP substrate (not shown), which is a semiconductor substrate, and in the figure, an n ⁻ type InGaAs collector layer 3 and a p ⁺ type InGaAs. A base layer 4, an n-type InP emitter layer 5 having a mesa shape, and an n ⁺ -type InGaAs emitter cap layer 6 are sequentially laminated in this order to constitute a heterojunction bipolar transistor. Further, a ledge structure 12 is formed in the mesa periphery of the emitter layer 5 so that a part of the emitter layer 5 protrudes, and the base electrode 8 is formed on the upper surface of the base layer 4 (that is, on the side far from the InP substrate). Is formed directly, and the upper surface of the ledge structure 12 is covered with an insulating protective film 13 that is a first insulating protective film, which is advantageous for electrical deactivation of the semiconductor surface, and the sidewall surface of the ledge structure 12; The upper surface of the base layer 4 that is not in contact with the emitter layer 5 and the ledge structure 12 is a second insulating protective film made of a material different from that of the first insulating protective film. It is covered with a protective film 10.

  As the insulating protective film 13, SiN is deposited by plasma CVD, and the upper surface of the ledge structure 12 is electrically inactivated. On the other hand, the sidewall surface of the ledge structure 12 and the upper surface of the base layer 4 are covered with BCB which is the insulating protective film 10 so that crystal defects and interface states are not formed.

  The above structure and the effects obtained thereby can be generalized to describe the ledge layer on the upper surface of the ledge structure by electrically inactivating the semiconductor surface or by pinning the Fermi level. Use an insulating protective film that depletes stably. On the other hand, an insulating protective film that hardly causes crystal defects and interface states is used for the surface of the ledge sidewall that is vulnerable to damage and the upper surface of the base layer. As a result, it is possible to avoid ledge wrinkles and crystal deterioration on the upper surface of the base layer, and at the same time stabilize the surface depletion of the ledge. In this way, electron injection from the emitter to the ledge is sufficiently suppressed, and crystal degradation on the ledge surface is avoided. As a result, it is possible to avoid long-term current gain degradation.

  2 and 3 show an example of process steps for realizing the guard ring structure shown in FIG. The emitter layer 5 has a thickness of 70 nm, the ledge structure 12 has a thickness of 20 nm, the emitter mesa width is 1 μm, and the ledge width is 0.3 μm. Here, in order to control the ledge layer thickness with high accuracy, an ultra-thin InGaAs etch stopper layer having a layer thickness of 2 nm at a position 20 nm away from the emitter / base layer interface (a position 50 nm away from the cap / emitter layer interface). 14 is inserted.

  The process for forming the HBT structure is as follows.

  First, an emitter electrode 9 is formed, and a resist mask 15 for forming an emitter mesa is formed [(a) of FIG. 2]. Thereafter, the InGaAs emitter cap layer 6 is etched by a dry etching method such as reactive ion etching (RIE), and the InP emitter layer 5 is further etched by about 20 nm. Then, the remaining InP layer is selectively etched using a hydrochloric acid-based wet etchant, and then the InGaAs etch stopper layer 14 is selectively etched using a citric acid-based wet etchant. Thereafter, the resist mask is removed, and a SiN film is deposited on the entire surface of the wafer by a plasma CVD method (FIG. 2B).

  Next, a resist mask 16 that is 0.3 μm larger on one side than the resist mask for forming the emitter mesa is formed. Then, using this resist mask 16, the SiN film (13) is removed by the RIE method or the like. Thereafter, using the remaining SiN film (13) as a mask, the InP layer (12) is selectively removed by a wet etchant, and the upper surface of the InGaAs base layer 4 is exposed [(c) of FIG. 3]. Then, the base electrode 8 is formed by the lift-off method, and the HBT mesa structure is completed by a commonly used method. Then, if a BCB film is formed by a spin coating method and the wiring layer 11 is formed, a desired HBT structure can be obtained [(d) of FIG. 3].

  In the case of forming a conventional ledge structure, a resist mask is formed after exposing the InGaAs etch stopper layer 14, and the 2nm InGaAs etch stopper layer 14 and the 30nm InP layer (12) are removed. Here, after that, the ultra-thin etch stopper layer 14 on the ledge layer is also removed so that the ledge surface becomes InP as in the new structure (the structure of the present embodiment).

  Incidentally, it is pointed out that when the ledge layer thickness does not need to be controlled with high accuracy (for example, on the order of 1 nm), the RIE etching time may be controlled without providing the InGaAs etch stopper layer 14. In the present embodiment, an InGaAs etch stopper layer 14 is provided in order to realize a conventional structure and a new structure having a ledge structure of the same size. Since the HBT energization deterioration also depends on the size of the ledge structure, it should be noted that a ledge structure of the same size must be prepared in order to compare the conventional structure and the new structure equally.

  Through the above steps, the conventional HBT shown in FIG. 8 and the HBT according to the present invention shown in FIG. 1 were produced, and an energization stress test was performed. Here, the conventional HBT and the HBT according to the present invention are manufactured using the same molecular beam epitaxy (MBE) apparatus using epitaxial wafers grown simultaneously. That is, there is no difference in crystal quality between the two. Furthermore, it should be noted that both the conventional HBT and the HBT according to the present invention were simultaneously manufactured using the same process apparatus.

FIG. 4 shows the results of the energization stress test of the conventional HBT and the HBT according to the present invention. The vertical axis shows the relative change in the current gain measured at room temperature, and the horizontal axis shows the stress elapsed time in logarithmic display. The energization stress conditions are an environmental temperature of 175 ° C., an injection current density of 1 mA / μm ² , and the current gain of the tested HBT in the initial state is 57.4 (average value) ± 1.5 (standard deviation) in the HBT according to the present invention. ), 56.2 (average value) ± 0.8 (standard deviation) in the conventional HBT. The current gain is a value when the collector current density is 1 mA / μm ² . Compared with the energization stress test result (for the HBT having no ledge structure) shown in FIG. 7, it can be seen that the time-dependent deterioration of the current gain can be significantly suppressed even in the conventional structure. However, in a long-term span, the current gain decreases by about 20% after 10,000 hours (417 days). On the other hand, in the structure according to the present invention, it can be seen that the change in current gain after 10,000 hours is suppressed to 10% or less. From another point of view, the energization stress time required to reduce the current gain to 90% is about 1000 hours in the conventional structure, but is 10,000 hours or more in the structure according to the present invention. Therefore, in the HBT according to the present invention, the deterioration life is improved by one digit or more as compared with the conventional HBT.

  From the result of the energization stress test described above, the effect of the HBT structure according to the present invention is clear. By using the present invention, it is possible to dramatically increase the energization deterioration life compared to the conventional HBT structure. This also improves the reliability of the HBT integrated circuit, which is advantageous for large-scale integration of the HBT. As a result, the ripple effect that the application range of the HBT integrated circuit is expanded is brought about.

In the description of the above embodiment, the npn InP / InGaAs HBT that is promising for realizing a high-speed circuit has been described in detail. However, the same effect can be obtained by using a GaAsSb material, which is a narrow band gap material, in the base layer. It can also be expected for the HBT used. Similar proposals can be made for pnp type HBTs. In general, including the above-described embodiments, any of InP, InAlP, InGaP, InGaAsP, InAlAs, and InAlGaAs is used as the material for the emitter layer, and InGaAs, InGaAsP, InAlGaAs, GaAsSb, InGaAsSb, and AlGaAsSb are used as the material for the base layer. One of them may be used, either SiN or SiO ₂ may be used as the material of the first insulating protective film, and either BCB or polyimide may be used as the material of the second insulating protective film.

It is a figure which shows one Embodiment of the structure concerning this invention. It is a figure which shows one Embodiment of the manufacturing process which implement | achieves the structure shown in FIG. It is a continuation of FIG. It is a figure which shows the energization stress test result of conventional HBT shown in FIG. 8, and HBT by this invention shown in FIG. It is an example of sectional drawing of a basic HBT structure. FIG. 6 is an enlarged view of an emitter mesa region and an external base region in the HBT structure shown in FIG. 5. It is a figure which shows the energization stress test result of the HBT structure shown in FIG. It is a figure which shows one Embodiment of a conventional structure. It is a figure which shows one Embodiment of a conventional structure. It is a figure which shows one Embodiment of a conventional structure.

Explanation of symbols

1: semi-insulating InP substrate, 2: n ⁺ type InP subcollector layer, 3: n ⁻ type InGaAs collector layer, 4: p ⁺ type InGaAs base layer, 5: n type InP emitter layer, 6: n ⁺ type InGaAs Emitter cap layer, 7: Collector electrode, 8: Base electrode, 9: Emitter electrode, 10: Insulating protective film with less defect introduction to the semiconductor surface, 11: Wiring layer, 12: InP ledge structure, 13: Electricity on the semiconductor surface Insulating protective film advantageous for mechanical deactivation, 14: etch stopper layer, 15, 16: resist mask.

Claims (2)

In a heterojunction bipolar transistor in which a subcollector layer, a collector layer, a base layer, an emitter layer having a mesa shape, and an emitter cap layer are sequentially stacked in this order on a semiconductor substrate,
A ledge structure is formed around the mesa of the emitter layer,
A base electrode is directly formed on the upper surface of the base layer;
An upper surface of the ledge structure is covered with a first insulating protective film;
The sidewall surface of the ledge structure and the upper surface of the base layer that is not in contact with the emitter layer and the ledge structure are covered with a second insulating protective film made of a material different from the first insulating protective film. A heterojunction bipolar transistor characterized by comprising: The heterojunction bipolar transistor according to claim 1, wherein
As the material of the emitter layer, any of InP, InAlP, InGaP, InGaAsP, InAlAs, and InAlGaAs is used.
As the material of the base layer, any of InGaAs, InGaAsP, InAlGaAs, GaAsSb, InGaAsSb, and AlGaAsSb is used.
As the material of the first insulating protective film, either SiN or SiO ₂ is used,
A heterojunction bipolar transistor characterized in that either BCB or polyimide is used as a material of the second insulating protective film.

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