JP3345293B2 - Heterojunction bipolar transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device structure of a heterojunction bipolar transistor using a compound semiconductor.

[0002]

2. Description of the Related Art Heterojunction bipolar transistors (hereinafter abbreviated as HBTs) are characterized by using a semiconductor material having a band gap larger than that of a base layer for an emitter layer, and are expected to be applied to high-speed and high-frequency integrated circuits. ing. When forming an HBT structure, AlGaAs and Ga
As, InGaP and GaAs, InAlAs and InGa
As and the combination of InP and InGaAs are the most important from the viewpoint of lattice matching of material crystals, and are therefore widely used. In particular, InP is used for the emitter layer,
InP / InGaAs using InGaAs for base layer
Since the system HBT has both excellent high-frequency characteristics and low power consumption characteristics, it is expected to be applied to next-generation ultra-high-speed integrated circuits.

[0003] The HBT generally has a mesa structure, but leakage current on the mesa surface often poses a problem. If the leakage current on the surface of the emitter mesa is large, the current gain is reduced, which causes a problem in circuit application. Also, if the leakage current on the surface of the collector mesa is large, deterioration of the collector breakdown voltage characteristic and the like will be caused. In the HBT, since the absolute value of the base current is as small as 1 / current gain of the absolute value of the collector current, it is particularly important to suppress the surface leakage current in the emitter mesa.

[0004] The generation of surface leakage current is generally considered to be caused by the generation of defects on the surface of the semiconductor mesa side wall. In order to suppress such surface leakage current,
A method of forming a surface protection film (passivation film) on the HBT mesa structure has been used. Here, the main purpose of the surface protective film is to suppress the generation of surface defects caused by external mechanical / chemical stress.

The material of the surface protective film is SiO ₂ , S
iN or polyimide. Among them, an organic film such as polyimide has a feature that few surface defects are introduced during film formation, and therefore, an I film having a low mechanical strength is used.
In an nP / InGaAs-based HBT, as a surface protective film,
Generally, an organic film such as polyimide is used.

[0006]

When polyimide is used as the surface protective film, ideal current-voltage initial characteristics with very little surface leakage current can be obtained. However, as specifically exemplified in “Embodiments” described later, when an electric stress is applied, a phenomenon occurs in which surface leakage current occurs within a short time of less than several hours. This phenomenon means that a new defect was generated on the surface of the side wall of the emitter mesa due to the electric stress.

According to the results of the study by the present inventor, this phenomenon is particularly caused by InP / InGaAs based HBTs.
This is remarkable when P is used as a material for the emitter layer. To completely stabilize the emitter mesa sidewall surface, simply
Using a surface protective film alone is not enough. In order to avoid the occurrence of emitter leakage current (or surface defects) due to electrical stress, it is necessary to take some measures on the emitter mesa itself.

An object of the present invention is to provide an HBT having an InP emitter mesa, which has an emitter mesa structure for suppressing generation of surface leakage current due to electric stress.

The inventor of the present invention has conducted careful studies on the assumption that the activation energy required for generating this surface defect has a deep correlation with the crystal plane orientation of the emitter mesa side wall. As a result, on the emitter mesa side wall,
It has been found that, when a plane that is crystallographically equivalent to the (01 1− ) plane exists, surface defects easily occur, and the surface leakage current increases. At the same time, (0
It was also confirmed that when there was no crystallographically equivalent plane to the 11- ) plane, no emitter surface leakage current was generated. Here, the above “1-” indicates a numerical value “−1”.
And

The present invention has been made based on the above findings, and has been described in claim 1 to achieve the above object.
As described above, a collector layer and a p-type
Layer and an n-type InP emitter layer are sequentially stacked.
Mesa heterojunction bipolar transistor
And the InP emitter mesa sidewalls are (111) plane, (1
1-1-) plane, (101) plane, (101-) plane, (11) plane
0) plane and (11-0) plane.
Construct heterojunction bipolar transistor
I do.

Further , according to the present invention, as described in claim 2, the semiconductor substrate having the (100) plane as a main surface has a small size.
At least a collector layer, a base layer, and an InP emitter layer
-Type heterojunction bipolar bipolar transistor
In the transistor, the emitter region has a crystal orientation [01]
1], [010], and [001].
Heterojunction type bipolar transistor
Configure the data. Thus, defining the emitter region
And (011-) plane or crystallographically equivalent
Realizing an InP emitter mesa that does not form a complicated surface
It becomes possible.

In the specification of the present application, a numeral surrounded by (), such as (100), indicates a plane direction, and [0]
11] indicates a crystal direction (direction of a normal vector of a crystal plane). Also, "1-"
Indicates a numerical value “−1” .

[0012]

FIG. 3 is a sectional view showing a layer structure of an InP / InGaAs-based HBT used in an embodiment for realizing the present invention. In FIG. 3 , 1 is n-InG
aAs cap layer, 2 is an n-InP emitter layer, 3 is p
-InGaAs base layer, 4 is an i-InGaAs collector layer, 5 is an n-InGaAs sub-collector layer, and 6 is (1
00) InP substrate. 7 is an emitter electrode, 8
Is a base electrode, 9 is a collector electrode, and 10 is a polyimide surface protective film.

[0013] The mesa structure of the HBT shown in FIG. 3,
After the emitter electrode 7 is formed by lift-off, the emitter electrode 7 is used as a mask to remove the InGaAs cap layer 1 with a sulfuric acid type etching solution and the InP emitter layer 2 with a hydrochloric acid type etching solution. .

It is known that when the InP layer is selectively etched with a hydrochloric acid-based etchant after a mask pattern is formed, InP mesa side walls are formed depending on the direction of the mask pattern. For example, (100) when performing etching by performing [011] direction of the stripe pattern on an InP substrate, as shown in FIG. 4 (a), (01 1-)
A plane and a ( 01-1 ) plane are formed. Also, (100) I
If nP on a substrate to form a [01 1] direction of the stripe pattern is etched to InP, as shown in FIG. 4 (b), is formed (1 1-1-) plane and (111) plane You. Further, (100) is etched the InP to form the 010 "direction of the stripe pattern on the InP substrate, as shown in FIG. 4 (c), (101) plane and (10
1) plane, or (1-01) plane and (1 0 1) surface is formed.

As described above, if etching is performed by applying a stripe pattern other than the [011] direction, InP
The emitter mesa sidewall has a (111) plane, a (101) plane, and planes equivalent thereto [( 1-1-1 ), (10 1 )
-), (110), (1 1 0), (1 0 1),
(1 01), (1-1- 0), a structure configured by the (1-10) plane].

The present inventor has realized an emitter mesa structure according to the present invention as shown in FIG. 1 by utilizing the above etching characteristics. Hereinafter, FIGS. 1, 2 and 4 will be referred to.
Where 1 is an underlined symbol, the symbol “1-” in this specification is used.
Hit. The implementation of the form are shown in FIG. 1, InP emitter mesa sidewalls, (111) plane, (101) plane, and their equivalent surface [(1 1-1-), (10 1), (11
0), ( 11-0 ) plane] ,
(011-) plane is not formed. In FIG. 1, reference numerals 1, 2, 7, and 8 denote the same components as those in FIG.

Further, in order to clearly show the effects of the present invention,
An emitter mesa structure for comparison as shown in FIG. 2 was also prepared. In this comparative example, the InP emitter mesa sidewall is (0
1 1) plane, (101) plane, and their equivalent plane [(0 1 1), (10 1), (110), (1 1
0) plane].

FIGS. 5 and 6 show current-voltage characteristics of the HBT having the emitter mesa structure shown in FIGS. 1 and 2 , respectively. 5 and 6 , the broken lines indicate the initial characteristics before the application of the electric stress, and the solid lines indicate the characteristics after the application of the electric stress. Here, the electric stress is such that a forward voltage of 0.85 V is applied between the emitter and the base, a reverse voltage of −0.2 V is applied between the base and the collector,
This was done by applying for 5 hours. This voltage application causes a collector current of about 50 kA / cm ² to flow through the HBT.

FIG. 5 or al apparent, the HBT having the emitter mesa structure consisting of the present invention, and overlaps the characteristics after the application of electrical stress indicated by the initial characteristics and the solid line shown by the broken line, the characteristics due to an electric stress It can be seen that no deterioration has occurred. The ideal factors (ideality factors) of the collector current and the base current are both smaller than 1.1, and the ideal current-voltage characteristics are maintained. The above facts indicate that the InP emitter mesa sidewalls
If it is composed of the (111) plane, the (101) plane, or a plane equivalent thereto, it means that no defect is generated on the mesa surface even when an electric stress is applied.

Meanwhile, in the emitter mesa structure illustrated in FIG. 2,
As is clear from FIG. 6, the base current after the application of the electric stress indicated by the solid line is significantly increased. In other words, it can be seen that when a (01 1- ) plane or a plane equivalent thereto appears on the InP emitter mesa side wall, a surface defect is easily generated.

[0021]

As described above, if the InP emitter mesa side wall is formed only of a crystal plane other than a plane crystallographically equivalent to the (01 1- ) plane, the emitter surface leakage current caused by electric stress is reduced. Occurrence can be prevented. The present invention has an excellent effect that, in particular, it is possible to suppress the initial deterioration of energization, which often becomes a problem when the HBT is energized.

[Brief description of the drawings]

Figure 1 is a plan view and a sectional view showing a form of implementation of the present invention, InP emitter region, the crystal axis [011] and
[010] and crystals crystallographically equivalent to these
FIG. 4 is a diagram showing an emitter mesa structure characterized by being defined by an axis .

FIG. 2 is a plan view and a cross-sectional view of a comparative example, in which an InP emitter region has crystal axes [011] and [010], and
Defined by crystallographically equivalent crystal axes
FIG. 4 is a diagram showing an emitter mesa structure characterized by the following.

FIG. 3 is a cross-sectional view of an InP / InGaAs-based HBT structure.

FIG. 4 is a perspective view showing a crystal plane orientation formed when InP is etched by applying a stripe pattern mask on a (100) InP substrate, and (a) is [011].
(B) is [0]
When a stripe pattern in the 11- ] direction is applied,
(C) is a diagram showing a case where a stripe pattern in the [010] direction is applied.

5 is a current-voltage characteristic of the HBT according to the implementation of the embodiment are shown in FIG.

FIG. 6 shows current-voltage characteristics of an HBT to which the comparative example shown in FIG. 2 is applied.

DESCRIPTION OF SYMBOLS 1 ... n-InGaAs cap layer 2 ... n-InP emitter layer 3 ... p-InGaAs base layer 4 ... i-InGaAs collector layer 5 ... n-InGaAs sub-collector layer 6 ... (100) InP substrate 7 ... Emitter electrode 8 Base electrode 9 Collector electrode 10 Polyimide surface protective film 11 Stripe pattern mask 12 (100) InP

Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/33-21/331 H01L 29/68-29/737 H01L 21/306-21/3063 H01L 21/308

Claims (2)

(57) [Claims] In a mesa-type heterojunction bipolar transistor in which a collector layer, a p-type base layer, and an n-type InP emitter layer are sequentially stacked on a semiconductor substrate, the InP emitter mesa sidewall has (111) Plane, (1
1-1-) plane, (101) plane, (101-) plane, (11) plane
A heterojunction bipolar transistor comprising a (0) plane and a (11-0) plane . 2. A mesa-type heterojunction bipolar transistor in which at least a collector layer, a base layer, and an InP emitter layer are sequentially stacked on a semiconductor substrate having a (100) plane as a main surface, an emitter region is formed of a crystal. A heterojunction bipolar transistor defined by directions [011-], [010], and [001] .