JP3108829B2 - InP-based field-effect semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an InP-based field effect type semiconductor device.

[0002]

2. Description of the Related Art In recent years, AlGaAs has been formed on a GaAs substrate.
HEMT in which an InAlAs / InGaAs structure is formed on an InP substrate excellent in high-speed operation, instead of a field effect semiconductor device such as a HEMT having a / GaAs structure.
Research on InP-based field-effect semiconductor devices such as those described above has been active.

However, when a semiconductor material such as InAlAs is exposed on the surface of such a semiconductor device, the semiconductor material may be exposed depending on the atmosphere exposed during manufacture or use.
In ₂ O ₃ or Al is formed on the surface of a semiconductor material layer such as nAlAs.
An oxide film such as ₂ O ₃ or another metamorphic layer is formed, and a phenomenon such as an increase in gate leak current and a decrease in gate withstand voltage, or deterioration over time or deterioration over time is observed.

[0004]

However, nevertheless,
Conventionally, InAlAs / In is formed on an InP substrate as described above.
An effective method for preventing deterioration of characteristics of a semiconductor device such as a HEMT having a GaAs structure has not been found.
The present invention provides an IP substrate on an InP substrate in which deterioration of characteristics over time is suppressed.
An object of the present invention is to provide an InP-based field-effect semiconductor device such as a HEMT having an nAlAs / InGaAs structure.

[0005]

In InP based field effect semiconductor device according to the present invention SUMMARY OF THE INVENTION may, Oh consisting InGaAs
Layer and an electron supply layer made of InAlAs.
A protective layer made of GaAs is formed on the
Cut off and properly select the composition of the InGaAs layer.
Balance the stresses and transfer them into the semiconductor crystal as a whole.
To prevent the introduction of
s ohmic layer and InAlAs electric children
Formed on the surface of a compound semiconductor layer containing In, such as a supply layer.
With emphasis on the suppression of altered layers
Arbitrarily and ignoring that it is introduced
Properly stipulated is the basis.

[0006]

[0007]

[0008]

[0009]

According to the present invention, InAlA is formed on an InP substrate.
In a semiconductor device such as a HEMT having an s / InGaAs structure, an InAlAs layer on an exposed surface thereof, an InGaAs
On a semiconductor layer containing In such as an s layer, a GaAs layer having a different lattice constant from these semiconductor materials but hardly causing a metamorphic layer is formed.
When the s protective layer is formed, deterioration of characteristics such as a decrease in gate breakdown voltage and an increase in leak current, which have conventionally been problems, can be prevented, and a highly reliable, high performance field effect semiconductor device can be realized.

In this case, if the GaAs protective layer is made thinner than about 20 °, crystal dislocations can be prevented from being introduced into the adjacent semiconductor crystal layer. However, even if the crystal dislocations are introduced, the characteristics of the device are not affected. It is not necessary to limit the thickness of the GaAs protective layer in an ohmic region or the like where no pitting occurs.

[0011]

Embodiments of the present invention will be described below. FIG. 1 shows an InP-based HEMT according to a first embodiment.
FIG. In this figure, 1 is an InP substrate, 2 is an i-InAlAs buffer layer, 3 is i-InG
aAs channel layer, 4 is a two-dimensional electron gas, 5 is n-In
An AlAs electron supply layer, 6 is an n (or i) -GaAs protective layer, 7 is an n-InGaAs ohmic layer, 8 is an n (or i) -GaAs protective layer, 9 is a gate electrode, 10 is a source electrode, and 11 is a drain. Electrode, 12 is HEMT area, 1
3 is an ohmic region.

In the InP-based HEMT of this embodiment, a 3000 ° thick i-InA
lAs buffer layer 2, i-InGaAs with a thickness of 500 °
A channel layer 3 and a 500-nm thick n-InAlAs electron supply layer 5 are grown to form a HEMT region 12, on which a 15-nm thick n (or i) -GaAs protective layer 6, a 500-mm thick, InP with impurity concentration of 2 × 10 ¹⁸ cm ^-3
An n-InGaAs ohmic layer 7 lattice-matched to the substrate,
A 20 ° thick n (or i) -GaAs protective layer 8 is grown to form an ohmic region 13, and the n (or i) -GaAs protective layer 8 at the center of the ohmic region 13 is formed.
The n-InGaAs ohmic layer 7 is removed by etching in a strip shape, and the exposed n (or i) -GaAs protective layer 6 is removed.
On the n (or i) -GaAs protective layer 8 divided into two, a source electrode 10 and a drain electrode 11 are formed.

The two-dimensional electron gas 4 is formed in the i-InGaAs channel layer 3 by the n-InAlAs electron supply layer 5. In addition, i-InAlAs buffer layer 2, i-InGaAs channel layer 3, n-InAlA
Various modifications of the HEMT region 12 including the s-electron supply layer 5 are conceivable.

In this InP-based HEMT, nI
The electrons in the two-dimensional electron gas 4 formed in the i-InGaAs channel layer 3 by the nAlAs electron supply layer 5 are controlled by the potential of the gate electrode 9 and the source electrode 10
By moving between the gate electrode and the drain electrode 11 at high speed, an amplifying action or a switching action occurs.

[0015] In this embodiment, the surface of the n-In Ga As layer 7 serving as the uppermost layer would otherwise, n (or i) -GaAs protective layer 8 is formed, also if originally gate electrode 9 And n (or i) on the surface of the n-InAlAs electron supply layer 5 exposed around the gate electrode 9.
A GaAs protective layer 26 is formed.

As described above, the n-I which easily forms the metamorphic layer
The n GaAs layer 7 and the n-InAlAs electron supply layer 5
(Or i) -GaAs protective layer 8, n (or i) -Ga
The As protective layer 6 shuts off the external atmosphere, suppresses the formation of a metamorphic layer on the surface of these layers, and reduces characteristic deterioration such as a decrease in gate breakdown voltage.

In this embodiment, n-InG
The aAs ohmic layer 7 is lattice-matched to the InP substrate, and n (or i) adjacent to both sides thereof has a different lattice constant.
-The thickness of the GaAs protective layer 6 is 15 °, n (or i)-
Since the thickness of the GaAs protective layer 8 is as thin as 20 °, the strain is absorbed and the n-InGaAs ohmic layer 7 and the n-InA
No dislocation is introduced into the 1As electron supply layer 5.

(Second Embodiment) FIG. 2 is a diagram showing a second embodiment of the present invention.
FIG. 3 is an explanatory diagram of a configuration of a P-based HEMT. In this figure, 2
1 is an InP substrate, 22 is an i-InAlAs buffer layer,
23 is an i-InGaAs channel layer, 24 is a two-dimensional electron gas, 25 is an n-InAlAs electron supply layer, and 26 is n
(Or i) -GaAs protective layer, 27 is n-InGaAs
An ohmic layer, 28 is an n (or i) -GaAs protective layer, 29 is a gate electrode, 30 is a source electrode, 31 is a drain electrode, 32 is a HEMT region, and 33 is an ohmic region.

In the InP-based HEMT of this embodiment, an i-InAlAs buffer layer 22, an i-InGaAs channel layer 23, an n-InA
A 1As electron supply layer 25 is grown to form a HEMT region 32, on which a 20 ° thick n (or i) -GaAs
Protective layer 26, thickness 100 °, impurity concentration 3 × 10 ¹⁸
n-InGaAs having an InAs molar ratio of 0.75 at cm ^-3
s ohmic layer 27, 20 (thickness) n (or i) −
A GaAs protective layer 28 is grown to form an ohmic region 33, and the n (or i) -GaAs protective layer 28 and the n-InGaAs ohmic layer 27 in the center of the ohmic region 33 are removed by strip etching. Exposed, n
(Or i) Gate electrode 29 on -GaAs protective layer 26
The source electrode 30 and the drain electrode 31 are formed on the n (or i) -GaAs protective layer 28 divided into two.

The two-dimensional electron gas 24 is formed in the i-InGaAs channel layer 23 by the n-InAlAs electron supply layer 25, and the electrons in the two-dimensional electron gas 24 are controlled by the potential of the gate electrode 29. By moving between the source electrode 30 and the drain electrode 31, an amplifying action or a switching action occurs.

The i-InAlAs buffer layer 22,
As the HEMT region 32 including the i-InGaAs channel layer 23 and the n-InAlAs electron supply layer 25, various modifications can be considered.

[0022] In this embodiment, the surface of the n-In Ga As layer 27 is the top layer would otherwise, n (or i) -GaAs protective layer 28 is formed, also, the gate electrode 29 would otherwise And n-InAlAs electron supply layer 25 exposed around gate electrode 29
(Or i) Since the -GaAs protective layer 26 is formed and is shielded from the external atmosphere, formation of a metamorphic layer on the surface of these layers is suppressed, and deterioration in characteristics such as a decrease in gate breakdown voltage is reduced. .

In this embodiment, n-In
Although the lattice constant of the GaAs layer 27 is larger than the lattice constant of the InP substrate 21, n (or i) -G
The thickness of the aAs protective layer 28 is set to 20 °, and n (or i) −
Since the thickness of the GaAs protective layer 26 is set to 20 °, the stress is balanced and the generation of dislocations in the adjacent crystal layer can be suppressed.

(Third Embodiment) FIG. 3 is a diagram showing the In embodiment of the third embodiment.
FIG. 3 is an explanatory diagram of a configuration of a P-based HEMT. In this figure, 4
1 is an InP substrate, 42 is an i-InAlAs buffer layer,
43 is an i-InGaAs channel layer, 44 is a two-dimensional electron gas, 45 is an n-InAlAs electron supply layer, and 46 is n
(Or i) -GaAs protective layer, 47 is n-InAlAs
Layer, 48 is an n-InGaAs ohmic protection layer, 49 is an n (or i) -GaAs layer, 50 is a gate electrode, 51
Is a source electrode, 52 is a drain electrode, 53 is a HEMT region, and 54 is an ohmic region.

In the InP-based HEMT of this embodiment, an i-InAlAs buffer layer 42, an i-InGaAs channel layer 43, and an n-InA
A 1As electron supply layer 45 is grown to form a HEMT region 53, on which a 20 ° thick n (or i) -GaAs
A protective layer 46, an n-InAlAs layer 47 lattice-matched to the InP substrate 41 having a thickness of 30 °, a thickness of 100 °, an impurity concentration of 3 × 10 ¹⁸ cm ^-3 and a molar ratio of InAs of 0.75.
N-InGaAs having a larger lattice constant than the InP substrate 41
s ohmic layer 48, 20 (thickness) n (or i) −
A GaAs protective layer 49 is grown to form an ohmic region 54, and the n (or i) -GaAs protective layer 49, n-InGaAs ohmic layer 48, and n-InAlAs layer 47 at the center of the ohmic region 54 are formed in a strip shape. Etched and removed to expose the exposed n (or i) -GaAs protective layer 4
6, a gate electrode 50 is formed, and a source electrode 51 and a drain electrode 52 are formed on the n (or i) -GaAs protective layer 49 divided into two.

The two-dimensional electron gas 44 is formed in the i-InGaAs channel layer 43 by the n-InAlAs electron supply layer 45, and the electrons in the two-dimensional electron gas 44 are controlled by the potential of the gate electrode 50. By moving between the source electrode 51 and the drain electrode 52, an amplification action and a switching action are generated.

Further, the i-InAlAs buffer layer 42,
As the HEMT region 53 including the i-InGaAs channel layer 43 and the n-InAlAs electron supply layer 45, various modifications can be considered.

In this embodiment, n-InGaAs ohmic layer 48, which is originally the uppermost layer, has n
(Or i) a -GaAs protective layer 49 is formed;
It is originally under the gate electrode 50,
An n (or i) -GaAs protective layer 46 is formed on the surface of the n-InAlAs electron supply layer 45 exposed around
Since it is shielded from the external atmosphere, formation of a metamorphic layer on the surface of these layers is suppressed, and deterioration in characteristics such as a decrease in gate breakdown voltage is reduced.

In this embodiment, n-In
The lattice constant of the GaAs ohmic layer 48 is
Is larger than the lattice constant of the InP substrate 41,
An n-InAlAs layer 47 lattice-matched with the nP substrate 41 is interposed, and n (or i) -Ga having a thickness of 20 ° is formed on both sides thereof.
As protective layer 46, n (or i) -GaAs protective layer 49
By disposing the layers, the stress is balanced and the occurrence of dislocations in the adjacent crystal layer is suppressed.

(Fourth Embodiment) FIG. 4 shows the In embodiment of the fourth embodiment.
FIG. 3 is an explanatory diagram of a configuration of a P-based HEMT. In this figure, 6
1 is an InP substrate, 62 is an i-InAlAs buffer layer,
63 is an i-InGaAs channel layer, 64 is a two-dimensional electron gas, 65 is an n-InAlAs electron supply layer, and 66 is n
(Or i) -GaAs protective layer, 67 is n-InGaAs
An ohmic layer, 68 is an n (or i) -GaAs protective layer, 69 is a gate electrode, 70 is a source electrode, 71 is a drain electrode, 72 is a HEMT region, and 73 is an ohmic region.

In the InP-based HEMT of this embodiment, an i-InAlAs buffer layer 62, an i-InGaAs channel layer 63, an n-InA
The HEAs region 72 is formed by growing the GaAs electron supply layer 65, and the n-GaAs protective layer 6 having a thickness of 100 ° is formed thereon.
6, an n-InGaAs ohmic layer 67 having a thickness of 200 °, an impurity concentration of 3 × 10 ¹⁸ cm ^-3 and a molar ratio of InAs of 0.75, and an n-GaAs protective layer 68 having a thickness of 200 °.
Is formed to form an ohmic region 73, and the n-GaAs protective layer 68, n-
The InGaAs ohmic layer 67 is removed by etching in a strip shape, a gate electrode 69 is formed on the exposed n-GaAs protective layer 66, and the n-GaAs protective layer 6 is divided into two.
A source electrode 70 and a drain electrode 71 are formed on 8.

The i-InGaAs channel layer 63
Then, a two-dimensional electron gas 64 is formed by the n-InAlAs electron supply layer 65, and electrons in the two-dimensional electron gas 64 are controlled by the potential of the gate electrode 69 and move between the source electrode 70 and the drain electrode 71. Thus, an amplifying action or a switching action is generated as in the above-described embodiments.

Further, the i-InAlAs buffer layer 62,
As in the above embodiments, the HEMT region 72 including the i-InGaAs channel layer 63 and the n-InAlAs electron supply layer 65 can take various modifications.

[0034] In this embodiment, the surface of the n-In Ga As ohmic layer 67 is the top layer if originally
An n-GaAs protective layer 68 is formed, and an n-GaAs protective layer 68 is formed on the surface of the n-InAlAs electron supply layer 65 which is originally under the gate electrode 69 and is exposed around the gate electrode 69.
Since the aAs protective layer 66 is formed and is shielded from the external atmosphere, formation of a metamorphic layer on the surface of these layers is suppressed, and characteristic deterioration such as reduction in gate breakdown voltage is reduced.

In this embodiment, n-In
The GaAs ohmic layer 67 has a lattice constant of InP substrate 61.
N-GaAs larger than the lattice constant of
Since the thickness of the s protective layer 68 is 200 ° and the thickness of the n-GaAs protective layer 66 is as thick as 100 °, n-In Ga A
Dislocation occurs in the s-ohmic layer 67, but since this layer has a function for ohmic connection, its deterioration in characteristics is relatively small. Is significant, n-GaAs
By increasing the thickness of the s protective layer 68 and the n-GaAs protective layer 66, it is possible to give priority to measures for preventing a metamorphic layer.

[0036]

As described above, according to the present invention,
InA exposed under the top layer of the device or under the gate electrode
Ga is formed on a semiconductor layer containing In or Al such as
The formation of the As layer and shielding from the external atmosphere prevents the formation of a metamorphic layer on the surface of the semiconductor layer containing In or Al due to the atmosphere exposed during the manufacture or use of these semiconductor devices. In addition, it is possible to provide a field effect semiconductor device such as a HEMT in which an InAlAs / InGaAs structure is formed on an InP substrate having excellent high-speed performance, which can prevent deterioration with time of characteristics such as a decrease in gate withstand voltage.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a configuration of an InP-based HEMT of a first embodiment.

FIG. 2 is an explanatory diagram of a configuration of an InP-based HEMT according to a second embodiment.

FIG. 3 is an explanatory diagram of a configuration of an InP-based HEMT according to a third embodiment.

FIG. 4 is a diagram illustrating the configuration of an InP-based HEMT according to a fourth embodiment.

[Explanation of symbols]

 Reference Signs List 1 InP substrate 2 i-InAlAs buffer layer 3 i-InGaAs channel layer 4 two-dimensional electron gas 5 n-InAlAs electron supply layer 6 n (or i) -GaAs protective layer 7 n-InGaAs ohmic layer 8 n (or i)- GaAs protective layer 9 gate electrode 10 source electrode 11 drain electrode 12 HEMT region 13 ohmic region

Continued on the front page (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/337 H01L 21/338 H01L 27/095 H01L 29/778 H01L 29/80 H01L 29/808 H01L 29/812

Claims (2)

(57) [Claims] 1. An InP substrate from a side close to the InP substrate.
GaAs protective layer / InGaAs layer / GaAs
A layered structure of a protective layer made of InP is provided, and the composition of the InGaAs layer has a lattice constant compared to that of InP.
Large and totally dislocations are not introduced into the semiconductor crystal.
It is necessary to maintain the balance of stress
InP-based field effect semiconductor device comprising and. 2. On an InP substrate, from a side close to the InP substrate.
GaAs protective layer / InGaAs layer / GaAs
A layered structure of a protective layer is provided, and the thickness of each semiconductor layer of the layered structure is arbitrarily determined to be half.
I characterized in that dislocations are introduced into the conductor crystal.
nP-based field effect semiconductor device.