JP2006308922A - Display device and its manufacturing method - Google Patents
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本発明は、薄膜トランジスタ（以下「ＴＦＴ」という。）を用いたインクジェット法によるアクティブマトリクス型の液晶表示装置とその製造方法に関する。 The present invention relates to an active matrix liquid crystal display device using an inkjet method using a thin film transistor (hereinafter referred to as “TFT”) and a method for manufacturing the same.
従来、液晶パネルのＴＦＴ製造において、以下（１）から（７）のようなフローで、インクジェット法による配線形成法が開発されている。（１）光透過型感光性樹脂の塗布、（２）光透過型感光性樹脂のパターニング（露光及び現像）、（３）光透過型感光性樹脂のポストベーク、（４）光透過型感光性樹脂の撥液処理、（５）インクジェット塗布パターン部の親液処理、（６）インクジェット塗布、（７）インクジェット塗布されたインクの乾燥・焼成。 2. Description of the Related Art Conventionally, in the manufacture of TFTs for liquid crystal panels, a wiring formation method using an ink jet method has been developed in the following flows (1) to (7). (1) Application of light transmission type photosensitive resin, (2) Patterning (exposure and development) of light transmission type photosensitive resin, (3) Post baking of light transmission type photosensitive resin, (4) Light transmission type photosensitivity. Liquid repellent treatment of resin, (5) lyophilic treatment of ink jet coating pattern part, (6) ink jet coating, (7) drying and baking of ink applied by ink jet.
これについて、図９を用いて説明する。同図（ａ）において、絶縁基板５１上に光透過型感光性樹脂５２を塗布し、この光透過型感光性樹脂５２をパターニング・ポストベーク・撥液処理し、また、光透過型感光性樹脂５２の開口部（ゲート配線１０１部及び補助容量配線３０１部）に当たる絶縁基板５１を親液処理する。次に、同図（ｂ）に示すように、光透過型感光性樹脂５２の開口部にインクジェット塗布によるインク１０１’を滴下する。この際、インク１０１’の盛り込み量は配線幅Ｗと接触角θにより決まってしまう。最後に、同図（ｃ）に示すように、インク１０１’の溶媒を蒸発・乾燥・焼成してゲート配線１０１（補助容量配線３０１）が形成される。ここで、インク１０１’は、低濃度のメタルを含有するインクであるため、ゲート配線１０１の膜厚を厚く形成することができない。 This will be described with reference to FIG. In FIG. 5A, a light-transmitting photosensitive resin 52 is applied on an insulating substrate 51, and the light-transmitting photosensitive resin 52 is subjected to patterning, post-baking, and liquid repelling treatment. The insulating substrate 51 corresponding to the opening 52 (the gate wiring 101 and the auxiliary capacitance wiring 301) is subjected to lyophilic treatment. Next, as shown in FIG. 4B, ink 101 ′ by inkjet coating is dropped into the opening of the light transmitting photosensitive resin 52. At this time, the filling amount of the ink 101 ′ is determined by the wiring width W and the contact angle θ. Finally, as shown in FIG. 5C, the gate wiring 101 (auxiliary capacitance wiring 301) is formed by evaporating, drying and baking the solvent of the ink 101 '. Here, since the ink 101 ′ is an ink containing a low-concentration metal, the gate wiring 101 cannot be formed thick.
なお、下記特許文献には、ＴＦＴのゲート電極膜を、導電材料を含有する液体材料を用いて、インクジェット法によって形成し、また、ＴＦＴのソース領域及びドレイン領域を、半導体材料を含有する液体材料を用いて、インクジェット法によって形成することが記載されている。 In the following patent document, a TFT gate electrode film is formed by an ink jet method using a liquid material containing a conductive material, and a source material and a drain region of the TFT are made of a liquid material containing a semiconductor material. And forming by an ink jet method.
液晶表示装置の製造におけるインクジェット法には、以下（１）から（３）の課題がある。（１）インクジェット塗布法では、所定粘度以下の低濃度のメタル含有インクしか適用できない。（２）光透過型感光性樹脂の撥液性にも限界があり、溢れなく塗布できるインク量に限界がある。（３）形成できる膜厚に限界があり、特に、細線幅時の所定の膜厚作製が複雑・困難である。 The inkjet method in manufacturing a liquid crystal display device has the following problems (1) to (3). (1) In the ink jet coating method, only low concentration metal-containing ink having a predetermined viscosity or less can be applied. (2) The liquid repellency of the light-transmitting photosensitive resin is also limited, and the amount of ink that can be applied without overflow is limited. (3) There is a limit to the film thickness that can be formed, and it is particularly difficult and difficult to produce a predetermined film thickness at the time of fine line width.
そこで、本発明においては、隣接する配線を対にして接近させることにより、インクジェット液滴塗布時の実質配線幅を増加して、実質盛り込み量を増加させることにより、従来と同じ配線幅で、２倍以上のより厚い膜厚の配線が得られる。 Therefore, in the present invention, the adjacent wirings are brought close to each other to increase the substantial wiring width at the time of applying the ink jet droplets and increase the substantial filling amount. A wiring with a film thickness that is twice or more thicker can be obtained.
このような方法を採用することにより、インクジェットに適した低濃度インクを用いた場合でも、１回のインクジェト塗布処理で細線厚膜形成が可能となる。 By adopting such a method, even when a low-density ink suitable for inkjet is used, a thin thick film can be formed by a single inkjet coating process.
以下、図面を用いて、本発明の実施例を説明する。 Embodiments of the present invention will be described below with reference to the drawings.
図１（ａ）は、本発明に係るアクティブマトリクス型の液晶表示装置の概略図、図１（ｂ）は、図１（ａ）に示す画素部３００の拡大図である。 FIG. 1A is a schematic view of an active matrix liquid crystal display device according to the present invention, and FIG. 1B is an enlarged view of a pixel portion 300 shown in FIG.
図１（ａ）において、走査配線駆動回路１００によって選択されたゲート配線１０１に対応して、データ配線駆動回路２００からソース配線２０１を介して表示パネル４００の画素部３００におけるＴＦＴ１０にデータ（電圧）が供給される。 In FIG. 1A, data (voltage) is applied to the TFT 10 in the pixel portion 300 of the display panel 400 from the data wiring driving circuit 200 via the source wiring 201 corresponding to the gate wiring 101 selected by the scanning wiring driving circuit 100. Is supplied.
図１（ｂ）において、ＴＦＴ１０は、ゲート配線１０１とソース配線２０１との交差部に設けられ、ＴＦＴ１０のゲート電極１１には、ゲート配線１０１が接続され、ＴＦＴ１０のソース電極（又はドレイン電極）１２には、ソース配線２０１が接続されている。 In FIG. 1B, the TFT 10 is provided at the intersection of the gate wiring 101 and the source wiring 201, the gate wiring 101 is connected to the gate electrode 11 of the TFT 10, and the source electrode (or drain electrode) 12 of the TFT 10. Is connected to a source wiring 201.
ＴＦＴ１０のドレイン電極（又はソース電極）１３は、液晶素子２０の画素電極２１に接続され、液晶素子２０は、画素電極２１と共通電極２２との間にあって、画素電極２１に供給されるデータ(電圧)により駆動される。なお、データを一時保持するための補助容量３０が、ドレイン電極１３と補助容量配線３０１との間に接続されている。 The drain electrode (or source electrode) 13 of the TFT 10 is connected to the pixel electrode 21 of the liquid crystal element 20, and the liquid crystal element 20 is between the pixel electrode 21 and the common electrode 22 and is supplied with data (voltage) supplied to the pixel electrode 21. ). A storage capacitor 30 for temporarily storing data is connected between the drain electrode 13 and the storage capacitor wiring 301.
図２は、図１に示す表示パネル４００における画素部３００の平面図とＴＦＴ１０の断面図であって、同図（ａ）は、図１に示すマトリクス状に配置された画素部３００の平面図、同図（ｂ）は、同図（ａ）に示す画素部３００におけるＴＦＴ１０の点線Ａ−Ａ’部の断面図である。 2 is a plan view of the pixel portion 300 and a cross-sectional view of the TFT 10 in the display panel 400 shown in FIG. 1. FIG. 2A is a plan view of the pixel portion 300 arranged in a matrix form shown in FIG. FIG. 4B is a cross-sectional view taken along the dotted line AA ′ of the TFT 10 in the pixel unit 300 shown in FIG.
図２（ａ）において、マトリクス状に配置された画素部３００には、ＴＦＴ１０がゲート配線１０１とソース配線２０１との交差部に配置されている。また、画素電極２１がＴＦＴ１０に接続され、補助容量配線３０１との間で補助容量を形成している。 In FIG. 2A, in the pixel portion 300 arranged in a matrix, the TFT 10 is arranged at the intersection of the gate wiring 101 and the source wiring 201. Further, the pixel electrode 21 is connected to the TFT 10 and forms an auxiliary capacitance with the auxiliary capacitance wiring 301.
図２（ｂ）において、ＴＦＴ１０は、以下のようにして形成される。まず、絶縁基板５１上の第１の光透過型感光性樹脂５２の開口部に、金属微粒子を含有するインクを用いたインクジェット塗布により、ゲート電極１１が形成される。次に、これらゲート電極１１及び第１の光透過型感光性樹脂５２上に、平坦なゲート絶縁膜５３を形成し、さらに、このゲート絶縁膜５３上に、半導体層５４、オーミックコンタクト層５５及び半導体層５４の保護膜５６を形成する。最後に、第２の光透過型感光性樹脂５７の開口部に、金属微粒子を含有するインクを用いたインクジェット塗布により、ソース電極１２及びドレイン電極１３が形成される。 In FIG. 2B, the TFT 10 is formed as follows. First, the gate electrode 11 is formed in the opening portion of the first light transmission type photosensitive resin 52 on the insulating substrate 51 by ink jet application using ink containing metal fine particles. Next, a flat gate insulating film 53 is formed on the gate electrode 11 and the first light transmission type photosensitive resin 52, and further, a semiconductor layer 54, an ohmic contact layer 55, and the like are formed on the gate insulating film 53. A protective film 56 for the semiconductor layer 54 is formed. Finally, the source electrode 12 and the drain electrode 13 are formed in the opening of the second light transmission type photosensitive resin 57 by inkjet coating using an ink containing metal fine particles.
図３（ａ）は、図２（ｂ）に示す絶縁基板５１上に形成した第１の光透過型感光性樹脂５２のパターン図であって、第１の光透過型感光性樹脂５２の開口部に、まだ、インクジェット塗布によるゲート電極１１、ゲート配線１０１及び補助容量配線３０１が形成されていない状態を示す。また、同図は、２つのゲート配線１０１を隣接配置して形成しようとするもので、符号３００，３００’は画素部を示す。 FIG. 3A is a pattern diagram of the first light transmission type photosensitive resin 52 formed on the insulating substrate 51 shown in FIG. 2B, and the opening of the first light transmission type photosensitive resin 52. A state where the gate electrode 11, the gate wiring 101, and the auxiliary capacitance wiring 301 are not yet formed in the portion is shown. In the figure, two gate wirings 101 are arranged adjacent to each other, and reference numerals 300 and 300 'denote pixel portions.
図３（ｂ）（ｃ）（ｄ）は、図３（ａ）に示す点線Ａ−Ａ’部の断面図であって、まず、同図（ｂ）において、撥液処理された第１の光透過型感光性樹脂５２の表面に、インクジェット塗布による低濃度の金属微粒子を含有するインク１０１’が、親液処理された絶縁基板５１に滴下される。次に、インク１０１’の溶媒を蒸発・乾燥させると、同図（ｃ）に示すように、捨て領域５２’を境界として、インク１０１’が分離される。このときインク１０１’は、結果的に、高濃度の金属微粒子を含有することになる。最後に、この高濃度のインク１０１’’を乾燥・焼成させると、同図（ｃ）に示すように、膜厚が従来の膜厚より２倍以上の膜厚のゲート配線１０１が形成される。なお、捨て領域５２’は、表示パネル４００の全領域を有効に活用する観点からみると、捨てる領域となる。この捨て領域５２’の幅は、ホトリソグラフィー技術の限界である５μｍとし、この幅を介して対のゲート配線１０１同士の橋絡を防止するために、捨て領域５２’について残メタル処理（ライトエッチング）を行う。 FIGS. 3B, 3C, and 3D are cross-sectional views taken along the dotted line AA ′ shown in FIG. 3A. First, in FIG. On the surface of the light-transmitting photosensitive resin 52, an ink 101 ′ containing low-concentration metal fine particles by inkjet coating is dropped onto the insulating substrate 51 that has been subjected to lyophilic treatment. Next, when the solvent of the ink 101 'is evaporated and dried, the ink 101' is separated with the disposal area 52 'as a boundary, as shown in FIG. At this time, as a result, the ink 101 ′ contains a high concentration of fine metal particles. Finally, when this high-concentration ink 101 '' is dried and fired, as shown in FIG. 5C, the gate wiring 101 having a film thickness twice or more that of the conventional film thickness is formed. . The discard area 52 ′ is an area to be discarded from the viewpoint of effectively using the entire area of the display panel 400. The width of the discarded region 52 ′ is set to 5 μm, which is the limit of the photolithography technology. In order to prevent a bridge between the pair of gate wirings 101 through this width, the remaining metal processing (light etching) is performed on the discarded region 52 ′. )I do.
このようにして形成された図３（ｄ）に示すゲート配線１０１の膜厚は、図９（ｃ）に示す従来のゲート配線１０１の膜厚の２倍以上となる。 The film thickness of the gate wiring 101 shown in FIG. 3D formed in this way is twice or more the film thickness of the conventional gate wiring 101 shown in FIG. 9C.
図４（ａ）は、絶縁基板５１上に形成した第１の光透過型感光性樹脂５２のパターン図であって、ゲート配線１０１を対とした図３（ａ）に示すものにおいて、さらに、補助容量配線３０１を対としたもので、点線Ｂ−Ｂ’部の断面図は、点線Ａ−Ａ’部の断面図と同様である。 FIG. 4A is a pattern diagram of the first light transmission type photosensitive resin 52 formed on the insulating substrate 51. In the pattern diagram shown in FIG. The auxiliary capacitance wiring 301 is a pair, and the cross-sectional view of the dotted line BB ′ portion is the same as the cross-sectional view of the dotted line AA ′ portion.
図４（ｂ）は、同じく絶縁基板５１上に形成した第１の光透過型感光性樹脂５２のパターン図であって、ゲート配線１０１と補助容量配線３０１とを対にしたものである。 FIG. 4B is a pattern diagram of the first light transmission type photosensitive resin 52 similarly formed on the insulating substrate 51, and is a pair of the gate wiring 101 and the auxiliary capacitance wiring 301.
図５は、図２（ｂ）に示す第２の光透過型感光性樹脂５７のパターン図であって、オーミックコンタクト層５５上の第２の光透過型感光性樹脂５７の開口部に、まだ、インクジェット塗布によるソース電極１２、ドレイン電極１３及びソース配線２０１が形成されていない状態を示す。また、同図は、２つのソース配線２０１を隣接配置して形成しようとするもので、符号３００，３００’は画素部を示す。同図においても、図３（ｂ）（ｃ）（ｄ）に示す手順によって、対のソース配線２０１が形成される。 FIG. 5 is a pattern diagram of the second light transmissive photosensitive resin 57 shown in FIG. 2B, and is still in the opening of the second light transmissive photosensitive resin 57 on the ohmic contact layer 55. The state in which the source electrode 12, the drain electrode 13, and the source wiring 201 are not formed by inkjet coating is shown. In the figure, two source wirings 201 are arranged adjacent to each other, and reference numerals 300 and 300 'denote pixel portions. Also in this figure, a pair of source wirings 201 is formed by the procedure shown in FIGS. 3B, 3C, and 3D.
図６は、同じく第２の光透過型感光性樹脂５７のパターン図であって、図５と異なるのは、ゲート配線１０１と補助容量配線３０１とを対にしたもので、対のソース配線２０１とすることは同じである。 FIG. 6 is also a pattern diagram of the second light transmission type photosensitive resin 57, and is different from FIG. 5 in that the gate wiring 101 and the auxiliary capacitance wiring 301 are paired, and the pair of source wirings 201. Is the same.
図７は、同じく第２の光透過型感光性樹脂５７のパターン図であって、対のソース配線２０１とすると共に、ゲート配線１０１を対とするものである。 FIG. 7 is also a pattern diagram of the second light transmission type photosensitive resin 57, which is a pair of source wiring 201 and a pair of gate wiring 101.
図８は、同じく第２の光透過型感光性樹脂５７のパターン図であって、図７と異なるのは、補助容量配線３０１を対にしたもので、対のソース配線２０１と対のゲート配線１０１とすることは同じである。 FIG. 8 is also a pattern diagram of the second light transmission type photosensitive resin 57, and is different from FIG. 7 in that the auxiliary capacitance wiring 301 is paired, and a pair of source wiring 201 and a pair of gate wiring. 101 is the same.
１０…薄膜トランジスタ（ＴＦＴ）、１１…ゲート電極、１２…ソース電極（又はドレイン電極）、１３…ドレイン電極（又はソース電極）、２０…液晶素子、２１…画素電極、２２…共通電極、３０…補助容量、５１…絶縁基板、５２…第１の光透過型感光性樹脂、５２’…捨て領域、５３…ゲート絶縁膜、５４…半導体層、５５…オーミックコンタクト層、５６…保護膜、５７…第２の光透過型感光性樹脂、１０１’，１０１’’…インク、７２…痕跡部、１００…走査配線駆動回路、１０１…ゲート配線、２００…データ配線駆動回路、２０１…ソース配線、３００，３００’…画素部、３０１…補助容量配線、４００…表示パネル
DESCRIPTION OF SYMBOLS 10 ... Thin-film transistor (TFT), 11 ... Gate electrode, 12 ... Source electrode (or drain electrode), 13 ... Drain electrode (or source electrode), 20 ... Liquid crystal element, 21 ... Pixel electrode, 22 ... Common electrode, 30 ... Auxiliary Capacitance 51 ... Insulating substrate 52 ... First light transmission type photosensitive resin 52 '... Disposal region 53 ... Gate insulating film 54 ... Semiconductor layer 55 ... Ohmic contact layer 56 ... Protective film 57 ... First Two light transmission type photosensitive resins, 101 ', 101''... ink, 72 ... trace part, 100 ... scanning wiring drive circuit, 101 ... gate wiring, 200 ... data wiring driving circuit, 201 ... source wiring, 300, 300 '... Pixel unit, 301 ... Auxiliary capacitance wiring, 400 ... Display panel
Claims (4)
前記薄膜トランジスタをマトリクス状に配置し、前記薄膜トランジスタのドレイン電極に接続された画素電極と第１の光透過型感光性樹脂の開口部に形成された補助容量配線との間で形成される補助容量と、前記薄膜トランジスタのゲート電極に接続される第１の光透過型感光性樹脂の開口部に形成されたゲート配線と、前記薄膜トランジスタのソース電極に接続される第２の光透過型感光性樹脂の開口部に形成されたソース配線とを備えた液晶表示装置において、
前記補助容量配線、ゲート配線、ソース配線の少なくとも１つを対とするか、又は、前記補助容量配線とゲート配線とを対として、インクジェット塗布による対配線を形成することを特徴とする液晶表示装置 A gate electrode formed in the opening of the first light transmission type photosensitive resin on the insulating substrate, a gate insulating film formed thereon, a semiconductor layer sequentially formed on the gate insulating film, and a separation An ohmic contact layer, a protective film protecting the semiconductor layer between the separated ohmic contact layers, and a source electrode and a drain electrode formed in the opening of the second light transmission type photosensitive resin. A thin film transistor;
An auxiliary capacitance formed between the pixel electrode connected to the drain electrode of the thin film transistor and an auxiliary capacitance wiring formed in the opening of the first light transmission type photosensitive resin, the thin film transistors being arranged in a matrix; The gate wiring formed in the opening of the first light transmission type photosensitive resin connected to the gate electrode of the thin film transistor, and the opening of the second light transmission type photosensitive resin connected to the source electrode of the thin film transistor In a liquid crystal display device provided with a source wiring formed in the part,
A liquid crystal display device, wherein at least one of the auxiliary capacitance line, the gate line, and the source line is paired, or the auxiliary capacitance line and the gate line are paired to form a pair line by ink jet coating.
前記薄膜トランジスタをマトリクス状に配置し、前記薄膜トランジスタのドレイン電極に接続された画素電極と第１の光透過型感光性樹脂の開口部に形成された補助容量配線との間で形成される補助容量と、前記薄膜トランジスタのゲート電極に接続される第１の光透過型感光性樹脂の開口部に形成されたゲート配線と、前記薄膜トランジスタのソース電極に接続される第２の光透過型感光性樹脂の開口部に形成されたソース配線とを備えた液晶表示装置の製造方法において、
前記補助容量配線、ゲート配線、ソース配線の少なくとも１つを対とするか、又は、前記補助容量配線とゲート配線とを対として、前記第１，２の光透過型感光性樹脂をパターニング、ポストベーク、撥液処理し、前記パターニング部分を親液処理した後に、インクジェット塗布による対配線を形成することを特徴とする液晶表示装置の製造方法 A gate electrode formed in the opening of the first light transmission type photosensitive resin on the insulating substrate, a gate insulating film formed thereon, a semiconductor layer sequentially formed on the gate insulating film, and a separation An ohmic contact layer, a protective film protecting the semiconductor layer between the separated ohmic contact layers, and a source electrode and a drain electrode formed in the opening of the second light transmission type photosensitive resin. A thin film transistor;
An auxiliary capacitance formed between the pixel electrode connected to the drain electrode of the thin film transistor and an auxiliary capacitance wiring formed in the opening of the first light transmission type photosensitive resin, the thin film transistors being arranged in a matrix; The gate wiring formed in the opening of the first light transmission type photosensitive resin connected to the gate electrode of the thin film transistor, and the opening of the second light transmission type photosensitive resin connected to the source electrode of the thin film transistor In a manufacturing method of a liquid crystal display device provided with a source wiring formed in a part,
Patterning and posting the first and second light-transmitting photosensitive resins using at least one of the auxiliary capacitance wiring, the gate wiring, and the source wiring as a pair, or using the auxiliary capacitance wiring and the gate wiring as a pair A method of manufacturing a liquid crystal display device, comprising: baking, lyophobic treatment, and lyophilic treatment of the patterning portion;
3. The method of manufacturing a liquid crystal display device according to claim 2, wherein light etching of the surface is performed after the formation of the counter wiring by ink jet coating.
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| JP2005132451A JP4341054B2 (en) | 2005-04-28 | 2005-04-28 | Liquid crystal display device and manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7868959B2 (en) | 2006-11-21 | 2011-01-11 | Hitachi Displays, Ltd. | Liquid crystal display device having common electrodes formed over the main face of an insulating substrate and made of a coating type electroconductive film inside a bank to regulate the edges thereof |
| US8537296B2 (en) | 2008-06-11 | 2013-09-17 | Samsung Display Co., Ltd. | Display device wherein a thickness of a first insulating layer is greater than a thickness of a first conductor and wherein the first insulating layer completely covers lateral side surfaces of the first conductor |
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2005
- 2005-04-28 JP JP2005132451A patent/JP4341054B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7868959B2 (en) | 2006-11-21 | 2011-01-11 | Hitachi Displays, Ltd. | Liquid crystal display device having common electrodes formed over the main face of an insulating substrate and made of a coating type electroconductive film inside a bank to regulate the edges thereof |
| US8537296B2 (en) | 2008-06-11 | 2013-09-17 | Samsung Display Co., Ltd. | Display device wherein a thickness of a first insulating layer is greater than a thickness of a first conductor and wherein the first insulating layer completely covers lateral side surfaces of the first conductor |
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| JP4341054B2 (en) | 2009-10-07 |
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