JP2006303005A - Process for fabricating semiconductor device and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a process for fabricating a semiconductor device in which generation of stress can be controlled at the upper end of sidewall of a trench. <P>SOLUTION: The process for fabricating a semiconductor device comprises a step for forming a trench 1a in a semiconductor substrate 1, a step for forming a thermal oxidation film 1b on the sidewall of the trench 1a, a step for burying a first insulation film 2 having a surface lower than that of the semiconductor substrate 1 in the trench 1a, and a step for introducing at least one of fluorine and nitrogen into the semiconductor substrate 1 located at the upper end of sidewall of the trench 1a. The first insulation film 2 is an isolation film, for example. The step for introducing at least one of fluorine and nitrogen may be followed by a step for forming a second insulation film 15 on the first insulation film 2 locate in the trench 1a, and a step for forming a sidewall covering the upper part of sidewall of the trench 1a by etching back the second insulation film 15. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device in which an insulator is embedded in a groove of a semiconductor substrate. In particular, the present invention relates to a method for manufacturing a semiconductor device and a semiconductor device capable of suppressing the generation of stress at the upper end of a sidewall of a groove.

6A to 6C are cross-sectional views for explaining a conventional method for manufacturing a semiconductor device.
First, as shown in FIG. 6A, a silicon oxide film 112 and a silicon nitride film 113 are formed in this order over a silicon substrate 101. Next, openings are formed in the silicon nitride film 113 and the silicon oxide film 112. Next, the silicon substrate 101 is etched using the silicon nitride film 113 as a mask. As a result, a groove 101 a is formed in the silicon substrate 101.

  Next, a thermal oxide film 101b is formed on the sidewall of the groove 101a. Thereby, the corner | angular part of the groove | channel 101a becomes round. Next, a silicon oxide film 102a is formed in the trench 101a and on the silicon nitride film 113 by a CVD method.

Next, as shown in FIG. 6B, the silicon oxide film 102a and the silicon nitride film 113 located on the silicon nitride film 113 are polished and removed by a CMP method. At this time, a little silicon nitride film 113 is left. Next, the remaining silicon nitride film 113 and silicon oxide film 112 are removed by etching. As a result, the element isolation film 102 is embedded in the silicon substrate 101. At this time, a depression is formed in the peripheral portion of the element isolation film 102. (For example, refer to Patent Document 1).
Japanese Patent Application Laid-Open No. 2004-281691 (FIGS. 5 to 7)

  Next, as shown in FIG. 6C, the gate oxide film 103 is formed by thermally oxidizing the silicon substrate 101. Next, a polysilicon film is formed on the entire surface including on the gate oxide film 103, and this polysilicon film is patterned. As a result, a gate electrode 104 is formed on the gate oxide film 103. Next, low-concentration impurity regions 106a and 106b, sidewalls 105, and impurity regions 107a and 107b to be a source and a drain are formed.

In the above structure, stress is generated at the interface between the thermal oxide film and the semiconductor substrate on the side wall of the groove. This stress tends to concentrate on the upper end portion of the groove sidewall (portion 101c in FIG. 6C).
In addition, when forming the gate oxide film, water and oxygen which are oxidizing species permeate through the element isolation film. For this reason, when the gate oxide film is formed, the thermal oxide film formed on the sidewall of the trench becomes thick, and the stress applied to the upper end portion of the trench sidewall increases.

If stress concentrates on the upper end of the side wall of the groove, a defect may occur in the semiconductor substrate located at the upper end. Since the upper end portion of the groove is a portion in direct contact with a semiconductor device such as a transistor, if a defect occurs in this portion, the characteristics of the semiconductor device deteriorate.
For this reason, it is necessary to suppress the generation of stress at the interface between the thermal oxide film and the semiconductor substrate at the upper end of the side wall of the groove.

  The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device capable of suppressing the generation of stress at the upper end portion of the side wall of a groove in which an insulator is embedded. Is to provide.

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a groove on a semiconductor substrate,
Forming a thermal oxide film on the side wall of the groove;
Burying a first insulating film whose surface is lower than the surface of the semiconductor substrate in the groove;
Introducing at least one of fluorine and nitrogen into the semiconductor substrate located at the upper end of the side wall of the groove.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming a mask film having an opening on a semiconductor substrate,
Etching the semiconductor substrate using the mask film as a mask to form a groove in the semiconductor substrate;
Forming a thermal oxide film on the side wall of the groove;
Forming a first insulating film on the mask film, in the opening, and in the groove;
Removing the upper portion of the first insulating film located on the mask film and in the opening, and the upper portion of the first insulating film located in the groove, and exposing the upper portion of the sidewall of the groove; and Removing the thermal oxide film located on top of the sidewall of the groove;
Introducing at least one of fluorine and nitrogen into the semiconductor substrate located at the upper end of the sidewall of the groove;
Forming a second insulating film on the first insulating film located in the trench;
Etching the second insulating film to form a sidewall covering the upper portion of the sidewall of the groove;
And a step of removing the mask film.

  When the mask film is a film in which a first mask film that is a silicon oxide film and a second mask film that is a silicon nitride film are stacked in this order, the step of removing the mask film includes the step of removing the mask film Removing the mask film; covering the first insulating film located in the trench; the sidewall; and the first mask film located around the trench with a resist film; and the resist Etching the first mask film using the film as a mask.

According to these semiconductor device manufacturing methods, at least one of fluorine and nitrogen is introduced into the semiconductor substrate located at the upper end of the side wall of the groove. For this reason, generation | occurrence | production of the stress in the upper end part of the side wall of a groove | channel is suppressed.
The first insulating film embedded in the trench is, for example, an element isolation film.

  After the step of introducing at least one of fluorine and nitrogen, a step of forming a second insulating film on the first insulating film located in the trench, and etching back the second insulating film And a step of forming a sidewall covering an upper portion of the side wall of the groove. The second insulating film is, for example, a silicon oxide film or a silicon nitride film.

  A step of forming a gate oxide film by thermally oxidizing the semiconductor substrate may be provided after the step of introducing at least one of fluorine and nitrogen. In the thermal oxidation process, the upper end portion of the sidewall of the groove is oxidized. Since at least one of fluorine and nitrogen is introduced into the oxidized portion, the generation of stress due to the oxidation is suppressed.

A semiconductor device according to the present invention includes: a groove formed in the semiconductor substrate;
A thermal oxide film formed on a sidewall of the groove;
A first insulating film embedded in the groove and having a lower surface than the surface of the semiconductor substrate;
Comprising
At least one of fluorine and nitrogen is introduced into the upper end of the side wall of the groove.

Another semiconductor device according to the present invention includes a semiconductor substrate,
A groove formed in the semiconductor substrate and separated from other regions of the element region;
A thermal oxide film formed on a sidewall of the groove;
An element isolation film embedded in the groove and having a lower surface than the surface of the semiconductor substrate;
A gate oxide film formed on the semiconductor substrate located in the element region;
Comprising
At least one of fluorine and nitrogen is introduced into the upper end of the side wall of the groove.

  These semiconductor devices may further include a sidewall formed on the surface of the first insulating film and covering an upper portion of the sidewall of the groove.

BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 and 2 are cross-sectional views for explaining a method for manufacturing a semiconductor device according to the first embodiment.

First, as shown in FIG. 1A, a silicon oxide film 12 as a pad film is formed on a silicon substrate 1 by a thermal oxidation method. Next, a silicon nitride film 13 is formed on the silicon oxide film 12 by a CVD method. The thickness of the silicon oxide film 12 is, for example, 5 nm or more and 20 nm or less, and the thickness of the silicon nitride film 13 is, for example, 100 nm or more and 300 nm or less. Next, a photoresist film (not shown) is applied on the silicon nitride film 13, and this photoresist film is exposed and developed. Thereby, a resist pattern is formed on the silicon nitride film 13. Next, the silicon nitride film 13 and the silicon oxide film 12 are etched using this resist pattern as a mask. Thereby, an opening 13 a is formed in the silicon nitride film 13 and the silicon oxide film 12. Next, the silicon substrate 1 is etched using the silicon nitride film 13 as a mask. Thereby, a groove 1 a is formed in the silicon substrate 1.
Thereafter, the resist pattern is removed.

  Next, the silicon substrate 1 is thermally oxidized. Thereby, the thermal oxide film 1b is formed on the side wall of the groove 1a, and the corner of the groove 1a is rounded. Next, a silicon oxide film is formed by CVD in each of the groove 1a and the opening 13a and on the entire surface including the silicon nitride film 13. Next, by performing CMP using the silicon nitride film 13 as a stopper, the silicon oxide film located on the silicon nitride film 13 is removed, and the upper surface of the silicon oxide film located in the trench 1a and the opening 13a is flattened. Turn into.

  Next, the silicon oxide film located in the opening 13a is removed by wet etching. In this way, the element isolation film 2 is embedded in the trench 1a. The upper surface of the element isolation film 2 is located below the surface of the silicon substrate 1.

  In this wet etching process, a portion of the silicon oxide film 12 serving as the pad film that faces the opening 13a is slightly removed. Thereby, the recessed part 12a is formed in the side surface of the opening part 13a. Further, the upper portion of the thermal oxide film 1b formed on the side wall of the groove 1a is removed, and the silicon substrate 1 is exposed on the upper side wall of the groove 1a.

  Next, as shown in FIG. 1B, at least one of fluorine ions or nitrogen ions is implanted into the silicon substrate 1 using the silicon nitride film 13 as a mask. As a result, a buffer region 1c into which at least one of fluorine ions and nitrogen ions is introduced is formed on the silicon substrate 1 located on the upper side wall (including the upper end) of the groove 1a.

  Next, as shown in FIG. 1C, a silicon oxide film 15 is formed on the entire surface including the element isolation film 2 located below the opening 13a by the CVD method. At this time, the CVD conditions are adjusted so that the silicon oxide film 15 is also embedded in the recess 12a.

  Next, as shown in FIG. 2A, the silicon oxide film 15 is etched back. As a result, a sidewall 2 a is formed on the periphery of the element isolation film 2 to cover the upper portion of the sidewall of the groove 1 a.

  Next, as shown in FIG. 2B, the silicon nitride film 13 is polished by a CMP method. At this time, the silicon nitride film 13 is left slightly on the silicon oxide film 12. Next, the remaining silicon nitride film 13 is removed by etching. Next, the silicon oxide film 12 is removed by etching.

  In this etching step, since the sidewall 2a is formed on the peripheral portion of the element isolation film 2, the formation of a depression in the peripheral portion of the element isolation film 2 in this step is suppressed.

  Next, as shown in FIG. 2C, the silicon substrate 1 is thermally oxidized. Thereby, a gate oxide film 3 is formed on the silicon substrate 1. In this step, since oxidized species such as water and oxygen permeate the sidewall 2a, the upper portion of the sidewall of the groove 1a is also oxidized to form a silicon oxide film 2b. However, the silicon oxide film 2b is formed in the buffer region 1c and contains the element (at least one of fluorine and nitrogen) introduced in the process shown in FIG. The upper end portion of the thermal oxide film 1b takes in the element (at least one of fluorine and nitrogen) introduced in the step shown in FIG. 1B from the buffer region 1c. Thereby, SiON, SiOF, or SiONF is formed in the upper end portion of the thermal oxide film 1b and the silicon oxide film 2b, respectively, and the generation of stress is suppressed in the upper end portion of the side wall of the groove 1a.

  Further, as described above, since the sidewall 2a is formed on the peripheral portion of the element isolation film 2, formation of a depression is suppressed. For this reason, it is possible to suppress the thinning of the end portion of the gate oxide film 3 as compared with the conventional case, and to suppress the generation of parasitic transistors.

  Next, a polysilicon film is formed on the entire surface including the gate oxide film 3, and this polysilicon film is patterned. Thereby, a gate electrode 4 is formed on the gate oxide film 3. Next, impurities are implanted into the silicon substrate 1 using the gate electrode 4 and the element isolation film 2 as a mask. Thereby, low-concentration impurity regions 6 a and 6 b are formed in the silicon substrate 1.

Next, a silicon oxide film is formed on the entire surface including the gate electrode 4, and this silicon oxide film is etched back. Thereby, the side wall of the gate electrode 4 is covered with the side wall 5. Next, impurities are implanted into the silicon substrate 1 using the gate electrode 4, the sidewall 5, and the element isolation film 2 as a mask. As a result, impurity regions 7 a and 7 b to be a source and a drain are formed in the silicon substrate 1.
In this way, a transistor is formed on the silicon substrate 1.

As described above, according to the first embodiment of the present invention, at least one of fluorine and nitrogen is introduced into the upper portion of the sidewall of the trench 1a in which the element isolation film 2 is embedded. For this reason, even if the silicon oxide film 2b is formed on the upper portion of the side wall of the groove 1a in the subsequent thermal oxidation process, the generation of stress at the upper end portion of the side wall of the groove 1a can be suppressed. In addition, since at least one of nitrogen and fluorine diffuses in the thermal oxide film 1b formed on the side wall of the groove 1a, the generation of stress at the upper end of the side wall of the groove 1a due to the thermal oxide film 1b can be suppressed.
For this reason, it is possible to suppress the occurrence of a leak current due to defects in the impurity regions 7a and 7b of the transistor. Therefore, deterioration of transistor characteristics is suppressed.

  Further, since the sidewall 2a is formed on the peripheral portion of the element isolation film 2, the formation of the depression is suppressed. For this reason, it is possible to suppress the thinning of the end portion of the gate oxide film 3 as compared with the conventional case, and to suppress the generation of parasitic transistors.

  Each drawing in FIG. 3 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the second embodiment. The semiconductor device manufactured according to this embodiment is the same as that of the first embodiment except that the sidewalls formed on the peripheral portion of the element isolation film are formed of silicon nitride. Hereinafter, the same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIG. 3A, a silicon oxide film 12 and a silicon nitride film 13 are formed on a silicon substrate 1, and an opening 13a is further formed. Next, the groove 1a, the thermal oxide film 1b, and the buffer region 1c are formed in the silicon substrate 1, and the element isolation film 2 is embedded in the groove 1a. Details of these steps are the same as those in the first embodiment.

  Next, a silicon nitride film 16 is formed on the entire surface including the element isolation film 2 located below the opening 13a by the CVD method. The thickness of the silicon nitride film 16 is, for example, not less than 50 nm and not more than 300 nm. At this time, the CVD conditions are adjusted so that the silicon nitride film 16 is also embedded in the recess 12a.

Next, as shown in FIG. 3B, the silicon nitride film 16 is etched back. As a result, a sidewall 2 a is formed on the periphery of the element isolation film 2. Further, the surface of the silicon nitride film 13 is also etched. In this state, the sidewall 2a is larger than the first embodiment (not shown).
Next, the silicon nitride film 13 is removed using the same method as in the first embodiment. In this step, the sidewall 2a becomes small.

  Next, as shown in FIG. 3C, a photoresist film is applied over the entire surface including the silicon oxide film 12, the sidewalls 2a, and the element isolation film 2, and the photoresist film is exposed and developed. Thereby, a resist pattern 50 is formed. The resist pattern 50 covers each of the sidewall 2a, the element isolation film 2, and the silicon oxide film 12 located around the sidewall 2a.

  Next, the silicon oxide film 12 is etched using the resist pattern 50 as a mask. As a result, the silicon oxide film 12 is removed except for portions located around the element isolation film 2.

  Thereafter, as shown in FIG. 3D, the resist pattern 50 is removed. Next, the gate oxide film 3 is formed by thermally oxidizing the silicon substrate 1. In this thermal oxidation process, since at least one of nitrogen and fluorine diffuses also in the thermal oxide film 1b formed on the sidewall of the groove 1a, stress is generated at the upper end of the sidewall of the groove 1a due to the thermal oxide film 1b. Can be suppressed. Further, since the sidewall 2a is formed on the peripheral portion of the element isolation film 2, the formation of the depression is suppressed. For this reason, it is possible to suppress the thinning of the end portion of the gate oxide film 3 as compared with the conventional case, and to suppress the generation of parasitic transistors.

Next, the gate electrode 4, the sidewall 5, the low concentration impurity regions 6a and 6b, and the impurity regions 7a and 7b are formed. These forming methods are the same as those in the first embodiment. In this way, a transistor is formed.
Thus, also in this embodiment, it is possible to suppress the occurrence of stress at the upper end portion of the side wall of the groove 1a due to the thermal oxide film 1b. Therefore, deterioration of transistor characteristics can be suppressed. Further, as compared with the conventional case, the thickness of the end portion of the gate oxide film 3 is suppressed, and the generation of parasitic transistors is suppressed.

  4 and 5 are cross-sectional views for explaining a method for manufacturing a semiconductor device according to the third embodiment. In the present embodiment, a first transistor having a high breakdown voltage and a second transistor having a lower breakdown voltage than the first transistor are formed on the same silicon substrate 1. Hereinafter, the same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIG. 4A, in each of the first element region 10a where the first transistor is formed and the second element region 10b where the second transistor is formed, a groove is formed in the silicon substrate 1. 1a is formed. Next, after forming the buffer region 1c, the element isolation film 2 is embedded in the groove 1a. Next, a sidewall 2 a is formed on the peripheral portion of the surface of the element isolation film 2. These steps are the same as those in the first embodiment. Since the sidewall 2a is formed on the peripheral portion of the element isolation film 2, the formation of a depression in the peripheral portion of the element isolation film 2 is suppressed.

Next, as shown in FIG. 4B, the silicon substrate 1 is thermally oxidized. As a result, the gate oxide film 3a of the first transistor is formed on the silicon substrate 1 located in the first element region 10a. Further, the silicon oxide film 3c is also formed on the silicon substrate located in the second element region 10b. Since the buffer region 1c is formed, the occurrence of stress at the upper end of the side wall of the groove 1a due to the thermal oxide film 1b is suppressed in this thermal oxidation step by the same action as in the first embodiment. The In addition, since the formation of depressions in the peripheral portion of the element isolation film 2 is suppressed, thinning of the end portion of the gate oxide film 3a is suppressed in this thermal oxidation process.
Note that the thickness of the gate oxide film 3a formed in this step is insufficient to withstand the operating voltage of the first transistor.

  Next, as shown in FIG. 4C, a photoresist film 51 is applied over the entire surface including the first element region 10a and the second element region 10b, and the photoresist film 51 is exposed and developed. As a result, the first element region 10a is covered with the photoresist film 51, but the photoresist film 51 is removed from the second element region 10b. Next, etching is performed using the photoresist film 51 as a mask to remove the silicon oxide film 3c located in the second element region 10b.

  Thereafter, as shown in FIG. 5A, the photoresist film 51 is removed. Next, the silicon substrate 1 is thermally oxidized again. As a result, the gate oxide film 3b of the second transistor is formed on the silicon substrate 1 located in the second element region 10b. Further, the gate oxide film 3a of the first transistor is also thickened and can withstand the operating voltage of the first transistor.

  Since the buffer region 1c is formed, the occurrence of stress at the upper end of the side wall of the groove 1a due to the thermal oxide film 1b is suppressed in this thermal oxidation step by the same action as in the first embodiment. The In addition, since the formation of depressions in the peripheral portion of the element isolation film 2 is suppressed, thinning of the end portions of the gate oxide films 3a and 3b is suppressed in this thermal oxidation process.

Next, as shown in FIG. 5B, in each of the first element region 10a and the second element region 10b, the gate electrode 4, the low-concentration impurity regions 6a and 6b, the sidewall 5, and the impurity regions 7a, 7b is formed. These forming methods are the same as those in the first embodiment.
In this manner, a high breakdown voltage transistor is formed in the first element region 10a, and a low breakdown voltage transistor is formed in the second element region 10b.

As described above, according to the present embodiment, stress is generated at the upper end of the side wall of the trench 1a due to the thermal oxide film 1b in the step of forming the gate oxide films 3a and 3b by the same operation as that of the first embodiment. Is suppressed. Therefore, deterioration of transistor characteristics is suppressed.
In addition, since the formation of depressions in the peripheral portion of the element isolation film 2 is suppressed, thinning of the end portions of the gate oxide films 3a and 3b is suppressed. Therefore, the generation of parasitic transistors is suppressed.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in the first embodiment, a silicon nitride film may be formed instead of the silicon oxide film 15. In the second embodiment, a silicon oxide film may be formed instead of the silicon nitride film 16. In the third embodiment, the method shown in the second embodiment may be used.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

(A) is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment, (B) is sectional drawing for demonstrating the next process of (A), (C) is (B). Sectional drawing for demonstrating the next process of. (A) is a cross-sectional view for explaining the next step of FIG. 1 (C), (B) is a cross-sectional view for explaining the next step of (A), and (C) is the next step of (B). Sectional drawing for demonstrating a process. (A) is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment, (B) is sectional drawing for demonstrating the next process of (A), (C) is (B). Sectional drawing for demonstrating the next process of (C), (D) is sectional drawing for demonstrating the next process of (C). (A) is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 3rd Embodiment, (B) is sectional drawing for demonstrating the next process of (A), (C) is (B). Sectional drawing for demonstrating the next process of. (A) is sectional drawing for demonstrating the next process of FIG.4 (C), (B) is sectional drawing for demonstrating the next process of (A). (A) is sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device, (B) is sectional drawing for demonstrating the next process of (A), (C) is the next process of (B). Sectional drawing for demonstrating.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 1a, 101a ... groove | channel, 1b, 101b ... thermal oxide film, 1c ... buffer region, 2,102 ... element isolation film, 2a ... peripheral part coating film, 3, 3a, 3b, 103 ... gate oxidation Film, 4, 104 ... Gate electrode, 5, 105 ... Side wall, 6a, 6b, 106a, 106b ... Low-concentration impurity region, 7a, 7b, 107a, 107b ... Impurity region, 10a ... First element region, 10b ... Second element region, 12, 14, 15, 112 ... silicon oxide film, 12a ... recess, 13, 16, 113 ... silicon nitride film, 50 ... resist pattern, 51 ... photoresist film

Claims (10)

Forming a groove on the semiconductor substrate;
Forming a thermal oxide film on the side wall of the groove;
Burying a first insulating film whose surface is lower than the surface of the semiconductor substrate in the groove;
Introducing at least one of fluorine and nitrogen into the semiconductor substrate located at the upper end of the sidewall of the groove;
A method for manufacturing a semiconductor device comprising: Forming a mask film having an opening on a semiconductor substrate;
Etching the semiconductor substrate using the mask film as a mask to form a groove in the semiconductor substrate;
Forming a thermal oxide film on the side wall of the groove;
Forming a first insulating film on the mask film, in the opening, and in the groove;
Removing the upper portion of the first insulating film located on the mask film and in the opening, and the upper portion of the first insulating film located in the groove, and exposing the upper portion of the sidewall of the groove; and Removing the thermal oxide film located on top of the sidewall of the groove;
Introducing at least one of fluorine and nitrogen into the semiconductor substrate located at the upper end of the sidewall of the groove;
Removing the mask film;
A method for manufacturing a semiconductor device comprising: The mask film is a film in which a first mask film that is a silicon oxide film and a second mask film that is a silicon nitride film are stacked in this order,
The step of removing the mask film includes
Removing the second mask film;
Covering the first insulating film located in the trench, the sidewall, and the first mask film located around the trench with a resist film;
Etching the first mask film using the resist film as a mask;
The manufacturing method of the semiconductor device of Claim 2 which comprises these. After the step of introducing at least one of fluorine and nitrogen,
Forming a second insulating film on the first insulating film located in the trench;
Etching the second insulating film to form a sidewall covering the upper portion of the sidewall of the groove;
The manufacturing method of the semiconductor device as described in any one of Claims 1-3 which comprises these.   The method for manufacturing a semiconductor device according to claim 4, wherein the sidewall is a silicon oxide film or a silicon nitride film.   The method for manufacturing a semiconductor device according to claim 1, wherein the first insulating film embedded in the groove is an element isolation film.   The method for manufacturing a semiconductor device according to claim 6, further comprising a step of forming a gate oxide film by thermally oxidizing the semiconductor substrate after the step of introducing at least one of fluorine and nitrogen. A semiconductor substrate;
A groove formed in the semiconductor substrate;
A thermal oxide film formed on a sidewall of the groove;
A first insulating film embedded in the groove and having a lower surface than the surface of the semiconductor substrate;
Comprising
A semiconductor device in which at least one of fluorine and nitrogen is introduced into an upper end portion of a side wall of the groove. A semiconductor substrate;
A groove formed in the semiconductor substrate and separated from other regions of the element region;
A thermal oxide film formed on a sidewall of the groove;
An element isolation film embedded in the groove and having a lower surface than the surface of the semiconductor substrate;
A gate oxide film formed on the semiconductor substrate located in the element region;
Comprising
A semiconductor device in which at least one of fluorine and nitrogen is introduced into an upper end portion of a side wall of the groove.   10. The semiconductor device according to claim 8, further comprising a sidewall formed on a surface of the first insulating film and covering an upper portion of a sidewall of the groove.

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