JP2006295208A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of components on a printed circuit by mounting a plurality of discrete electronic components on a semiconductor chip. <P>SOLUTION: The surface of the semiconductor chip in which a plurality of connection electrodes are provided is covered with a lower insulating film so that the connection electrodes are exposed. A plurality of wiring patterns, in which one end is connected to the connection electrodes and a connection part for the components is provided in the other end, are formed on the lower insulating film. The wiring patterns are covered with an upper insulating film so that the connection part for the components is exposed. The discrete electronic components are connected between different connection parts for the components. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit that is mounted and built in an electronic device.

  2. Description of the Related Art In recent years, in the field of small electronic devices such as mobile phones, electronic components mounted inside have been reduced in size, functionality, density, and density. In addition, in order to reduce the size of the device, it has been studied to configure the device with as few electronic components as possible, and in response to this, a plurality of semiconductor integrated circuits (hereinafter referred to as “ICs”) that are conventionally housed in separate packages. Are also housed in a single package.

  As an example of this, a semiconductor device having a structure as described in Patent Document 1 is known. This semiconductor device has a structure in which the semiconductor chip and the discrete electronic component are accommodated in one package by bonding and fixing the discrete electronic component on a conductive plate arranged in parallel with the semiconductor chip. This structure is shown in FIGS. 9 (a) and 9 (b). FIG. 9B shows a DD cross section of FIG.

  In this semiconductor device, an insulating layer 82 is provided on a semiconductor chip 81, two conductive plates 83 and 84 are provided side by side, and a discrete electronic component 85 is bonded and fixed thereon with a conductive adhesive 86. Yes. Then, an electrode of each part is electrically connected to the lead terminal 87, and the periphery thereof is covered with a resin sealing part 88, so that a semiconductor package excellent in close contact with the substrate is formed.

  As a representative example of a small semiconductor device, a CSP (Chip Size Package) as shown in FIG. 10A and FIG. 10B has the same package size as the semiconductor chip. ) Type of semiconductor device is known. FIG.10 (b) is the EE cross section of Fig.10 (a).

  In this semiconductor device 91, the surface of a semiconductor chip 92 provided with a plurality of electrode pads 93 is covered with a first insulating layer 94 so that the electrode pads 93 are exposed, and one end is formed on the first insulating layer 94. A plurality of wiring patterns 95 connected to the electrode pads 93 and provided with external terminal electrode pads 97 at the other end are formed, and the wiring patterns 95 are second insulated so that the external terminal electrode pads 97 are exposed. The external connection terminal 99 made of solder bumps is formed on the external terminal electrode pad 97 by covering with the layer 96.

JP-A-5-21698

  However, in the semiconductor device shown in FIGS. 9A and 9B, in order to attach the conductive plates 83 and 84 to the semiconductor chip 81, an insulating sheet 82 made of polyimide or the like as an adhesive is used. And a process of attaching the conductive plates 83 and 84 made of Cu to the substrate is necessary, and this work is difficult. That is, it is difficult to attach a plate-like object having a size of 0.5 mm square or less via an adhesive by mechanical operation, and it is particularly difficult to attach a plurality of conductive plates in a dense state.

  Theoretically, in order to mount a discrete electronic component of 0.5 × 0.8 mm size used in a small electronic device, if there are two conductive portions for mounting in a 0.7 × 1.0 mm region, It is enough. However, in FIG. 9, the two conductive plates 83 and 84 occupy 70 to 80% of the semiconductor chip 81. This seems to be because the conductive plates 83 and 84 are enlarged in order to facilitate the handling of the conductive plates 83 and 84 and to shorten the wire when connecting to the ground electrode or the power supply electrode.

  The present invention has been made in view of such circumstances, and provides a semiconductor integrated circuit in which a plurality of discrete electronic components are mounted on a semiconductor chip to reduce the number of components on a printed wiring board. Is.

  The present invention provides a semiconductor chip having a plurality of connection electrodes provided on the surface, a lower insulating layer covering the surface of the semiconductor chip so that the connection electrodes are exposed, and one end formed on the lower insulating layer. Connected between a plurality of wiring parts that are connected and provided with a part connection part at the other end, an upper insulating layer that covers the wiring part so that the part connection part is exposed, and a connection part for different parts And a semiconductor integrated circuit.

  According to the present invention, since the wiring portion provided with the component connection portion is formed on the surface of the semiconductor chip and the electronic component is connected between the different component connection portions, the electronic component is placed on the surface of the semiconductor chip. The mounted one can be packaged as one semiconductor integrated circuit.

  According to another aspect, the present invention provides a semiconductor chip having a plurality of connection electrodes provided on the surface, a lower insulating layer that covers the surface of the semiconductor chip so that the connection electrodes are exposed, and a lower insulating layer on the lower insulating layer. A plurality of wiring portions each having one end connected to the connection electrode and the other end or one end and the other end provided with a component connection portion or / and an external terminal connection portion; and a component connection portion; The upper insulating layer that covers the wiring portion so that the external terminal connection portion is exposed, the electronic component connected between the different component connection portions, and the semiconductor chip surface to which the electronic component is connected exist. An electronic component including an external connection terminal formed in the external terminal connection portion and connected to the semiconductor chip is a semiconductor integrated circuit characterized in that a height after the connection is lower than that of the external connection terminal.

  In the present invention, the semiconductor chip only needs to have a plurality of connection electrodes provided on the surface. The connection electrode means a portion usually called an electrode pad that is bonded to a lead terminal by a wire. The semiconductor chip may be any semiconductor chip. For example, an integrated circuit is formed on various semiconductor substrates (wafers) such as a group 14 (former group IV / Japanese) semiconductor such as Si or a compound semiconductor. What is necessary is just what is generally called a semiconductor chip diced.

  The lower insulating layer and the upper insulating layer are preferably formed using an organic polymer from the viewpoint of ease of forming work and cost. An example of this polymer is polyimide. In order to expose the connection electrode, patterning is necessary. For this purpose, a photosensitive polymer may be used. Further, a non-photosensitive polymer may be formed and patterned with a photosensitive resist.

  The wiring portion is generally called a wiring pattern, and includes various wiring patterns formed by various etching and electrolytic plating.

  The electronic component is generally called a discrete electronic component and is connected between different component connection portions. The connection part for parts is usually gold-plated on the surface, and in order to connect discrete electronic parts between different part connection parts, solder paste is placed on the connection parts for parts and the discrete electronics are placed on the parts. Parts can be placed and connected by reflowing through a reflow oven or the like.

  According to the present invention, since a plurality of small discrete electronic components can be mounted on a semiconductor chip, it is possible to contribute to a reduction in the number of components on the printed wiring board.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS. Note that the present invention is not limited thereby.

Embodiment 1
FIG. 1A and FIG. 1B are explanatory views showing Embodiment 1 of the semiconductor integrated circuit of the present invention. FIG.1 (b) has shown the AA cross section of Fig.1 (a).
A semiconductor integrated circuit 1 includes a semiconductor chip (also referred to as an “IC chip”) 2 provided with electrode pads (first connection portions) 3, a lower insulating film (lower insulating layer) 4, wiring (wiring portions) 5, an upper portion An insulating film (upper insulating layer) 6, a component connection terminal (second connection portion) 7, and a discrete electronic component 8 are configured.

  A plurality of electrode pads 3 are provided at the end of the surface of the semiconductor chip 2. The surface of the semiconductor chip 2 is covered with a lower insulating film 4 except for the electrode pads 3. A plurality of wirings 5 are formed on the lower insulating film 4. One end of the wiring 5 is connected to the electrode pad 3, the other end is provided with a connection pad, and a component connection terminal 7 made of solder is formed on the connection pad.

  The wiring 5 is covered with the upper insulating film 6 except for the portion of the connection pad where the component connection terminals 7 are formed. The discrete electronic component 8 is connected between the component connection terminals 7 of different wirings 5.

2A to 2E are explanatory views showing a manufacturing process of the semiconductor integrated circuit of the present embodiment. The manufacturing process will be described based on these drawings.
The semiconductor chip 2 is based on silicon (Si) and has an integrated circuit formed therein. The semiconductor chip 2 is provided with an electrode pad 3 to which a wire made of metal is bonded.

First, the surface of the semiconductor chip 2 is covered with a polyimide lower insulating film 4 having a thickness of 5 μm except for the electrode pad 3 (see FIG. 2A). Although not shown, an insulating film such as SiO ₂ or SiN exists under the lower insulating film 4.

  Next, the wiring 5 is formed on the lower insulating film 4 by plating. The wiring 5 forms an electrically conductive pattern from the electrode pad 3 to the portion where the discrete electronic component 8 is mounted (see FIG. 2B).

  A specific method for forming the wiring 5 will be described. First, titanium tungsten (TiW) and copper (Cu) are sequentially formed on the electrode pad 3 and the lower insulating film 4, that is, on the entire surface of the semiconductor chip 2 by sputtering so as to have a thickness of about 0.1 μm. . Next, a photosensitive resist is applied on copper to a thickness of 10 μm, exposed through a mask, and developed to form a groove in a portion for forming the wiring 5 (not shown). Independent copper wiring by depositing 5μm thick copper into the groove by chemical plating, chemically stripping the photosensitive resist and removing the sputtered copper and titanium tungsten exposed on the surface. 5 is formed.

  Next, a photosensitive polymer is applied to the thickness of 10 μm on the wiring 5 and the lower insulating film 4, that is, the entire surface of the semiconductor chip 2, and a portion where the discrete electronic component 8 is mounted, that is, a connection pad portion is formed. The upper insulating film 6 is formed by exposing through a mask and developing so as to be exposed (see FIG. 2C).

  In addition, a non-photosensitive polymer and a photosensitive resist may be used without using a photosensitive polymer. That is, by applying a non-photosensitive polymer, applying a photosensitive resist thereon, exposing through a mask, and developing, the discrete electronic component is simultaneously applied to the photosensitive resist and the non-photosensitive polymer. A connection opening (connection pad) may be formed. This method also provides the same structure.

  Next, the portion of the copper wiring 5 exposed so that the discrete electronic component 8 can be mounted, that is, the portion of the connection pad, is made of 3 μm of nickel (Ni) by electroless plating and 0 of gold (Au) thereon. 1 μm is formed (not shown).

  Next, the component connection terminal 7 is formed by printing solder paste on the gold (see FIG. 2 (d)), and the discrete electronic component 8 is placed on the component connection terminal 7 and discrete by reflow processing. The electronic component 8 is fixed (see FIG. 2 (e)).

  At the end of the process, singulation (dicing) is performed at the timing position 9 to complete the semiconductor integrated circuit 1. Thus, after assembling the semiconductor chip 2 in the wafer state, the discrete electronic component 8 is mounted and then dicing is performed.

  FIG. 3A and FIG. 3B are explanatory views showing a state where the semiconductor integrated circuit 1 completed by the manufacturing process described above is packaged. 3A shows the internal structure of a semiconductor package called TSOP (Thin Small Outline Package), and FIG. 3B shows the internal structure of a semiconductor package called CSP. Yes.

  For example, a semiconductor package 70 or a semiconductor package 71 having the same appearance as a conventional package is manufactured by resin molding the semiconductor integrated circuit 1 completed by the manufacturing process described above.

  In the semiconductor package 70 shown in FIG. 3A, the semiconductor chip 2 on which the discrete electronic component 8 is mounted is fixed to a region called a die pad 14 with a die attach material 11 such as silver paste, and the whole is an epoxy resin. 16, and the electrode pad and the lead terminal 17 are electrically connected by the wire 12.

  A semiconductor package 71 shown in FIG. 3B is a package very close to the size of the semiconductor chip. In this semiconductor package 71, the semiconductor chip 2 on which the discrete electronic component 8 is mounted on the printed circuit board 15 having the insulating portion 15a and the conductive portion 15b is fixed with a die attach material 11 such as a polyimide insulating sheet. The whole is sealed with an epoxy resin 16, the electrode pad and the conductive portion 15b are electrically connected by the wire 12, and the external connection terminal 19 is provided on the surface of the printed circuit board 15 on which the semiconductor chip 2 is not mounted. It has a structure.

Embodiment 2
4 (a) and 4 (b) are explanatory views showing a semiconductor integrated circuit according to a second embodiment of the present invention. FIG. 4B shows a BB cross section of FIG. The semiconductor integrated circuit of the present embodiment has a structure obtained by developing the semiconductor integrated circuit shown in the first embodiment.

  In the present semiconductor integrated circuit 72, the electrode pad 23 forming surface of the semiconductor chip 22 faces downward, and the lower insulating film 24, the wiring 25, the upper insulating film 26, the component connection terminal 27, and the external connection terminal 29 are formed on the downward surface. It has a structure. That is, a connection pad and an external connection terminal pad are formed on the wiring 25. A component connection terminal 27 is formed on the connection pad, and a discrete electronic component 28 is mounted on the component connection terminal 27. An external connection terminal 29 made of a solder bump is formed on the external connection terminal pad.

  The discrete electronic component 28 may be provided in the middle of the wiring 25 arranged from the electrode pad 23 to the external connection terminal 29 or in a branched portion, or may be provided in a portion of the wiring 25 extended from the external connection terminal 29.

  A region other than the component connection terminal 27 and the external connection terminal 29 is covered with an upper insulating film 26 made of a photosensitive polymer having a thickness of 10 μm.

FIG. 5A to FIG. 5E are explanatory views showing a manufacturing process of the semiconductor integrated circuit of this embodiment. The manufacturing process will be described based on these drawings.
The semiconductor chip 22 is the same as that of the first embodiment, and first, similarly to the first embodiment, the surface of the semiconductor chip 2 is covered with the lower insulating film 4 (see FIG. 5A).

  Next, the wiring 5 is formed on the lower insulating film 4 (see FIG. 5B), and then the upper insulating film is formed on the entire surface of the semiconductor chip 2 excluding the connection pad and the external connection terminal pad. 6 is formed (see FIG. 5C).

  Next, solder paste is printed on the connection pad portion and the external connection terminal pad portion, thereby forming the component connection terminal 27 for mounting the discrete electronic component 8 and the connection portion 27a for forming the external connection terminal. (See FIG. 5 (d)).

  Next, the discrete electronic component 8 is placed on the component connection terminal 7, and a solder ball is placed on the connection portion 27a, and the reflow process is performed to fix the discrete electronic component 8 to the component connection terminal 7, External connection terminals 29 made of solder bumps are formed on the connection portions 27a (see FIG. 5E). Thus, the external connection terminal 29 is attached at the same time as the discrete electronic component 8 is attached. Finally, dicing is performed.

  This manufacturing process is different from the manufacturing process of FIG. 2 in that the wiring 25 on the electrode pad 23 to which the wire 12 is connected is covered with the upper insulating film 26 and the external connection terminal 29 is attached. is there.

Embodiment 3
FIG. 6A and FIG. 6B are explanatory views showing Embodiment 3 of the semiconductor integrated circuit of the present invention. FIG. 6B shows a CC cross section of FIG. The semiconductor integrated circuit of the present embodiment also has a structure obtained by developing the semiconductor integrated circuit shown in the first embodiment.

  The semiconductor integrated circuit 41 has a structure in which a semiconductor chip 42 with the electrode pad 43 forming surface facing upward and a semiconductor chip 52 with the electrode pad 53 forming surface facing downward are connected by a flip chip.

  A lower insulating film 44, wiring 45, and upper insulating film 46 are sequentially formed on the electrode pad 43 forming surface of the upward semiconductor chip 42. The wiring 45 has one end connected to the electrode pad 43 and the other end formed with a component connection terminal 47 on which a discrete electronic component 48 is mounted and a circular pad for connection to a connection portion 59 made of a solder bump. The circular pad is formed at the end or in the middle of the wiring 45. The upper surface of the upward semiconductor chip 42 is covered with an upper insulating film 46 made of a photosensitive polymer having a thickness of 10 μm so that a part of the circular pads is exposed.

  A lower insulating film 54, a wiring 55, and an upper insulating film 56 are sequentially formed on the electrode pad 53 forming surface of the downward semiconductor chip 52. The wiring 55 has one end connected to the electrode pad 53 and the other end formed with a circular pad for connection to the connection portion 59. The lower surface of the downward semiconductor chip 52 is covered with an upper insulating film 56 made of a photosensitive polymer having a thickness of 10 μm so that a part of the circular pads is exposed.

  Then, the circular pad of the upward semiconductor chip 42 and the circular pad of the downward semiconductor chip 52 are joined via the connection portion 59.

  In the semiconductor integrated circuit 41 shown in FIGS. 6A and 6B, the semiconductor chip 42, the semiconductor chip 52, and the discrete electronic component 48 are provided via the wiring 45, the wiring 55, and the connection portion 59. Accordingly, electrical connections are made to each other.

  6A and 6B, all the electrode pads 53 of the semiconductor chip 52 are electrically connected to the electrode pads 43 of the semiconductor chip 42. However, the connection pads dedicated to the semiconductor chip 52 are connected to the semiconductor chip 42. You may make it provide as a part of wiring 45 on it.

  FIG. 7 is an explanatory view showing a state in which the above-described semiconductor integrated circuit 41 is packaged, and the above-described semiconductor integrated circuit 41 is assembled into a package 73 as shown in this figure.

  FIG. 8A and FIG. 8B are explanatory views showing a semiconductor integrated circuit in a wafer state. As shown in this figure, the above-described semiconductor integrated circuit is assembled in a state of a wafer 100 from start to finish. Finally, dicing into pieces.

  In this way, the surface of the semiconductor chip provided with a plurality of electrode pads is covered with the lower insulating film so that the electrode pads are exposed, a plurality of wirings are formed thereon, and one end of the wiring is formed as an electrode. In addition to pad connection, a component connection terminal is provided at the other end of the wiring, the wiring part is covered with an upper insulating film so that the component connection terminal is exposed, and discrete electronic components are connected between the component connection terminals of different wirings. As a result, a plurality of small discrete electronic components can be mounted on the semiconductor chip, thereby reducing the number of components on the printed wiring board.

1 is an explanatory diagram showing a first embodiment of a semiconductor integrated circuit according to the present invention. FIG. 6 is an explanatory diagram illustrating a manufacturing process of the semiconductor integrated circuit according to the first embodiment. FIG. 6 is an explanatory diagram showing a state where the semiconductor integrated circuit completed by the manufacturing process of Embodiment 1 is packaged. It is explanatory drawing which shows Embodiment 2 of the semiconductor integrated circuit of this invention. FIG. 10 is an explanatory diagram illustrating a manufacturing process of the semiconductor integrated circuit according to the second embodiment. It is explanatory drawing which shows Embodiment 3 of the semiconductor integrated circuit of this invention. It is explanatory drawing which shows the state which packaged the semiconductor integrated circuit of Embodiment 3. FIG. It is explanatory drawing which shows the semiconductor integrated circuit of a wafer state. It is explanatory drawing which shows the structure which accommodated the conventional semiconductor chip and discrete electronic components in one package. It is explanatory drawing which shows the semiconductor device called the conventional chip size package.

Explanation of symbols

1, 41, 72 Semiconductor integrated circuit 2, 22, 42, 52 Semiconductor chip 3, 23, 43, 53 Electrode pad 4, 24, 44, 54 Lower insulating film 5, 25, 45, 55 Wiring 6, 26, 46, 56 Upper insulating film 7, 27, 47 Component connection terminal 8, 28, 48 Discrete electronic component 9 Tying position 11 Die attach material 12 Wire 14 Die pad 15 Printed circuit board 15a Insulation portion 15b Conductive portion 16 Epoxy resin 17 Lead terminal 19, 29 External Connection Terminal 27a Connection Portion for Forming External Connection Terminal 59 Connection Portion 70, 71, 73 Semiconductor Package

Claims (5)

A semiconductor chip provided with a plurality of connection electrodes on the surface;
A lower insulating layer covering the surface of the semiconductor chip so that the connection electrode is exposed;
A plurality of wiring portions formed on the lower insulating layer, one end of which is connected to the connection electrode and the other end or one end and the other end are provided with a component connection portion or / and an external terminal connection portion;
An upper insulating layer covering the wiring part so that the connection part for parts and the connection part for external terminals are exposed;
Electronic components connected between different component connections;
An external connection terminal formed on a connection portion for external terminals existing on the same surface as the semiconductor chip surface to which the electronic component is connected;
An electronic component connected to a semiconductor chip has a height after connection lower than that of an external connection terminal.   2. The semiconductor integrated circuit according to claim 1, wherein a part of the wiring portion is a wiring portion in which an external terminal connection portion is provided at one end and a component connection portion is provided at the other end.   3. A semiconductor integrated circuit obtained by flip-chip connecting another semiconductor integrated circuit to the external connection terminal of the semiconductor integrated circuit according to claim 1.   The semiconductor integrated circuit according to claim 1 or 2 is mounted on a die pad, the connection electrode and the lead terminal are connected by a wire, the semiconductor integrated circuit, the die pad and the wire are sealed with a resin, and a part of the lead terminal is exposed. A semiconductor integrated circuit device.   3. The semiconductor integrated circuit according to claim 1 or 2 is mounted on one surface of a printed circuit board composed of an insulating substrate and a conductive portion, and the connection electrode and the conductive portion of the printed circuit board are connected by a wire. A semiconductor integrated circuit device in which an external connection terminal electrically connected to the conductive portion is formed on the other surface of the printed circuit board.

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