JP2006294882A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2006294882A
JP2006294882A JP2005114055A JP2005114055A JP2006294882A JP 2006294882 A JP2006294882 A JP 2006294882A JP 2005114055 A JP2005114055 A JP 2005114055A JP 2005114055 A JP2005114055 A JP 2005114055A JP 2006294882 A JP2006294882 A JP 2006294882A
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semiconductor substrate
semiconductor device
solder
connection body
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JP4645276B2 (en
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Yuji Iizuka
祐二 飯塚
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Fuji Electric Co Ltd
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Fuji Electric Holdings Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has high heat dissipation efficiency and ensures high connection reliability by preventing connection defect and the occurrence of damage due to thermal stress. <P>SOLUTION: A rolled material such as aluminum and copper of good conductivity is punched on a semiconductor substrate 1, and a connector 3 which is subjected to bending processing is fixed thereto by a solder 2. The bottom surface of the recess of the connector 3 is a constraint region 4 fixed by the solder 2, and the upper part of the connector 3 is a non-constraint region 5 which is not fixed by the solder 2. Since the constraint region 4 of the connector 3 which functions as a spring in the non-constraint region 5 is fixed by the solder 2 on the semiconductor substrate 1, thermal stress generated inside the solder 2 due to the difference of thermal expansion efficient between the connector 3 and the semiconductor substrate 1 is reduced by the spring function of the connector 3, and connection reliability is improved. At the same time, heat dissipation function is improved. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明は、パワーモジュールなどの半導体装置に関する。   The present invention relates to a semiconductor device such as a power module.

パワーデバイスは電力変換用途のスイッチングデバイスとして用いられる。図１３は、従来の半導体チップを実装したパワーモジュール（半導体装置）の要部断面図である。従来の半導体装置は、アルミニウムや銅などの良伝導体の材質で作られた銅ベース５７（放熱ベース）の上に半導体基板５１（半導体チップ）を固着した導電パターン５３、５４、５５、５６を形成した絶縁基板５２（配線基板）が固着されて配置され、単体のモジュールが形成される。このような単体のモジュールが外部ケース５９に収納され、半導体装置が構成される。また、半導体基板５１の表面電極からは、通常アルミワイヤ６０などが接合され、回路パターンを有する導電パターン５４との間の導通を保持する構造を有する。このアルミワイヤ６０には放熱上の効果はなく、半導体基板５１で発生した熱は、導電パターン５６に固着された半導体基板５１の下部の電極面および絶縁基板５２を介して銅ベース５７に放熱される。   The power device is used as a switching device for power conversion. FIG. 13 is a cross-sectional view of a main part of a power module (semiconductor device) mounted with a conventional semiconductor chip. The conventional semiconductor device has conductive patterns 53, 54, 55, 56 in which a semiconductor substrate 51 (semiconductor chip) is fixed on a copper base 57 (heat dissipation base) made of a good conductor material such as aluminum or copper. The formed insulating substrate 52 (wiring substrate) is fixedly disposed and a single module is formed. Such a single module is housed in the outer case 59 to constitute a semiconductor device. In addition, an aluminum wire 60 or the like is usually joined from the surface electrode of the semiconductor substrate 51, and the semiconductor substrate 51 has a structure that maintains electrical connection with the conductive pattern 54 having a circuit pattern. The aluminum wire 60 has no heat dissipation effect, and the heat generated in the semiconductor substrate 51 is radiated to the copper base 57 through the lower electrode surface of the semiconductor substrate 51 fixed to the conductive pattern 56 and the insulating substrate 52. The

このようなパワーモジュールでは、中小容量のモジュールはチップサイズが年々小型化する傾向が顕著であるため、実装上の配線密度が限界に達しつつある。また、大容量のモジュールは大定格動作の必要からチップの発熱密度が著しく増大する傾向にある。
このため、図１４のように、良伝導性のリードフレーム６１を半導体基板５１上面電極に固着させ、導通と放熱の双方の機能を付加する試みがなされている（例えば、特許文献１参照）。この構成は、半導体基板１の表面を冷却できる他、複数のアルミワイヤを接合する工程を単一の部材をチップに接合する工程に集約できる利点がある。
しかし、従来のリードフレーム構造を有する半導体装置では、放熱性を損なうことなく、長期に渡る使用環境温度の変化（熱サイクル）に対するリードフレーム６１と半導体基板５１の接続信頼性を確保することが難しいという問題があった。それは、半導体基板１とリードフレーム６１の熱膨張係数に大きな差があり、そのため、熱サイクルの度に半導体基板５１とリードフレーム６１の接合層に熱応力が加わり、接合層は破壊されてしまうためである。 In such a power module, since the small and medium capacity modules tend to have a smaller chip size year by year, the wiring density on mounting is reaching its limit. In addition, a module having a large capacity has a tendency that the heat generation density of the chip is remarkably increased due to the necessity of a large rated operation.
For this reason, as shown in FIG. 14, an attempt has been made to attach a highly conductive lead frame 61 to the upper electrode of the semiconductor substrate 51 and add both functions of conduction and heat dissipation (see, for example, Patent Document 1). This configuration has an advantage that the surface of the semiconductor substrate 1 can be cooled and the process of bonding a plurality of aluminum wires can be integrated into the process of bonding a single member to a chip.
However, in a semiconductor device having a conventional lead frame structure, it is difficult to ensure the connection reliability between the lead frame 61 and the semiconductor substrate 51 against a long-term change in operating environment temperature (thermal cycle) without impairing heat dissipation. There was a problem. This is because there is a large difference in the thermal expansion coefficient between the semiconductor substrate 1 and the lead frame 61, and therefore, thermal stress is applied to the bonding layer between the semiconductor substrate 51 and the lead frame 61 every time the thermal cycle occurs, and the bonding layer is destroyed. It is.

これを解決するために、半導体基板５１（半導体チップ）の表面電極に固着する導電体をプレス加工して、導電体の接続領域の表面を複数の直線状の縦溝と複数の直線状の横溝とが交差するように形成し、接続領域の裏側を複数の縦突条と複数の横突条とが交差するように形成する。この導電体は蛇腹状をしているため、この導電体の表面側を半導体基板の表面電極に半田で固着すると、半導体基板が熱サイクルで膨張、伸縮したときでも、その変位を緩和できるため、熱応力による接続不良や損傷を防止することができることが開示されている（例えば、特許文献２参照）。
また、熱応力を緩和する方法として、半導体基板上に応力緩和層を設けてこの応力緩和層とリードフレームを半田接合するとが開示されている（特許文献３など）。
また、電子部品を導電パターン付き絶縁基板（配線基板）に半田付けする場合に、電子部品に応力緩和機構体を設けて熱応力を吸収する方法が開示されている（特許文献４など）。
特開２０００−１５６４３９号公報、第１図 特開２００４−４７８００号公報、第２図 特開２００３−２３４４４７号公報、第３図 特開平１１−２２４８９１号公報、第１図 In order to solve this, the conductor fixed to the surface electrode of the semiconductor substrate 51 (semiconductor chip) is pressed, and the surface of the connection region of the conductor is formed with a plurality of straight vertical grooves and a plurality of straight horizontal grooves. And a plurality of vertical ridges and a plurality of horizontal ridges cross each other on the back side of the connection region. Since this conductor has a bellows shape, when the surface side of this conductor is fixed to the surface electrode of the semiconductor substrate with solder, even when the semiconductor substrate expands and contracts by thermal cycle, the displacement can be relaxed, It is disclosed that connection failure and damage due to thermal stress can be prevented (for example, see Patent Document 2).
Further, as a method for relieving thermal stress, it is disclosed that a stress relaxation layer is provided on a semiconductor substrate and the stress relaxation layer and a lead frame are soldered together (Patent Document 3, etc.).
In addition, when soldering an electronic component to an insulating substrate (wiring substrate) with a conductive pattern, a method of absorbing a thermal stress by providing a stress relaxation mechanism on the electronic component is disclosed (Patent Document 4 and the like).
Japanese Patent Laid-Open No. 2000-156439, FIG. Japanese Patent Laid-Open No. 2004-47800, FIG. Japanese Patent Laid-Open No. 2003-234447, FIG. 3 Japanese Patent Laid-Open No. 11-224891, FIG.

しかし、前記の特許文献２において、導電体の縦溝および横溝が半田で充満されると、蛇腹効果（ばね効果）が薄れて、導電体は剛体化される。そのため、熱サイクルによる熱応力を吸収できなくなり、接続不良や損傷を防止することが困難になる。
この発明の目的は、前記の課題を解決して、放熱効率が高く、熱応力による接続不良や損傷の発生が防止できて高い接続信頼性が確保できる半導体装置を提供することにある。 However, in Patent Document 2, when the vertical and horizontal grooves of the conductor are filled with solder, the bellows effect (spring effect) is reduced and the conductor is made rigid. Therefore, it becomes impossible to absorb the thermal stress due to the thermal cycle, and it becomes difficult to prevent connection failure and damage.
An object of the present invention is to provide a semiconductor device that solves the above-described problems, has high heat dissipation efficiency, can prevent connection failure and damage due to thermal stress, and can ensure high connection reliability.

前記の目的を達成するために、半導体基板と、該半導体基板に接合する接続体と、を有する半導体装置において、前記接続体は、前記半導体基板に固着される複数の拘束領域と、該拘束領域間を連接するとともに固着されない複数の非拘束領域を有する構成とする。 また、前記非拘束領域は、前記拘束領域の表面より離れているとよい。
また、前記半導体基板と前記接続体との固着は導電性接着剤にて行うとよい。
また、前記接続体は、断面形状が略波状となる部分を有し、略波状となる部分のうち、前記半導体基板側に凹んだ凹部を前記拘束領域とし、前記半導体基板とは単体側に膨らんだ凸部を前記非拘束領域とする構成とするとよい。
また、前記複数の拘束領域からなる部分を前記半導体基板と前記接続体との接合領域とし、該接合領域の中心部から該接合領域の外周部に向かって複数の拘束領域が配置されるとともに、前記拘束領域の面積が前記中心部から前記外周部に向かって小さくなる構成とするとよい。 In order to achieve the above object, in a semiconductor device having a semiconductor substrate and a connection body bonded to the semiconductor substrate, the connection body includes a plurality of restriction regions fixed to the semiconductor substrate, and the restriction region. A plurality of unconstrained regions are connected to each other and are not fixed. The unconstrained region may be separated from the surface of the constrained region.
Further, the semiconductor substrate and the connection body may be fixed with a conductive adhesive.
Further, the connection body has a portion having a substantially wavy cross-sectional shape, and of the substantially wavy portion, a concave portion recessed on the semiconductor substrate side is used as the restraining region, and the semiconductor substrate swells on a single side. It is preferable that the convex portion is the unconstrained region.
In addition, a portion composed of the plurality of constraining regions is a joint region between the semiconductor substrate and the connection body, and a plurality of constraining regions are arranged from the center of the joint region toward the outer periphery of the joint region, It is preferable that the area of the constraining region is reduced from the central portion toward the outer peripheral portion.

また、前記複数の拘束領域からなる部分を前記半導体基板と前記接続体との接合領域とし、前記半導体基板と前記接続体との接合領域の中心部から該接合領域の外周部に向かって複数の拘束領域が配置されるとともに、前記拘束領域と前記半導体基板との距離が前記中心部から前記外周部に向かって大きくなる構成とするとよい。
また、前記非拘束領域に前記導電性接着剤と接合しない非接合部材を設けるとよい。
また、前記導電性接着剤は半田であるとよい。
また、前記非接合部材は前記半田が濡れないソルダレジスト領域であるとよい。
また、前記拘束領域の形状を開口部として有する位置決め枠を前記拘束領域に嵌め込むとよい。
また、前記非拘束領域の一部に支持基板の導体パターンを接合するとよい。 Further, a portion composed of the plurality of constraining regions is defined as a joint region between the semiconductor substrate and the connection body, and a plurality of portions are formed from a central portion of the joint region between the semiconductor substrate and the connection body toward an outer peripheral portion of the joint region. It is preferable that the constraining region is arranged and the distance between the constraining region and the semiconductor substrate is increased from the central part toward the outer peripheral part.
In addition, a non-joining member that is not joined to the conductive adhesive may be provided in the non-restraining region.
The conductive adhesive may be solder.
The non-joining member may be a solder resist region where the solder is not wetted.
A positioning frame having the shape of the restraining area as an opening may be fitted into the restraining area.
Moreover, it is good to join the conductor pattern of a support substrate to a part of said unconstrained area | region.

また、前記非拘束領域の一部に外部導出用の導体を接合するとよい。
また、前記非拘束領域の一部を外部導出用の導体として延設するとよい。 Moreover, it is preferable to join an external lead-out conductor to a part of the unconstrained region.
Moreover, it is good to extend a part of said non-restraining area | region as a conductor for external derivation | leading-out.

この発明によれば、半導体基板とリードフレームや導電パターン付き支持基板の間に、ばね作用のある接続体を挟んで半田などの接着材で固着することで、熱応力によって接着材内に発生する剪断作用を軽減して接続信頼性を向上させ、同時に放熱作用の向上を図ることができる。   According to this invention, a connecting body having a spring action is sandwiched between a semiconductor substrate and a lead frame or a support substrate with a conductive pattern and fixed with an adhesive such as solder, thereby generating in the adhesive due to thermal stress. The shearing action can be reduced to improve the connection reliability, and at the same time, the heat dissipation action can be improved.

発明の実施の形態を以下の実施例で説明する。   Embodiments of the invention are described in the following examples.

図１および図２は、この発明の第１実施例の半導体装置の要部構成図であり、図１（ａ）は半導体基板と接続体を組み合わせた要部平面図、図１（ｂ）は図１（ａ）のＸ−Ｘ線で切断した要部断面図、図２は組み立て後の要部断面図である。図１は接続体を半導体基板上に半田で固着した模式図を示す。
図１において、半導体基板１上に良伝導性のアルミニウム、銅などを２００μｍ程度にの圧延した材料を打ち抜き加工し、それに曲げ加工を施した接続体３を半田２で固着する。図１（ｂ）の断面図に示すように、接続やい３の断面は波状（矩形波状）となっており、凹部の底部とそれに連続する側面の一部が半田２で固着され拘束領域４となる。凸部の上面とそれに連続する側面であって、半田が固着されない部分が非拘束領域５となる。接続体３の凹部の底面と半導体基板１との間には半田２が介在し、半導体基板上に接続体３が当接することはない。 1 and 2 are main part configuration diagrams of a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a main part plan view combining a semiconductor substrate and a connection body, and FIG. FIG. 2 is a cross-sectional view of main parts cut along line XX in FIG. 1A, and FIG. 2 is a cross-sectional view of main parts after assembly. FIG. 1 is a schematic view showing a connection body fixed on a semiconductor substrate with solder.
In FIG. 1, a material obtained by rolling highly conductive aluminum, copper, or the like to a thickness of about 200 μm is punched on a semiconductor substrate 1, and a connection body 3 subjected to bending is fixed with solder 2. As shown in the cross-sectional view of FIG. 1B, the cross-section of the connecting wire 3 has a wave shape (rectangular wave shape). It becomes. The upper surface of the convex portion and the side surface continuous therewith, the portion to which the solder is not fixed becomes the unconstrained region 5. The solder 2 is interposed between the bottom surface of the concave portion of the connection body 3 and the semiconductor substrate 1 so that the connection body 3 does not come into contact with the semiconductor substrate.

ここで、半導体基板としてＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）に代表されるパワー半導体素子などの発熱の大きいものへ接続するには接続体として熱伝導性の良好な材料、上記に例示したように、良伝導性のアルミニウム、銅などの非鉄材料が好適である。発熱（放熱）の程度によっては、鉄とニッケルの合金なども適用可能である。また、半田以外にも、例えば、樹脂系の導電性接着剤の適用も可能である。
図２において、接続体３を半導体基板１上に半田３で固着した後、絶縁基板４６（支持基板）に形成した導電パターン４４に半導体基板１の裏面を固着し、接続体３の非拘束領域の一部をリードフレーム４３（外部導出導体）に形成した導電パターン４１に固着し、リードフレーム４３の他端を絶縁基板４６に形成した導電パターン４５に固着する。絶縁基板４６の裏面に形成した導電パターン４７を半田４８を介して銅ベース４９（冷却体と支持補強基板の働きをする）に固着し、銅ベース４９をヒートシンク５０に固着する。絶縁基板４６と銅ベース４９の代わりに、アルミニウム板の上に絶縁膜を被覆しこの絶縁膜の上に導電パターンを形成したアルミ基板を用いても構わない。 Here, as a semiconductor substrate, a material having high heat conductivity as a connection body, such as a power semiconductor element typified by IGBT (Insulated Gate Bipolar Transistor), can be connected. Non-ferrous materials such as conductive aluminum and copper are preferred. Depending on the degree of heat generation (heat dissipation), an alloy of iron and nickel can also be applied. In addition to solder, for example, a resin-based conductive adhesive can be applied.
In FIG. 2, the connection body 3 is fixed to the semiconductor substrate 1 with the solder 3, and then the back surface of the semiconductor substrate 1 is fixed to the conductive pattern 44 formed on the insulating substrate 46 (support substrate). Is fixed to the conductive pattern 41 formed on the lead frame 43 (external lead conductor), and the other end of the lead frame 43 is fixed to the conductive pattern 45 formed on the insulating substrate 46. A conductive pattern 47 formed on the back surface of the insulating substrate 46 is fixed to a copper base 49 (which functions as a cooling body and a supporting and reinforcing substrate) via a solder 48, and the copper base 49 is fixed to a heat sink 50. Instead of the insulating substrate 46 and the copper base 49, an aluminum substrate in which an insulating film is coated on an aluminum plate and a conductive pattern is formed on the insulating film may be used.

図３は、図１の接続体の製造方法であり、同図（ａ）〜同図（ｄ）は工程順に示した製造工程図である。尚、同図（ｄ）は同図（ｃ）の斜視図である。ここでは図１（ａ）の接続体３の１個の枡目を代表させて説明する。
良伝導性のアルミニウム、銅などの圧延された非鉄材料を打ち抜き加工し、格子状の導板６を形成する（同図（ａ））。
次に、格子状の交差箇所を拘束領域４となるように窪むように曲げ加工を施こし（同図（ｂ））、導板の箇所でａ、ｂ、ｃ、ｄを側壁とし、その先のｅ、ｆ、ｇ、ｈを直角に曲げて水平にして非拘束領域５として接続体３を形成する（同図（ｃ）、（ｄ））。
半導体基板１上にこのような接続体３の拘束領域４を半田２で固着することで、半田２に固着する拘束領域４が分散され、半田２が付かない上部の非拘束領域５がばね効果の働きをして、半導体基板１と接続体３の間の線膨張係数差で生じた熱応力ではんだ２にせん断ひずみが集中することを低減することができる。その結果、接続信頼性を向上させることができる。 FIG. 3 is a manufacturing method of the connection body of FIG. 1, and FIGS. 3A to 3D are manufacturing process diagrams shown in the order of processes. FIG. 4D is a perspective view of FIG. Here, one cell of the connection body 3 in FIG.
A rolled non-ferrous material such as aluminum or copper having good conductivity is punched to form a lattice-shaped conductive plate 6 (FIG. 1A).
Next, bending is performed so that the lattice-shaped intersections are recessed so as to become the constraining regions 4 ((b) in the figure), and a, b, c, and d are used as side walls at the conductive plate, The connection body 3 is formed as the unconstrained region 5 by bending e, f, g, and h at right angles and leveling them (FIGS. 3C and 3D).
By fixing the constraining region 4 of the connecting body 3 on the semiconductor substrate 1 with the solder 2, the constraining region 4 that is fixed to the solder 2 is dispersed, and the upper non-constraining region 5 to which the solder 2 is not attached has a spring effect. Thus, it is possible to reduce the concentration of shear strain on the solder 2 due to the thermal stress generated by the difference in linear expansion coefficient between the semiconductor substrate 1 and the connection body 3. As a result, connection reliability can be improved.

尚、接続体３の形状は図１の格子状の他に、図４のように拘束領域４を大きくした格子状のものや、図５のように円形の拘束領域を放射状に配置し、その中心部の拘束領域４ａを周囲の拘束領域４ｂより大きくしたものでも良い。
図１５は、図４に示した接続体の変形例の部分斜視図である。半導体基板１や半田２の図示は省略している。非拘束領域５の幅に比べ、拘束領域４の幅（面積）が大きい格子状の接続体である。格子状に配置された複数の拘束領域４と、拘束領域４の上方（非接合面方向）へ屈曲した非接合領域５とが連設されている。非拘束領域５が上方へ屈曲していることにより、拘束領域４を導電性接着剤で半導体基板へ固着させたときに導電性接着剤から離れているため、非拘束領域のばね効果を有効に機能させることができる。尚、非拘束領域５を図１の如く拘束領域に対して鉛直に屈曲させて断面を矩形波状に形成してもよいし、図１５の如く、斜め上方へ略波状に屈曲させてもよい。 In addition to the lattice shape shown in FIG. 1, the shape of the connection body 3 is a lattice shape having a larger restricted area 4 as shown in FIG. 4 or a circular restricted area arranged radially as shown in FIG. The central restricted area 4a may be larger than the surrounding restricted area 4b.
FIG. 15 is a partial perspective view of a modified example of the connector shown in FIG. Illustration of the semiconductor substrate 1 and the solder 2 is omitted. This is a grid-like connection body in which the width (area) of the constrained region 4 is larger than the width of the unconstrained region 5. A plurality of constraining regions 4 arranged in a lattice shape and a non-joining region 5 bent upward (non-joining surface direction) of the constraining region 4 are connected. Since the non-restraining region 5 is bent upward, the spring effect of the non-restraining region is effectively obtained because the restraining region 4 is separated from the conductive adhesive when the restraining region 4 is fixed to the semiconductor substrate with the conductive adhesive. Can function. The unconstrained region 5 may be bent vertically with respect to the constraining region as shown in FIG. 1, and the cross section may be formed in a rectangular wave shape, or may be bent in a substantially wave shape obliquely upward as shown in FIG.

図１６は、図１５のＸ１〜Ｘ４平面で切断した部分の矢視断面図である。複数の拘束領域からなる部分を接合領域とした場合、半田２は、図１（ｂ）の如く半導体基板１と接続体３との接合領域全面に渡って設けてもよいし、図１６のように、拘束領域４の部分のみに設けてもよい。
しかし、前記の接続体３において、非拘束領域５に半田２が固着すると、非拘束領域５が拘束されてしまい、接続体３のばね機能が損なわれる。それを解決する方法をつぎの実施例で説明する。 FIG. 16 is a cross-sectional view taken along the X1-X4 plane of FIG. When a portion composed of a plurality of constraining regions is used as a bonding region, the solder 2 may be provided over the entire bonding region between the semiconductor substrate 1 and the connection body 3 as shown in FIG. Alternatively, it may be provided only in the portion of the restraint region 4.
However, when the solder 2 adheres to the unconstrained region 5 in the connection body 3, the unconstrained region 5 is restrained, and the spring function of the connection body 3 is impaired. A method for solving this will be described in the next embodiment.

図６は、この発明の第２実施例の半導体装置の要部断面図である。図１との違いは、接続体３の非拘束領域５に半田２が濡れないソルダレジストとして用いられるエポキシ系の樹脂で樹脂塗布部７を形成した点である。非拘束領域５を樹脂塗布部７でコーティングすることで、非拘束領域５に半田２が固着しなくなり所望の機能を実現することができる。 また、図７のように、非拘束領域５下をポリイミド樹脂８などのリフロー耐熱性のあるもので型注入して先に硬化させて、非拘束領域５に半田２が固着しないようにして所望の機能を実現することができる。図７のように、エポキシ樹脂８で非拘束領域５を包囲してしまっても、エポキシ樹脂８自体の剛性は金属である接続体３に比較して十分低いのでばね機能は確保される。
半田２の代わりに樹脂系の導電性接着剤を用いた場合は、この樹脂系の導電接着剤と非接着の材質のものを樹脂塗布部７に相当する箇所に設けるとよい。 FIG. 6 is a cross-sectional view of the main part of the semiconductor device according to the second embodiment of the present invention. The difference from FIG. 1 is that the resin application part 7 is formed of an epoxy resin used as a solder resist in which the solder 2 does not get wet in the unconstrained region 5 of the connection body 3. By coating the non-restraining area 5 with the resin application part 7, the solder 2 does not adhere to the non-restraining area 5 and a desired function can be realized. Further, as shown in FIG. 7, the lower part of the unconstrained region 5 is molded with a reflow heat resistant material such as polyimide resin 8 and cured first so that the solder 2 does not adhere to the unconstrained region 5. The function can be realized. As shown in FIG. 7, even if the unrestrained region 5 is surrounded by the epoxy resin 8, the rigidity of the epoxy resin 8 itself is sufficiently lower than that of the connection body 3 made of metal, so that the spring function is ensured.
When a resin-based conductive adhesive is used instead of the solder 2, a resin-based conductive adhesive and a non-adhesive material may be provided at a location corresponding to the resin application portion 7.

図８は、この発明の第３実施例の半導体装置の要部構成図であり、同図（ａ）は要部平面図、同図（ｂ）は同図（ａ）のＸ−Ｘ線で切断した要部断面図、同図（ｃ）は位置決め枠の要部平面図である。これは接続体３を半導体基板１上に半田２で固着した模式図を示す。
接続体３の凹凸の形状が崩れないように同図（ｃ）のように、拘束領域４の形状の開口部１０を有する位置決め枠９を形成し、位置決め枠９の開口部１０に接続体３の拘束領域４を嵌め込み、この位置決め枠９を嵌め込んだ接続体３を半導体基板１上に半田２で固着する。位置決め枠９を用いることにより、厚さ２００μｍと薄い素材を複雑な形状に折って形成した接続体３の形状を損なうことなく接合することができる。また、位置決め枠９を半田に濡れない材質（例えば、エポキシなど）で形成しておけば、半田２の非拘束領域５へのはい上がりを抑制することもできる。あるいは、位置決め枠９を熱膨張係数の小さな材質（例えば、セタミックなど）で形成するようにしてよい。 8A and 8B are main part configuration diagrams of a semiconductor device according to a third embodiment of the present invention. FIG. 8A is a plan view of the main part, and FIG. 8B is a sectional view taken along line XX in FIG. Sectional drawing which cut | disconnected principal part and the same figure (c) are principal part top views of a positioning frame. This shows a schematic view in which the connection body 3 is fixed to the semiconductor substrate 1 with the solder 2.
As shown in FIG. 3C, the positioning frame 9 having the opening 10 having the shape of the restraining region 4 is formed so that the uneven shape of the connection body 3 does not collapse, and the connection body 3 is formed in the opening 10 of the positioning frame 9. The connecting region 3 in which the positioning frame 9 is inserted is fixed to the semiconductor substrate 1 with the solder 2. By using the positioning frame 9, it is possible to join without damaging the shape of the connection body 3 formed by folding a thin material having a thickness of 200 μm into a complicated shape. Further, if the positioning frame 9 is formed of a material that does not wet the solder (for example, epoxy), it is possible to suppress the solder 2 from rising to the unrestrained region 5. Alternatively, the positioning frame 9 may be formed of a material having a small thermal expansion coefficient (for example, cematic).

また、図７のようにエポキシ樹脂８を非拘束領域５下に配置した後、この位置決め枠９をセットし半田３で固着すると、非拘束領域５に半田３が一層付き難くなり、接続体３のばね機能を確実に確保できる。   Further, as shown in FIG. 7, when the epoxy resin 8 is arranged below the non-restraining region 5 and then the positioning frame 9 is set and fixed with the solder 3, the solder 3 is more difficult to attach to the non-restraining region 5. The spring function of can be ensured.

図９は、この発明の第４実施例の半導体装置の要部断面図である。この図の接続体３の断面は図５のＸ−Ｘ線で切断した断面図である。図１との違いは半導体基板１の中央部と接続する接続体３の拘束領域４ａが外周部の拘束領域４より面積を大きくし、またその深さを深くした点である。こうすることで、発熱が大きい半導体基板１の中央部の熱を効果的に放熱することができて、熱応力を低減して接続信頼性を向上させることができる。また、熱応力の大きな外周部で半田２の厚さが中央部より厚いため、外周部の熱応力を緩和できて接続信頼性を向上させることができる。   FIG. 9 is a sectional view showing the principal part of a semiconductor device according to the fourth embodiment of the present invention. The cross section of the connection body 3 in this figure is a cross section taken along the line XX in FIG. The difference from FIG. 1 is that the constraining region 4a of the connecting body 3 connected to the central portion of the semiconductor substrate 1 has a larger area and a deeper depth than the constraining region 4 in the outer peripheral portion. By doing so, the heat of the central portion of the semiconductor substrate 1 that generates a large amount of heat can be effectively radiated, and the thermal stress can be reduced and the connection reliability can be improved. In addition, since the thickness of the solder 2 is thicker at the outer peripheral portion where the thermal stress is larger than that at the central portion, the thermal stress at the outer peripheral portion can be alleviated and the connection reliability can be improved.

図１０は、この発明の第５実施例の半導体装置の要部断面図である。図１との違いは半導体基板１の中央部と接続する接続体３の拘束領域４ｃが外周部の拘束領域４ｂより表面からの深さを深くして、半導体基板１の外周部と接続する接続体３の拘束領域４ｂでの半田２の厚さを中央部の拘束領域４ｃでの半田２の厚さより厚くした点である。熱応力が大きく加わる外周部の半田２の厚さを厚くすることで熱応力を効果的に吸収するすることができて、接続信頼性を向上させることができる。また、中央部の大きな発熱を効果的に放熱することができる。   FIG. 10 is a cross-sectional view of the principal part of the semiconductor device according to the fifth embodiment of the present invention. 1 is different from FIG. 1 in that the constraining region 4c of the connection body 3 connected to the central portion of the semiconductor substrate 1 is deeper from the surface than the constraining region 4b of the outer peripheral portion and is connected to the outer peripheral portion of the semiconductor substrate 1. This is that the thickness of the solder 2 in the restraining region 4b of the body 3 is made thicker than the thickness of the solder 2 in the restraining region 4c at the center. By increasing the thickness of the solder 2 on the outer peripheral portion to which a large thermal stress is applied, the thermal stress can be effectively absorbed, and the connection reliability can be improved. In addition, large heat generation at the center can be effectively radiated.

図１１、この発明の第６実施例の半導体装置の要部断面図である。これは図１の半導体基板１の裏面を導電パターン２２（接続体３の拘束領域４と固着する金属パターン）が形成された絶縁基板２１（支持基板）にエポキシ樹脂１８付き接続体１３を介して半田１２で固着し、エポキシ樹脂８付き接続体３に導体２５（外部導出導体）を固着し、半導体基板２１上の導電パターン２４と導体２５をリード導体２６で接続し、図示していないが、図２のように銅ベース１９とヒートシンク２０を固着してモジュールを形成する。勿論、図２で説明したようにアルミ基板を用いても構わない。絶縁基板２１の導電パターン２２の隙間に樹脂膜２３を形成しているのは、この部分と接する接続体３の非拘束領域５が絶縁基板２１に固定しないようにして、拘束されないようにするためである。
この実施例では、半導体基板１の裏面を接続体１３を介して半田１２接合するため、半導体基板１との線膨張係数差が大きい熱伝導性の良好な材質の絶縁基板２１を用いることができる。尚、接続体１３と導電パターン２２の固着は常温直接接合（圧着接合）や溶接接合（スポット溶接）などで温度を上昇させないで固着するとよい。 FIG. 11 is a cross-sectional view of a principal part of a semiconductor device according to a sixth embodiment of the present invention. This is because the back surface of the semiconductor substrate 1 of FIG. 1 is connected to the insulating substrate 21 (support substrate) on which the conductive pattern 22 (metal pattern fixed to the restraining region 4 of the connection body 3) is formed via the connection body 13 with the epoxy resin 18. Although fixed with the solder 12, the conductor 25 (external lead-out conductor) is fixed to the connection body 3 with the epoxy resin 8, and the conductive pattern 24 and the conductor 25 on the semiconductor substrate 21 are connected by the lead conductor 26. As shown in FIG. 2, the copper base 19 and the heat sink 20 are fixed to form a module. Of course, an aluminum substrate may be used as described in FIG. The resin film 23 is formed in the gap between the conductive patterns 22 of the insulating substrate 21 so that the unconstrained region 5 of the connecting body 3 in contact with this portion is not fixed to the insulating substrate 21 and is not restrained. It is.
In this embodiment, since the back surface of the semiconductor substrate 1 is joined to the solder 12 via the connection body 13, the insulating substrate 21 made of a material having a good thermal conductivity and a large difference in linear expansion coefficient from the semiconductor substrate 1 can be used. . The connection body 13 and the conductive pattern 22 may be fixed without increasing the temperature by direct bonding at normal temperature (crimp bonding) or welding bonding (spot welding).

図１２、この発明の第７実施例の半導体装置の要部断面図である。図１１との違いは、リード導体２６を用いず、導電パターン３２を形成した熱伝導性の良好な絶縁基板３１を接続体３の非拘束領域５に接続した点である。この場合、半導体基板１が両面接合されるため、熱応力の強さは倍増することになるが、前述した接続体３、１３の熱応力低減効果により、接続信頼性を確保することができる。熱伝導性の良好な絶縁基板２１、３１からの同時に両面から放熱することができる。尚、この場合も樹脂膜３３は樹脂膜２３と同じ働きをする。   FIG. 12 is a fragmentary cross-sectional view of a semiconductor device according to a seventh embodiment of the present invention. A difference from FIG. 11 is that the lead conductor 26 is not used, and the insulating substrate 31 having a good thermal conductivity in which the conductive pattern 32 is formed is connected to the unconstrained region 5 of the connection body 3. In this case, since the semiconductor substrate 1 is bonded on both sides, the strength of the thermal stress is doubled, but the connection reliability can be ensured by the effect of reducing the thermal stress of the connection bodies 3 and 13 described above. Heat can be radiated from both surfaces simultaneously from the insulating substrates 21 and 31 having good thermal conductivity. In this case as well, the resin film 33 functions in the same manner as the resin film 23.

この発明の第１実施例の半導体装置の要部構成図であり、（ａ）は半導体基板と接続体を組み合わせた要部平面図、（ｂ）は（ａ）のＸ−Ｘ線で切断した要部断面図BRIEF DESCRIPTION OF THE DRAWINGS It is a principal part block diagram of the semiconductor device of 1st Example of this invention, (a) is a principal part top view which combined the semiconductor substrate and the connection body, (b) was cut | disconnected by the XX line of (a). Cross section of the main part この発明の第１実施例の半導体装置の組み立て後の要部断面図Sectional view of the principal part after assembly of the semiconductor device of the first embodiment of the present invention 図１の接続体の製造方法であり、（ａ）〜（ｄ）は工程順に示した製造工程図It is a manufacturing method of the connection object of Drawing 1, and (a)-(d) is a manufacturing process figure shown in process order 拘束領域を大きくした格子状の接続体の形状図Shape of a grid-like connection body with a large restraint area 円形の拘束領域を放射状に配置し、その中心部の拘束領域を周囲の拘束領域より大きくした接続体の形状図Schematic diagram of a connected body in which circular constraining areas are arranged radially and the constraining area in the center is larger than the surrounding constraining areas この発明の第２実施例の半導体装置の要部断面図Sectional drawing of the principal part of the semiconductor device of 2nd Example of this invention 非拘束領域下にポリイミド樹脂を配置した接続体の要部断面図Cross-sectional view of the main part of the connector with polyimide resin placed under the unrestrained area この発明の第３実施例の半導体装置の要部構成図であり、（ａ）は要部平面図、（ｂ）は（ａ）のＸ−Ｘ線で切断した要部断面図、（ｃ）は位置決め枠の要部平面図It is a principal part block diagram of the semiconductor device of 3rd Example of this invention, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the XX line of (a), (c). Is a plan view of the main part of the positioning frame この発明の第４実施例の半導体装置の要部断面図Sectional drawing of the principal part of the semiconductor device of 4th Example of this invention. この発明の第５実施例の半導体装置の要部断面図Sectional drawing of the principal part of the semiconductor device of 5th Example of this invention この発明の第６実施例の半導体装置の要部断面図Sectional drawing of the principal part of the semiconductor device of 6th Example of this invention この発明の第７実施例の半導体装置の要部断面図Sectional drawing of the principal part of the semiconductor device of 7th Example of this invention. 従来のパワーモジュールの要部断面図（ワイヤ）Sectional view of the main part of a conventional power module (wire) 従来のパワーモジュールの別の要部断面図（リードフレーム）Another main part sectional view of a conventional power module (lead frame) 図４に示した接続体の変形例の部分斜視図The fragmentary perspective view of the modification of the connection body shown in FIG. 図１５のＸ１〜Ｘ４平面で切断した部分の矢視断面図15 is a cross-sectional view taken along the X1-X4 plane in FIG.

符号の説明Explanation of symbols

１ 半導体基板
２、１２、４８ 半田
３、１３ 接続体
４、４ａ、４ｂ、４ｃ、１４ 拘束領域
５、１５ 非拘束領域
７ 樹脂塗布部
８、１８ エポキシ樹脂
９ 位置決め枠
１０ 開口部
２１、３１ 絶縁基板
２２、２４、３２、４１、４４、４５、４７ 導電パターン
２３ 樹脂膜
２５ 導体
２６ リード導体
４２、３３ 樹脂膜
４３ リードフレーム
４６ 絶縁基板
４９ 銅ベース
５０ ヒートシンク DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2, 12, 48 Solder 3, 13 Connection body 4, 4a, 4b, 4c, 14 Restraint area 5, 15 Unrestrained area 7 Resin application part 8, 18 Epoxy resin 9 Positioning frame 10 Opening part 21, 31 Insulation Substrate 22, 24, 32, 41, 44, 45, 47 Conductive pattern 23 Resin film 25 Conductor 26 Lead conductor 42, 33 Resin film 43 Lead frame 46 Insulating substrate 49 Copper base 50 Heat sink

Claims (13)

半導体基板と、該半導体基板に接合する接続体と、を有する半導体装置において、前記接続体は、前記半導体基板に固着される複数の拘束領域と、該拘束領域間を連接するとともに固着されない複数の非拘束領域を有することを特徴とする半導体装置。 In a semiconductor device having a semiconductor substrate and a connection body bonded to the semiconductor substrate, the connection body includes a plurality of constraining regions fixed to the semiconductor substrate and a plurality of constraining regions connected to each other and not fixed to each other. A semiconductor device having an unconstrained region. 前記非拘束領域は、前記拘束領域の表面より離れていることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the unconstrained region is separated from a surface of the constrained region. 前記半導体基板と前記接続体との固着は導電性接着剤にて行うことを特徴とする請求項１または請求項２に記載の半導体装置。 The semiconductor device according to claim 1, wherein the semiconductor substrate and the connection body are fixed with a conductive adhesive. 前記接続体は、断面形状が略波状となる部分を有し、略波状となる部分のうち、前記半導体基板側に凹んだ凹部を前記拘束領域とし、前記半導体基板とは単体側に膨らんだ凸部を前記非拘束領域とすることを特徴とする請求項１に記載の半導体装置。 The connection body has a portion having a substantially wavy cross-sectional shape, and of the portions having a substantially wavy shape, a concave portion recessed on the semiconductor substrate side is used as the restraining region, and the semiconductor substrate is a convex portion swelled on the single body side. The semiconductor device according to claim 1, wherein a portion is the unconstrained region. 前記複数の拘束領域からなる部分を前記半導体基板と前記接続体との接合領域とし、該接合領域の中心部から該接合領域の外周部に向かって複数の拘束領域が配置されるとともに、前記拘束領域の面積が前記中心部から前記外周部に向かって小さくなることを特徴とする請求項１〜請求項４のいずれか一項に記載の半導体装置。 The portion composed of the plurality of constraining regions is used as a joint region between the semiconductor substrate and the connection body, and a plurality of constraining regions are arranged from the center of the joint region toward the outer periphery of the joint region. 5. The semiconductor device according to claim 1, wherein an area of the region decreases from the central portion toward the outer peripheral portion. 6. 前記複数の拘束領域からなる部分を前記半導体基板と前記接続体との接合領域とし、前記半導体基板と前記接続体との接合領域の中心部から該接合領域の外周部に向かって複数の拘束領域が配置されるとともに、前記拘束領域と前記半導体基板との距離が前記中心部から前記外周部に向かって大きくなることを特徴とする請求項１〜請求項５のいずれか一項に記載の半導体装置。 A portion composed of the plurality of constraining regions is defined as a joint region between the semiconductor substrate and the connection body, and a plurality of constraining regions are directed from the center of the joint region between the semiconductor substrate and the connection body toward the outer periphery of the joint region. The semiconductor according to claim 1, wherein a distance between the constraining region and the semiconductor substrate increases from the central portion toward the outer peripheral portion. apparatus. 前記非拘束領域に前記導電性接着剤と接合しない非接合部材を設けたことを特徴とする請求項１〜請求項６のいずれか一項に記載の半導体装置。 The semiconductor device according to claim 1, wherein a non-joining member that is not joined to the conductive adhesive is provided in the non-restraining region. 前記導電性接着剤は半田であることを特徴とする請求項１〜請求項７のいずれか一項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the conductive adhesive is solder. 前記非接合部材は前記半田が濡れないソルダレジスト領域であることを特徴とする請求項８に記載の半導体装置。 The semiconductor device according to claim 8, wherein the non-joining member is a solder resist region where the solder is not wetted. 前記拘束領域の形状を開口部として有する位置決め枠を前記拘束領域に嵌め込むことを特徴とする請求項１〜請求項１０のいずれか一項に記載の半導体装置。 11. The semiconductor device according to claim 1, wherein a positioning frame having the shape of the constraining region as an opening is fitted into the constraining region. 前記非拘束領域の一部に支持基板の導体パターンを接合したことを特徴とする請求項１〜請求項１０のいずれか一項に記載の半導体装置。 11. The semiconductor device according to claim 1, wherein a conductor pattern of a support substrate is bonded to a part of the unconstrained region. 前記非拘束領域の一部に外部導出用の導体を接合したことを特徴とする請求項１〜請求項１０のいずれか一項に記載の半導体装置。 11. The semiconductor device according to claim 1, wherein an external lead-out conductor is joined to a part of the unconstrained region. 前記非拘束領域の一部を外部導出用の導体として延設したことを特徴とする請求項１〜請求項１０のいずれか一項に記載の半導体装置。 11. The semiconductor device according to claim 1, wherein a part of the unconstrained region is extended as a conductor for leading out.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011216822A (en) * 2010-04-02 2011-10-27 Hitachi Ltd Power semiconductor module
JP2013008771A (en) * 2011-06-23 2013-01-10 Nissan Motor Co Ltd Semiconductor module
JP2015233036A (en) * 2014-06-09 2015-12-24 三菱電機株式会社 Semiconductor device
JP2016092346A (en) * 2014-11-11 2016-05-23 三菱電機株式会社 Power semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS447543Y1 (en) * 1966-04-04 1969-03-22
JPS63100847U (en) * 1986-12-19 1988-06-30
JP2000349207A (en) * 1999-06-02 2000-12-15 Denso Corp Method and device for mounting semiconductor device
JP2004047800A (en) * 2002-07-12 2004-02-12 Toyota Industries Corp Connecting member and connecting structure
JP2004336043A (en) * 2003-05-02 2004-11-25 Orthodyne Electronics Corp Ribbon bonding
JP2006190728A (en) * 2005-01-04 2006-07-20 Mitsubishi Electric Corp Electric power semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS447543Y1 (en) * 1966-04-04 1969-03-22
JPS63100847U (en) * 1986-12-19 1988-06-30
JP2000349207A (en) * 1999-06-02 2000-12-15 Denso Corp Method and device for mounting semiconductor device
JP2004047800A (en) * 2002-07-12 2004-02-12 Toyota Industries Corp Connecting member and connecting structure
JP2004336043A (en) * 2003-05-02 2004-11-25 Orthodyne Electronics Corp Ribbon bonding
JP2006190728A (en) * 2005-01-04 2006-07-20 Mitsubishi Electric Corp Electric power semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011216822A (en) * 2010-04-02 2011-10-27 Hitachi Ltd Power semiconductor module
JP2013008771A (en) * 2011-06-23 2013-01-10 Nissan Motor Co Ltd Semiconductor module
JP2015233036A (en) * 2014-06-09 2015-12-24 三菱電機株式会社 Semiconductor device
JP2016092346A (en) * 2014-11-11 2016-05-23 三菱電機株式会社 Power semiconductor device

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