JP2006286744A - Semiconductor mounting substrate, substrate for mounting semiconductor, and appearance inspection method and device for them - Google Patents

Semiconductor mounting substrate, substrate for mounting semiconductor, and appearance inspection method and device for them Download PDF

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JP2006286744A
JP2006286744A JP2005101850A JP2005101850A JP2006286744A JP 2006286744 A JP2006286744 A JP 2006286744A JP 2005101850 A JP2005101850 A JP 2005101850A JP 2005101850 A JP2005101850 A JP 2005101850A JP 2006286744 A JP2006286744 A JP 2006286744A
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underfill
substrate
inspection
semiconductor chip
semiconductor
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JP4235621B2 (en
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Atsushi Tsunoda
角田　　敦
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Taiyo Yuden Co Ltd
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Taiyo Yuden Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To highly accurately, inexpensively, and simply execute appearance inspection of underfill. <P>SOLUTION: The appearance inspection method is used for inspecting the appearance of a substrate (10) in which a semiconductor chip (1) is mounted facedown, and the underfill (4) is formed in between the semiconductor chip. The quality in underfill formation is determined by identifying an inspection pattern to the substrate surface and the underfill corresponding to a semiconductor chip mounting region (11) on the substrate. The presence or the absence of exposure of the inspection pattern can be easily identified since the inspection pattern, the substrate, and the underfill are identifiable. Consequently, the accuracy of visual inspection can be improved. It is also possible to prevent the steep cost increase since a simple automation system can be constructed by combining a general-purpose camera or the like with the appearance inspection device. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体実装基板、半導体実装用基板、その外観検査方法及び外観検査装置に関する。詳しくは、フェイス面に接続用電極部（バンプ）を形成した半導体チップをフェイスダウンで取り付けるインタポーザ等の半導体実装回路用基板に係り、特に、半導体チップの取り付けに際し、その半導体チップと基板との間にエポキシ樹脂等を主成分とする熱硬化性樹脂組成物を充填して封止する構造の半導体実装基板、半導体実装用基板、その外観検査方法及び外観検査装置に関する。   The present invention relates to a semiconductor mounting substrate, a semiconductor mounting substrate, an appearance inspection method, and an appearance inspection apparatus. More specifically, the present invention relates to a semiconductor mounting circuit board such as an interposer for mounting a semiconductor chip having connection electrode portions (bumps) on the face face thereof face down, and in particular, between the semiconductor chip and the board when mounting the semiconductor chip. The present invention relates to a semiconductor mounting substrate, a semiconductor mounting substrate, a visual inspection method thereof, and a visual inspection device having a structure in which a thermosetting resin composition mainly composed of an epoxy resin or the like is filled and sealed.

近年、各種電子機器用回路基板に対する高密度実装及び低背化要求のさらなる高まりに伴い、パッケージングされていない半導体チップ（ベアチップ）によるダイレクトチップアタッチ方式が注目されている。たとえば、当該方式の代表であるフリップチップ実装では、半導体チップ側に高融点半田バンプを形成して、セラミック回路基板側の半田との金属間接合を行う、いわゆる「Ｃ４技術」が著名である。   2. Description of the Related Art In recent years, with a further increase in demand for high-density mounting and low profile on various electronic circuit boards, a direct chip attach method using an unpackaged semiconductor chip (bare chip) has attracted attention. For example, in flip chip mounting, which is a representative of this method, the so-called “C4 technology” is known, in which high melting point solder bumps are formed on the semiconductor chip side and metal-to-metal bonding with the solder on the ceramic circuit board side is performed.

ところで、セラミック回路基板の代わりにガラスエポキシ樹脂等の樹脂系回路基板を用いた場合には、半導体チップと樹脂系回路基板との熱膨張係数の違いに起因して半田バンプの接合部に破壊が生じることがあり、この対策として、半導体チップと樹脂系回路基板との間を熱硬化性の液状樹脂組成物で封止し、熱応力を分散させて接続の信頼性を向上するという技術、いわゆるアンダーフィルが行われている。   By the way, when a resin circuit board such as a glass epoxy resin is used instead of a ceramic circuit board, the solder bump joint is broken due to the difference in thermal expansion coefficient between the semiconductor chip and the resin circuit board. As a countermeasure against this, a technique of sealing the space between the semiconductor chip and the resin circuit board with a thermosetting liquid resin composition and dispersing thermal stress to improve connection reliability, so-called Underfill is being performed.

図７は、アンダーフィルの概念図である。この図において、まず、（ａ）に示すように、フェイス面に多数のバンプ１ａを形成した半導体チップ１のフェイス面を下向きに（フェイスダウン）した状態でインタポーザ２の所定位置に載置し、半田溶融工程で、半導体チップ１のバンプ１ａとインタポーザ２の半田２ａとの金属間接合を行った後、（ｂ）に示すように、半導体チップ１とインタポーザ２の間の空隙に毛細管現象を利用して熱硬化性の液状樹脂組成物３を充填し、（ｃ）に示すように、熱を加えて硬化させることにより液状樹脂組成物３の固化物（以下、アンダーフィル４という）を形成する。   FIG. 7 is a conceptual diagram of underfill. In this figure, first, as shown in (a), the face surface of the semiconductor chip 1 having a large number of bumps 1a formed on the face surface is placed at a predetermined position of the interposer 2 with the face surface facing downward (face down). In the solder melting process, after the metal bonding between the bump 1a of the semiconductor chip 1 and the solder 2a of the interposer 2 is performed, a capillary phenomenon is used in the gap between the semiconductor chip 1 and the interposer 2 as shown in FIG. Then, the thermosetting liquid resin composition 3 is filled, and as shown in (c), a solidified product of the liquid resin composition 3 (hereinafter referred to as an underfill 4) is formed by applying heat to cure. .

適切に形成されたアンダーフィル４は、（ｄ）に示すように、半導体チップ１の４側面からのはみ出し（フィレット）がそれぞれほぼ均等であり、しかも、半導体チップ１の各側面を過不足なく覆っているが、不適切に形成されたアンダーフィル４は、たとえば、（ｅ）に示すように、半導体チップ１の一つまたは複数の側面のアンダーフィル４のフィレットが不足（ア部参照）したり、または、（ｆ）に示すように、大きなフィレット（イ部参照）になったり、あるいは、半導体チップ１の表面の全部または一部を覆って（ウ部参照）しまったりする。ア部の発生原因は液状樹脂組成物３の充填量不足であり、イ部及びウ部の発生原因は液状樹脂組成物３の充填量過剰である。   Properly formed underfill 4 has substantially uniform protrusions (fillets) from the four side surfaces of the semiconductor chip 1 as shown in (d), and covers each side surface of the semiconductor chip 1 without excess or deficiency. However, the underfill 4 formed improperly, for example, as shown in (e), the fillet of the underfill 4 on one or a plurality of side surfaces of the semiconductor chip 1 is insufficient (see (a)). Or, as shown in (f), it becomes a large fillet (refer to the portion A), or covers the whole or part of the surface of the semiconductor chip 1 (refer to the portion C). The cause of occurrence of the part a is an insufficient filling amount of the liquid resin composition 3, and the cause of the occurrence of the part a and the part c is an excess filling amount of the liquid resin composition 3.

液状樹脂組成物３の充填量不足は、アンダーフィルの本来の目的、すなわち、半導体チップ１とインタポーザ２（特に樹脂系回路基板）との間を熱硬化性の液状樹脂組成物で封止し、熱応力を分散させて電気的接続の信頼性を向上することを阻害するおそれがあるため、検査工程で確実に見つけ出さなければならない。また、液状樹脂組成物３の充填量過剰は、アンダーフィルの本来の目的を阻害しないが、たとえば、大きなフィレット（イ部）は見た目が悪く、商品価値を損なうため、これも、検査工程で確実に見つけ出す必要がある。半導体チップ１の表面の全部や一部を覆っている（ウ部参照）場合も同様である。   The insufficient filling amount of the liquid resin composition 3 is the original purpose of the underfill, that is, the space between the semiconductor chip 1 and the interposer 2 (particularly the resin circuit board) is sealed with a thermosetting liquid resin composition, Since it may hinder the distribution of thermal stress to improve the reliability of the electrical connection, it must be reliably found in the inspection process. In addition, the excessive filling amount of the liquid resin composition 3 does not hinder the original purpose of the underfill, but, for example, a large fillet (a portion) looks bad and impairs the commercial value. Need to find out. The same applies to the case where the whole or part of the surface of the semiconductor chip 1 is covered (see section C).

一般的に液状樹脂組成物３の塗布は、生産性を上げるために自動塗布機を用いて行われることが多い。しかしながら、小型化が要求される回路製品の場合は必然的にアンダーフィル４も微小化し、このため、自動機を用いて非常に微小なエリアに液状樹脂組成物３を塗布しなければならず、高精度な自動塗布機をもってしても、アンダーフィル４の不良（前記のア部、イ部、ウ部など）を絶無化することはきわめて難しい。   In general, the application of the liquid resin composition 3 is often performed using an automatic coating machine in order to increase productivity. However, in the case of circuit products that require miniaturization, the underfill 4 is inevitably miniaturized. For this reason, the liquid resin composition 3 must be applied to a very small area using an automatic machine. Even with a high-precision automatic coating machine, it is extremely difficult to eliminate defects in the underfill 4 (the above-mentioned parts a, b, c).

こうした背景から、通常は、液状樹脂組成物３の塗布後や硬化形成後に、アンダーフィル４のフィレット良否を判断するための外観検査を行っている。   From such a background, the appearance inspection for judging the quality of the fillet of the underfill 4 is usually performed after the application of the liquid resin composition 3 or after the curing formation.

外観検査の方法の一つは検査員による目視検査である。しかしながら、目視検査は人的コストがかさむ上、小型化された回路製品のアンダーフィル形成部分は非常に微細で見にくいため、検査のバラツキも大きく、安定した検査精度を維持できない。一方、画像認識等による自動化された外観検査も可能ではあるが、この場合には、アンダーフィル４のフィレットの有無やフィレット形状を判定するための高精度なカメラや画像処理装置が必要であり、設備コストが嵩むという不都合がある。   One of the visual inspection methods is visual inspection by an inspector. However, the visual inspection increases human cost, and the underfill-formed portion of the miniaturized circuit product is very fine and difficult to see. Therefore, the inspection varies greatly, and stable inspection accuracy cannot be maintained. On the other hand, automated appearance inspection by image recognition or the like is also possible, but in this case, a highly accurate camera and image processing device for determining the presence or absence of the fillet of the underfill 4 and the fillet shape are necessary. There is a disadvantage that the equipment cost increases.

このように、従来のアンダーフィルの外観検査は、信頼性の点やコストの点で課題があり、精度よく、しかも、低コストで簡単に検査できる手法が望まれていた。   As described above, the conventional appearance inspection of the underfill has problems in terms of reliability and cost, and a technique that can be easily inspected with high accuracy and at low cost has been desired.

特許文献１には、回路基板へ実装されたベアチップ単体の電気的特性検査を容易に行うための技術が記載されている。この技術では、ベアチップ外周にバンプ接続部から電気的に配線された検査用パッドを形成し、測定機器からの配線をその検査用パッドに接続することにより、ベアチップ単体の特性検査を可能としている。この技術によれば、アンダーフィルで封止されたバンプ接合部を破壊することなく、回路製品の不良要因を特定することが可能であり、製造コストの低減を期待できるとされている。   Patent Document 1 describes a technique for easily performing an electrical characteristic inspection of a bare chip mounted on a circuit board. In this technique, an inspection pad that is electrically wired from the bump connection portion is formed on the outer periphery of the bare chip, and the wiring from the measuring device is connected to the inspection pad, thereby enabling the characteristic inspection of the bare chip alone. According to this technique, it is possible to specify a cause of a defect in a circuit product without destroying a bump joint portion sealed with an underfill, and a reduction in manufacturing cost can be expected.

特開平１０−２４２２０６号公報JP-A-10-242206

しかしながら、特許文献１に記載された技術にあっては、回路基板上に形成されたパターンはあくまで特性検査用のパッドにすぎず、アンダーフィル外観検査の効率化を意図して設計されたものではない。したがって、精度よく、しかも、低コストで簡単にアンダーフィルの外観検査を行うための課題解決に利用できない。   However, in the technique described in Patent Document 1, the pattern formed on the circuit board is merely a pad for characteristic inspection, and is not designed to improve the efficiency of underfill appearance inspection. Absent. Therefore, it cannot be used for solving the problem for performing the underfill appearance inspection easily with high accuracy and at low cost.

そこで、本発明の目的は、精度よく、しかも、低コストで簡単にアンダーフィルの外観検査を行うことができる半導体実装基板、半導体実装用基板、その外観検査方法及び外観検査装置を提供することにある。   Accordingly, an object of the present invention is to provide a semiconductor mounting substrate, a semiconductor mounting substrate, an appearance inspection method, and an appearance inspection apparatus capable of performing an underfill appearance inspection with high accuracy and at low cost. is there.

請求項１記載の発明は、半導体チップがフェイスダウン実装された基板と、前記半導体チップと前記基板の間に充填されたアンダーフィルとを含み、前記基板上の半導体チップ実装領域に対応させて、前記基板表面及び前記アンダーフィルに対して識別可能な検査パターンが形成されたことを特徴とする半導体実装基板である。
請求項２記載の発明は、前記検査パターンは、前記基板表面及び前記アンダーフィルとのコントラスト差により画像識別可能であることを特徴とする請求項１記載の半導体実装基板である。
請求項３記載の発明は、前記検査パターンは、前記アンダーフィルのフィレットが適正な長さの場合に、その検査パターンのすべてが当該アンダーフィルによって隠されてしまう位置及び形状であることを特徴とする請求項１記載の半導体実装基板である。
請求項４記載の発明は、半導体チップをフェイスダウン実装し、前記半導体チップとの間にアンダーフィルが形成される半導体実装用基板において、前記基板上の半導体チップ実装領域に対応して、前記基板表面及び前記アンダーフィルに対して識別可能な検査パターンが形成されていることを特徴とする半導体実装用基板である。
請求項５記載の発明は、前記検査パターンは、前記基板表面及び前記アンダーフィルとのコントラスト差により画像識別可能であることを特徴とする請求項４記載の半導体実装用基板である。
請求項６記載の発明は、前記検査パターンは、前記アンダーフィルのフィレットが適正な長さの場合に、その検査パターンのすべてが当該アンダーフィルによって隠されてしまう位置及び形状であることを特徴とする請求項４記載の半導体実装用基板である。
請求項７記載の発明は、半導体チップがフェイスダウン実装され、前記半導体チップとの間にアンダーフィルが形成されている基板の外観検査方法であって、前記基板上の半導体チップ実装領域に対応して、前記基板表面及び前記アンダーフィルに対し、検査パターンを識別することにより、前記アンダーフィル形成の良否を判定することを特徴とする外観検査方法である。
請求項８記載の発明は、半導体チップがフェイスダウン実装され、前記半導体チップとの間にアンダーフィルを形成した後の基板の画像を撮影する撮影手段と、前記撮影手段によって撮影された画像を二値化画像に変換する二値化画像変換手段と、前記二値化画像中に、前記基板上の半導体チップ実装領域に対応して、前記基板表面及び前記アンダーフィルに対し、検査パターンが含まれているか否かを判定する判定手段と、前記判定手段の判定結果を報知する報知手段とを備えたことを特徴とする外観検査装置である。 The invention according to claim 1 includes a substrate on which a semiconductor chip is mounted face-down, and an underfill filled between the semiconductor chip and the substrate, corresponding to a semiconductor chip mounting region on the substrate, The semiconductor mounting substrate is characterized in that an inspection pattern which can be identified with respect to the substrate surface and the underfill is formed.
According to a second aspect of the present invention, in the semiconductor mounting substrate according to the first aspect, the inspection pattern can be identified by a contrast difference between the substrate surface and the underfill.
The invention according to claim 3 is characterized in that, when the fillet of the underfill has an appropriate length, the inspection pattern has a position and a shape in which all of the inspection pattern is hidden by the underfill. The semiconductor mounting substrate according to claim 1.
According to a fourth aspect of the present invention, in a semiconductor mounting substrate in which a semiconductor chip is face-down mounted and an underfill is formed between the semiconductor chip and the semiconductor chip, the substrate corresponds to a semiconductor chip mounting region on the substrate. A semiconductor mounting substrate characterized in that an inspection pattern distinguishable from the surface and the underfill is formed.
According to a fifth aspect of the present invention, in the semiconductor mounting substrate according to the fourth aspect, the image of the inspection pattern can be identified by a contrast difference between the surface of the substrate and the underfill.
The invention according to claim 6 is characterized in that, when the fillet of the underfill has an appropriate length, the inspection pattern has a position and a shape in which all of the inspection pattern is hidden by the underfill. The semiconductor mounting substrate according to claim 4.
The invention according to claim 7 is a method for inspecting the appearance of a substrate in which a semiconductor chip is mounted face-down and an underfill is formed between the semiconductor chip and the semiconductor chip, and corresponds to a semiconductor chip mounting region on the substrate. The visual inspection method is characterized in that the quality of the underfill is determined by identifying an inspection pattern for the substrate surface and the underfill.
According to an eighth aspect of the present invention, a semiconductor chip is mounted face-down and an image of the substrate after an underfill is formed between the semiconductor chip and an image photographed by the photographing means. A binarized image converting means for converting to a binarized image, and the binarized image includes an inspection pattern for the substrate surface and the underfill corresponding to a semiconductor chip mounting region on the substrate. An appearance inspection apparatus comprising: a determination unit that determines whether or not the image is determined; and a notification unit that notifies a determination result of the determination unit.

本発明によれば、基板上に形成された検査パターンの見え方により、アンダーフィル形成の良否を判定できる。すなわち、アンダーフィルを形成するための液状樹脂組成物の充填量が不十分であれば、検査パターンの全部または一部が露出し、一方、液状樹脂組成物の充填量が必要充分であれば、検査パターンのすべてがアンダーフィルで覆われるが、検査パターンと基板及びアンダーフィルが識別可能になっているため、検査パターンの露出の有無を容易に識別できる。したがって、目視検査の精度を高めることができる。また、汎用のカメラ等を組み合わせて簡単な自動化システムを構築することもでき、大幅なコストアップを招くこともない。   According to the present invention, the quality of underfill formation can be determined by the appearance of the inspection pattern formed on the substrate. That is, if the filling amount of the liquid resin composition for forming the underfill is insufficient, all or part of the inspection pattern is exposed, while if the filling amount of the liquid resin composition is necessary and sufficient, Although all of the inspection pattern is covered with underfill, since the inspection pattern, the substrate, and the underfill can be identified, the presence or absence of the inspection pattern can be easily identified. Therefore, the accuracy of visual inspection can be increased. In addition, a simple automation system can be constructed by combining general-purpose cameras and the like, which does not cause a significant cost increase.

以下、本発明の実施形態を、フリップチップを例にして、図面を参照しながら説明する。なお、以下の説明における様々な細部の特定ないし実例および数値や文字列その他の記号の例示は、本発明の思想を明瞭にするための、あくまでも参考であって、それらのすべてまたは一部によって本発明の思想が限定されないことは明らかである。また、周知の手法、周知の手順、周知のアーキテクチャおよび周知の回路構成等（以下「周知事項」）についてはその細部にわたる説明を避けるが、これも説明を簡潔にするためであって、これら周知事項のすべてまたは一部を意図的に排除するものではない。かかる周知事項は本発明の出願時点で当業者の知り得るところであるので、以下の説明に当然含まれている。   Hereinafter, embodiments of the present invention will be described with reference to the drawings, taking a flip chip as an example. It should be noted that the specific details or examples in the following description and the illustrations of numerical values, character strings, and other symbols are only for reference in order to clarify the idea of the present invention, and the present invention may be used in whole or in part. Obviously, the idea of the invention is not limited. In addition, a well-known technique, a well-known procedure, a well-known architecture, a well-known circuit configuration, and the like (hereinafter, “well-known matter”) are not described in detail, but this is also to simplify the description. Not all or part of the matter is intentionally excluded. Such well-known matters are known to those skilled in the art at the time of filing of the present invention, and are naturally included in the following description.

図１は、本実施形態における半導体実装回路用基板１０（基板、半導体実装基板、半導体実装用基板）の外観図である。この図において、半導体実装回路用基板１０は、特にそれに限定されないが、ここでは、不図示の半導体チップ（図７の半導体チップ１参照）と、これも不図示の回路基板との間の電気的接続を中継するためのインタポーザであるものとする。半導体実装回路用基板１０の一方面１０ａ（半導体チップの実装面）には、半導体チップを実装するための半導体チップ実装領域１１が設けられており、この半導体チップ実装領域１１には、半導体チップのフェイス面に形成されたバンプ（図７のバンプ１ａ参照）と金属間接合する多数の半田１１ａが設けられている。   FIG. 1 is an external view of a semiconductor mounting circuit board 10 (substrate, semiconductor mounting board, semiconductor mounting board) in the present embodiment. In this figure, the substrate 10 for a semiconductor mounting circuit is not particularly limited thereto, but here, an electrical circuit between a semiconductor chip (not shown) (see the semiconductor chip 1 in FIG. 7) and a circuit board (not shown) as well. It is assumed that it is an interposer for relaying connections. A semiconductor chip mounting region 11 for mounting a semiconductor chip is provided on one surface 10a (semiconductor chip mounting surface) of the substrate 10 for semiconductor mounting circuit. The semiconductor chip mounting region 11 includes a semiconductor chip mounting region 11. A large number of solders 11a are provided for bonding between bumps (see bump 1a in FIG. 7) formed on the face surface and metal.

さて、半導体実装回路用基板１０は、ガラスエポキシ樹脂等の樹脂系回路基板であり、冒頭で説明したとおり、この樹脂系回路基板は、半導体チップとの熱膨張係数の違いに起因して半田バンプの接合部に破壊が生じることがあり、この対策として、半導体チップと樹脂系回路基板（半導体実装回路用基板１０）との間を熱硬化性の液状樹脂組成物で封止し、熱応力を分散させて接続の信頼性を向上するという技術、いわゆるアンダーフィルが行われる。   The semiconductor mounting circuit board 10 is a resin circuit board such as a glass epoxy resin. As explained at the beginning, this resin circuit board is a solder bump due to a difference in thermal expansion coefficient from that of a semiconductor chip. As a countermeasure against this, the gap between the semiconductor chip and the resin circuit board (semiconductor mounting circuit board 10) is sealed with a thermosetting liquid resin composition to prevent thermal stress. A technique of improving the reliability of connection by dispersing, so-called underfill is performed.

本実施形態の主題は、アンダーフィルの良否判定を、精度よく、しかも、低コストで簡単に行うことにある。そのための特徴的事項として、本実施形態では、半導体実装回路用基板１０の一方面１０ａの所定位置に所定形状の検査マーク１２ａ〜１２ｄを形成している。   The subject of this embodiment is to perform underfill pass / fail judgment easily with high accuracy and at low cost. As a characteristic matter for that purpose, in the present embodiment, inspection marks 12a to 12d having a predetermined shape are formed at predetermined positions on one surface 10a of the substrate 10 for semiconductor mounting circuit.

検査マーク１２ａ〜１２ｄの位置及び形状は、適正なアンダーフィルが行われたときに、そのアンダーフィルの下に検査マーク１２ａ〜１２ｄのすべてが隠れてしまう位置及び形状であればよく、たとえば、図示のように、半導体チップ実装領域１１の外形線（破線）上であって、且つ、その外形線から外側に若干はみ出す位置及び形状としてもよい。具体的な“はみ出し量”については後述するが、検査マーク１２ａ〜１２ｄの形状は、たとえば、図示のように、長手方向を半導体チップ実装領域１１の外形線方向に合わせた長方形としてもよい。   The positions and shapes of the inspection marks 12a to 12d may be any positions and shapes that would hide all of the inspection marks 12a to 12d under the underfill when appropriate underfill is performed. As described above, the position and shape may be on the outline (broken line) of the semiconductor chip mounting region 11 and slightly protrude outward from the outline. Although the specific “protruding amount” will be described later, the shapes of the inspection marks 12 a to 12 d may be, for example, a rectangle in which the longitudinal direction is aligned with the outline direction of the semiconductor chip mounting region 11 as illustrated.

アンダーフィルは、冒頭で説明したように、熱硬化性の液状樹脂組成物の固化物であり、固化状態のアンダーフィルの色はほぼ“黒色または灰色”（以下、黒色とする）である。また、半導体実装回路用基板１０の一方面１０ａは、半導体チップ実装領域１１内の半田１１ａと検査マーク１２ａ〜１２ｄを除きソルダレジストで覆われており、このソルダレジストの色は多くの場合ほぼ“緑色”である。   As explained at the beginning, the underfill is a solidified product of a thermosetting liquid resin composition, and the color of the solidified underfill is almost “black or gray” (hereinafter referred to as black). Further, the one surface 10a of the semiconductor mounting circuit board 10 is covered with a solder resist except for the solder 11a and the inspection marks 12a to 12d in the semiconductor chip mounting region 11, and the color of the solder resist is almost " “Green”.

本実施形態の特徴的事項である検査マーク１２ａ〜１２ｄは、これらの色（黒色や緑色）に対して、目視識別または画像識別可能であること、つまり、コントラスト差が大きい色を有していることがポイントである。たとえば、検査マーク１２ａ〜１２ｄを、Ｃｕ、Ａｇ、Ｎｉ、Ｓｎまたは半田などの金属パターンで形成した場合、その金属パターンの表面は光をよく反射するため、高コントラストの高輝度色となる。あるいは、金属パターンでなく、レジンやシルクなどの樹脂材を用いて検査マーク１２ａ〜１２ｄを形成してもよい。同様に、それらの樹脂表面は光をよく反射するので、高コントラストの高輝度色となる。   The inspection marks 12a to 12d, which are characteristic items of the present embodiment, have such colors (black and green) that are visually identifiable or image identifiable, that is, have a color with a large contrast difference. That is the point. For example, when the inspection marks 12a to 12d are formed of a metal pattern such as Cu, Ag, Ni, Sn, or solder, the surface of the metal pattern reflects light well, so that a high brightness color with high contrast is obtained. Alternatively, the inspection marks 12a to 12d may be formed using a resin material such as resin or silk instead of the metal pattern. Similarly, those resin surfaces reflect light well, resulting in a high-contrast, high-luminance color.

図２は、本実施形態におけるアンダーフィル外観検査の概念図であり、（ａ）は外観検査の結果が“良”（ＯＫ）の場合、（ｂ）は外観検査の結果が“否”（ＮＧ）の場合である。まず、半導体実装回路用基板１０の一方面１０ａに半導体チップ１を載置し、半田溶融工程で、半導体チップ１のバンプと半導体実装回路用基板１０の半田との金属間接合を行った後、半導体チップ１と半導体実装回路用基板１０の間の空隙に毛細管現象を利用して熱硬化性の液状樹脂組成物を充填し、熱を加えて硬化させることによりアンダーフィル４を形成する。このアンダーフィル４が適量である場合、（ａ）に示すように、４つの検査マーク１２ａ〜１２ｄはアンダーフィル４の下に隠れて見えなくなる。   2A and 2B are conceptual diagrams of the underfill appearance inspection in the present embodiment. FIG. 2A is a case where the result of the appearance inspection is “good” (OK), and FIG. ). First, after placing the semiconductor chip 1 on the one surface 10a of the semiconductor mounting circuit board 10 and performing the metal-metal bonding between the bumps of the semiconductor chip 1 and the solder of the semiconductor mounting circuit board 10 in the solder melting step, The underfill 4 is formed by filling a space between the semiconductor chip 1 and the substrate 10 for semiconductor mounting circuit with a thermosetting liquid resin composition using a capillary phenomenon and curing it by applying heat. When the underfill 4 is an appropriate amount, the four inspection marks 12a to 12d are hidden under the underfill 4 and cannot be seen as shown in FIG.

これに対して、たとえば、液状樹脂組成物を充填量が不足していた場合は、アンダーフィル４のフィレットの一部が小さくなり、その部分の検査マーク（図では左側の検査マーク１２ｂ）が露出する。   On the other hand, for example, when the filling amount of the liquid resin composition is insufficient, a part of the fillet of the underfill 4 becomes small, and the inspection mark (the inspection mark 12b on the left side in the drawing) of the part is exposed. To do.

ここで、検査マーク１２ａ〜１２ｄの色は、アンダーフィル４の色（黒色）や半導体実装回路用基板１０の一方面１０ａの色（緑色）よりもコントラスト差が大きい色であるため、たとえ目視であったとしても、上記の検査マークの“露出”状態、つまり、不適切なアンダーフィル４を確実に見つけ出すことができる。   Here, the colors of the inspection marks 12a to 12d are colors having a larger contrast difference than the color of the underfill 4 (black) and the color of the one surface 10a of the semiconductor mounting circuit board 10 (green). Even if it exists, the “exposed” state of the inspection mark, that is, the inappropriate underfill 4 can be surely found.

しかも、かかる検査は、アンダーフィル４の色（黒色）や半導体実装回路用基板１０の一方面１０ａの色（緑色）と検査マーク１２ａ〜１２ｄの色とのコントラストの違いに基づいて行っているため、大がかりなシステムを用いることなく、簡易な仕組みで自動化も可能である。   Moreover, such inspection is performed based on the difference in contrast between the color of the underfill 4 (black) or the color of the one surface 10a (green) of the semiconductor mounting circuit board 10 and the colors of the inspection marks 12a to 12d. It is possible to automate with a simple mechanism without using a large-scale system.

図３は、本実施形態におけるアンダーフィル外観検査の自動化の概念図である。この図において、カメラ１３（撮影手段）は、光源１４、１５からの光で照明された被検査物（ここでは、半導体チップ１を実装しアンダーフィル４を形成した半導体実装回路用基板１０）表面の多階調カラー画像または多階調モノクロ画像（以下、単に画像１６という。）を撮影する。この画像は二値化処理部１７（二値化画像変換手段）に送られ、二値化処理部１７で所定の閾値ＳＬを用いて二値化画像１８に変換された後、良否判定部１９（判定手段）でアンダーフィルの外観良否が判定され、その判定結果が、たとえば、ＯＫランプ２０やＮＧランプ２１からなる報知手段２２で報知される。   FIG. 3 is a conceptual diagram of automation of the underfill appearance inspection in the present embodiment. In this figure, a camera 13 (photographing means) is a surface of an object to be inspected (here, a semiconductor mounting circuit substrate 10 on which a semiconductor chip 1 is mounted and an underfill 4 is formed) illuminated with light from light sources 14 and 15. A multi-tone color image or a multi-tone monochrome image (hereinafter simply referred to as an image 16) is taken. This image is sent to the binarization processing unit 17 (binarized image conversion means), converted into the binarized image 18 using the predetermined threshold SL by the binarization processing unit 17, and then the pass / fail judgment unit 19 (Determination means) determines the quality of the appearance of the underfill, and the determination result is notified by the notification means 22 including the OK lamp 20 and the NG lamp 21, for example.

二値化画像１８とは、閾値ＳＬよりも低い画素信号を黒レベル、閾値ＳＬを越える画素信号を白レベルにした画像である。今、閾値ＳＬを、アンダーフィル４の色（黒色）や半導体実装回路用基板１０の一方面１０ａの色（緑色）を黒レベルとすることができ、且つ、検査マーク１２ａ〜１２ｄの色を白レベルとすることができる適切な値に設定すれば、たとえば、図２（ａ）のような場合には、二値化画像１８のすべての画素信号が閾値ＳＬ以下になり、一方、図２（ｂ）のような場合には、二値化画像１８の一部（アンダーフィル４からはみ出している検査マーク１２ｂ）の画素信号が閾値ＳＬを越える。   The binarized image 18 is an image in which pixel signals lower than the threshold SL are set to the black level and pixel signals exceeding the threshold SL are set to the white level. Now, the threshold SL can be set to the black level for the color of the underfill 4 (black) and the color (green) of the one surface 10a of the semiconductor mounting circuit board 10, and the colors of the inspection marks 12a to 12d are white. If the level is set to an appropriate value, for example, in the case of FIG. 2A, all the pixel signals of the binarized image 18 are equal to or lower than the threshold value SL, while FIG. In the case of b), the pixel signal of a part of the binarized image 18 (inspection mark 12b protruding from the underfill 4) exceeds the threshold value SL.

したがって、二値化画像１８の閾値ＳＬを超える部分の有無を良否判定部１９で判断することにより、図２（ａ）のような場合には、ＯＫランプ２０を点灯してアンダーフィル４の“良”を報知し、または、図２（ｂ）のような場合には、ＮＧランプ２１を点灯してアンダーフィル４の“否”を報知することができ、アンダーフィルの外観検査の自動化を図ることができる。   Therefore, by determining whether or not there is a portion exceeding the threshold value SL of the binarized image 18, the OK lamp 20 is turned on in the case of FIG. In the case shown in FIG. 2B, the NG lamp 21 can be turned on to notify the “no” of the underfill 4 and the underfill visual inspection can be automated. be able to.

図４は、検査マーク１２ａ〜１２ｄの具体的な位置を示す概念図であり、とりわけ半導体チップ実装領域１１の外形線からの適切な“はみ出し量”を示す図である。この図において、Ｃは、半導体実装回路用基板１０の一方面１０ａから半導体チップ１の上面までの高さ（以下、フリップチップ実装高さ）である。また、Ｂは、半導体実装回路用基板１０と半導体チップ１の間の空隙（以下、フリップチップ接合部ギャップ）であり、さらに、Ａは、半導体チップ１の半導体チップ実装領域１１からの検査マーク１２ａ〜１２ｄの“はみ出し量”（以下、検査マーク外形位置）である。   FIG. 4 is a conceptual diagram showing specific positions of the inspection marks 12a to 12d. In particular, FIG. 4 is a diagram showing an appropriate “protruding amount” from the outline of the semiconductor chip mounting region 11. In this figure, C is the height from the one surface 10a of the semiconductor mounting circuit board 10 to the upper surface of the semiconductor chip 1 (hereinafter referred to as flip chip mounting height). B is a gap between the semiconductor mounting circuit substrate 10 and the semiconductor chip 1 (hereinafter referred to as a flip-chip joint gap), and A is an inspection mark 12a from the semiconductor chip mounting region 11 of the semiconductor chip 1. ˜12d “extension amount” (hereinafter referred to as inspection mark outer shape position).

検査マーク外形位置Ａの適切な値は、（ａ）に示すように、アンダーフィル４のフィレットが小さい場合（液状樹脂組成物３の充填量が不足している場合）に検査マーク１２ａ〜１２ｄの一部が露出し、且つ、（ｂ）に示すように、アンダーフィル４のフィレットが大きい場合（液状樹脂組成物３の充填量が適量の場合）に検査マーク１２ａ〜１２ｄのすべてがアンダーフィル４の下に隠れる値に設定する。   Appropriate values for the inspection mark outer shape position A are as shown in FIG. 5A when the fillet of the underfill 4 is small (when the filling amount of the liquid resin composition 3 is insufficient). When a part is exposed and the fillet of the underfill 4 is large as shown in (b) (when the filling amount of the liquid resin composition 3 is appropriate), all of the inspection marks 12a to 12d are underfill 4. Set to a value hidden under.

さて、フリップチップ接合部ギャップＢに液状樹脂組成物３を充填した場合、その液状樹脂組成物３は毛細管現象によってフリップチップ接合部ギャップＢに入り込むとともに、そのフリップチップ接合部ギャップＢの外側にフィレットが形成される。フィレットの長さ（裾野の広がり）は、そのときの液状樹脂組成物３の充填量に依存し、たとえば、（ａ）のように、フリップチップ接合部ギャップＢの大きさ程度であれば、ほぼフリップチップ接合部ギャップＢに相当する大きさのフィレットになる。このときのフィレットの高さをＤmin、フィレットの長さをＥminとすると、Ｄmin≒Ｅmin≒Ｂ、したがって、「Ｅmin≒Ｂ≦Ａ」の関係にしておけば、上記一の条件、すなわち、「アンダーフィル４のフィレットが小さい場合（液状樹脂組成物３の充填量が不足している場合）に検査マーク１２ａ〜１２ｄの一部を露出させる」を満たすことができる。   Now, when the liquid resin composition 3 is filled in the flip chip joint gap B, the liquid resin composition 3 enters the flip chip joint gap B by capillary action, and fillets outside the flip chip joint gap B. Is formed. The length of the fillet (the spread of the skirt) depends on the filling amount of the liquid resin composition 3 at that time. For example, as shown in (a), if the size of the flip chip joint gap B is about the size, The fillet has a size corresponding to the flip chip joint gap B. If the height of the fillet at this time is Dmin and the length of the fillet is Emin, Dmin≈Emin≈B. Therefore, if the relationship of “Emin≈B ≦ A” is satisfied, the above one condition, that is, “under” When the fillet of the fill 4 is small (when the filling amount of the liquid resin composition 3 is insufficient), part of the inspection marks 12a to 12d is exposed ”.

一方、（ｂ）のように、液状樹脂組成物３の充填量が適量で、フィレットの高さがフリップチップ実装高さＣに相当する程度になった場合には、フィレットの長さが増加する。このときのフィレットの高さをＤmax、フィレットの長さをＥmaxとすると、Ｄmax≦Ｅmaxになる。このとき、Ｃ≦Ｅmaxであるから、「Ａ≦Ｃ≦Ｅmax」の関係にしておけば、上記二の条件、すなわち、「アンダーフィル４のフィレットが大きい場合（液状樹脂組成物３の充填量が適量の場合）に検査マーク１２ａ〜１２ｄのすべてをアンダーフィル４の下に隠す」を満たすことができる。   On the other hand, as shown in (b), when the filling amount of the liquid resin composition 3 is an appropriate amount and the height of the fillet is equivalent to the flip chip mounting height C, the length of the fillet increases. . If the height of the fillet at this time is Dmax and the length of the fillet is Emax, then Dmax ≦ Emax. At this time, since C ≦ Emax, if the relationship “A ≦ C ≦ Emax” is satisfied, the above two conditions, that is, “when the fillet of the underfill 4 is large (the filling amount of the liquid resin composition 3 is When all of the inspection marks 12a to 12d are concealed under the underfill 4, it can be satisfied.

したがって、上記の二つの関係（「Ｅmin≒Ｂ≦Ａ」と「Ａ≦Ｃ≦Ｅmax」）を合わせて、「フリップチップ接合部ギャップ（Ｂ）≦検査マーク外形位置（Ａ）≦フリップチップ実装高さ（Ｃ）」の関係にしておけば、上記一及び二の条件、すなわち、「アンダーフィル４のフィレットが小さい場合（液状樹脂組成物３の充填量が不足している場合）に検査マーク１２ａ〜１２ｄの一部を露出させる」と、「アンダーフィル４のフィレットが大きい場合（液状樹脂組成物３の充填量が適量の場合）に検査マーク１２ａ〜１２ｄのすべてをアンダーフィル４の下に隠す」とを共に満たすことができ、液状樹脂組成物３の充填量不足と適量とを正しく区別することができる。   Therefore, the above two relations (“Emin≈B ≦ A” and “A ≦ C ≦ Emax”) are combined, and “Flip chip joint gap (B) ≦ Inspection mark outline position (A) ≦ Flip chip mounting height” (C) ”, the inspection mark 12a can be obtained under the above-described one and two conditions, that is,“ when the fillet of the underfill 4 is small (when the filling amount of the liquid resin composition 3 is insufficient) ”. When a fillet of the underfill 4 is large (when the filling amount of the liquid resin composition 3 is appropriate), all of the inspection marks 12a to 12d are hidden under the underfill 4. And the liquid resin composition 3 can be correctly distinguished from the insufficient filling amount and the appropriate amount.

以上説明したとおり、本実施形態においては、半導体実装回路用基板１０の一方面１０ａ（半導体チップ実装面）に、この半導体実装回路用基板１０の表面のソルダレジストの色（緑色）、並びに、当該半導体実装回路用基板１０の一方面１０ａの半導体チップ実装領域１１に実装される半導体チップと当該半導体実装回路用基板１０の一方面１０ａとの間の空隙に充填して固化されるアンダーフィル４の色（黒色）と明らかにコントラストが異なる検査パターン１２ａ〜１２ｄを形成するとともに、その検査パターン１２ａ〜１２ｄの位置及び形状を、適切な適切なアンダーフィル４が形成された場合にそのアンダーフィル４のフィレットの影に隠れるように設定したので、仮に目視検査する場合であっても、単に検査パターン１２ａ〜１２ｄが外から見えるか否かだけを調べればよく、検査員毎のバラツキを無くして精度のよい検査を行うことができる。また、人的コストを抑えて、自動化する場合であっても、ＣＣＤやＣＭＯＳ等の汎用のカメラ１３に加え、光源１４、１５や二値化処理部１７及び良否判定部１９並びに報知手段２２などの簡単な回路の組み合わせで自動化検査システムを構築することができ、設備投資を抑制することもできる。   As described above, in this embodiment, the color (green) of the solder resist on the surface of the substrate 10 for semiconductor mounting circuit, the one surface 10a (semiconductor chip mounting surface) of the substrate 10 for semiconductor mounting circuit, The underfill 4 is filled and solidified in a gap between the semiconductor chip mounted on the semiconductor chip mounting region 11 on the one surface 10a of the semiconductor mounting circuit substrate 10 and the one surface 10a of the semiconductor mounting circuit substrate 10. The inspection patterns 12a to 12d which are clearly different in contrast from the color (black) are formed, and the positions and shapes of the inspection patterns 12a to 12d are changed to those of the underfill 4 when an appropriate appropriate underfill 4 is formed. Since the setting is made so as to be hidden behind the fillet shadow, even if a visual inspection is performed, the inspection patterns 12a-1 are simply used. Well by examining the d only whether externally visible, it is possible to perform good test accuracy by eliminating variations among inspectors. Further, even in the case of automation with reduced human cost, in addition to a general-purpose camera 13 such as a CCD or CMOS, the light sources 14 and 15, the binarization processing unit 17, the pass / fail judgment unit 19, the notification unit 22, etc. It is possible to construct an automated inspection system with a combination of simple circuits, and to suppress capital investment.

なお、以上の実施形態では、半導体実装回路用基板１０の一方面１０ａの半導体チップ実装領域１１の４辺のそれぞれに検査パターン１２ａ〜１２ｄを形成しているが、これに限定されない。   In the above embodiment, the test patterns 12a to 12d are formed on each of the four sides of the semiconductor chip mounting region 11 on the one surface 10a of the semiconductor mounting circuit board 10. However, the present invention is not limited to this.

図５は、検査パターンの他の例を示す図である。まず、（ａ）の例では、半導体実装回路用基板１０の一方面１０ａの半導体チップ実装領域１１の４辺のそれぞれに検査パターン１２ａ′〜１２ｄ′を形成している点で上記の実施形態（図１参照）と一致し、各々の検査パターン１２ａ′〜１２ｄ′を半導体チップ実装領域１１の４辺から若干量αだけ離隔している点で相違する。なお、この検査パターン１２ａ′〜１２ｄ′についても、前記の重要な関係、すなわち、「フリップチップ接合部ギャップ（Ｂ）≦検査マーク外形位置（Ａ）≦フリップチップ実装高さ（Ｃ）」を適用する。   FIG. 5 is a diagram illustrating another example of the inspection pattern. First, in the example of (a), the test patterns 12a ′ to 12d ′ are formed on each of the four sides of the semiconductor chip mounting region 11 on the one surface 10a of the substrate 10 for semiconductor mounting circuit. 1 is different from that shown in FIG. 1 in that the test patterns 12a ′ to 12d ′ are slightly separated from the four sides of the semiconductor chip mounting region 11 by an amount α. It should be noted that the above-mentioned important relationship, that is, “flip chip joint gap (B) ≦ inspection mark outline position (A) ≦ flip chip mounting height (C)” is also applied to the inspection patterns 12a ′ to 12d ′. To do.

このような検査パターン１２ａ′〜１２ｄ′にすると、パターン形成の無駄を省くことができる。すなわち、上記の離隔距離αはほとんどの場合、アンダーフィル４に隠れてしまう部分であり、この部分にパターンを形成する必要はなく、むしろ、パターンを形成しないことによって、検査パターン１２ａ′〜１２ｄ′の材料、たとえば、Ｃｕ、Ａｇ、Ａｕ、Ｎｉ、Ｓｎ、半田などの金属材料、または、レジンやシルクなどの樹脂材料の所要量を削減して無駄を省くことができるからである。   When such inspection patterns 12a ′ to 12d ′ are used, it is possible to eliminate waste of pattern formation. That is, in most cases, the above-mentioned separation distance α is a portion hidden behind the underfill 4, and it is not necessary to form a pattern in this portion. Rather, the inspection patterns 12 a ′ to 12 d ′ are not formed by forming no pattern. This is because, for example, the required amount of metal materials such as Cu, Ag, Au, Ni, Sn, and solder, or resin materials such as resin and silk can be reduced, thereby eliminating waste.

さらに、パターン形成の無駄を省く観点からは、（ｂ）や（ｃ）のようにしてもよい。すなわち、半導体チップ実装領域１１の４辺のそれぞれに細分化した検査パターン１２ａ″〜１２ｄ″を形成してもよい。各々の辺に形成する検査パターンの数は、図示のように各辺毎に３個であってもよいし、１個または２個ないしは３個以上であってもよい。（ｂ）や（ｃ）の違いは、半導体チップ実装領域１１の４辺から適量α離隔して検査パターン１２ａ″〜１２ｄ″を形成するか否かの点にある。このようにしても、検査パターン１２ａ″〜１２ｄ″を細分化した分だけパターン材料を少なくすることができ、特に、半導体チップ実装領域１１の４辺から適量α離隔して検査パターン１２ａ″〜１２ｄ″を形成した場合には、そのパターン材料の所要量を最小限にすることができる。   Furthermore, from the viewpoint of eliminating waste of pattern formation, (b) and (c) may be used. That is, the subdivided test patterns 12 a ″ to 12 d ″ may be formed on each of the four sides of the semiconductor chip mounting region 11. The number of inspection patterns formed on each side may be three as shown in the figure, or may be one, two, or three or more. The difference between (b) and (c) lies in whether or not the test patterns 12a ″ to 12d ″ are formed by being separated from the four sides of the semiconductor chip mounting region 11 by an appropriate amount α. Even in this case, the pattern material can be reduced by the amount obtained by subdividing the inspection patterns 12a ″ to 12d ″. In particular, the inspection patterns 12a ″ to 12d are separated from the four sides of the semiconductor chip mounting region 11 by an appropriate amount α. When "" is formed, the required amount of the pattern material can be minimized.

図６は、検査パターンの更に他の例を示す図である。この図において、白抜き矢印は、アンダーフィル４を形成する際の液状樹脂組成物の充填方向である。今、液状樹脂組成物の半導体実装用回路基板１０への濡れ性が充分に良好な場合は、半導体チップ実装領域１１の上辺（充填方向の下流側に位置する辺）のみに検査マーク１２ａ（または検査マーク１２ａ′若しくはそれらを細分化した検査マーク１２ａ″）を形成することができる。充填された液状樹脂組成物は白抜き矢印の方向に流入し、その流入先に位置する検査マーク１２ａ（または検査マーク１２ａ′若しくはそれらを細分化した検査マーク１２ａ″）の上にフィレットが形成されるからであり、当該フィレットの長さが液状樹脂組成物の充填量に対応するからである。このようにすると、検査マーク１２ａ（または検査マーク１２ａ′若しくはそれらを細分化した検査マーク１２ａ″）の数を少なくすることができ、パターン材料の所要量を更に抑制することができる。   FIG. 6 is a diagram showing still another example of the inspection pattern. In this figure, the white arrow is the filling direction of the liquid resin composition when the underfill 4 is formed. If the wettability of the liquid resin composition to the circuit board 10 for semiconductor mounting is sufficiently good now, the inspection mark 12a (or only on the upper side (side located downstream in the filling direction) of the semiconductor chip mounting region 11 The inspection mark 12a ′ or the inspection mark 12a ″ obtained by subdividing them can be formed. The filled liquid resin composition flows in the direction of the white arrow, and the inspection mark 12a (or the inflow destination) is located. This is because the fillet is formed on the inspection mark 12a ′ or the inspection mark 12a ″) obtained by subdividing them, and the length of the fillet corresponds to the filling amount of the liquid resin composition. In this way, the number of inspection marks 12a (or inspection marks 12a ′ or inspection marks 12a ″ obtained by subdividing them) can be reduced, and the required amount of pattern material can be further suppressed.

本発明は、以上の実施形態に限定されることなく、その技術思想の範囲内で様々な発展例や変形例を包含する。たとえば、フリップチップに限らず、アンダーフィルを形成する各種の半導体チップに適用できる。たとえば、回路基板にＢＧＡ（Ball Grid Array）接合されたＣＳＰ（Chip Size Package）であってもよい。また、半導体実装回路用基板１０は樹脂系基板のみならず、半導体チップとの熱膨張係数の違いに起因する半田接合の破壊等のおそれがある他の材質、たとえば、金属基板やフィルム基板などであってもよい。また、検査パターンについても、パターン印刷などのように基板上へ検査マークを堆積させる製法のみならず、たとえば、エッチングなどの化学的手法でマーク部分を除去する方法であってもよい。たとえば、樹脂系基板の場合、表層のソルダレジストをエッチングして下層の金属パターンを露出させ、これを検査マークとしてもよい。また、半導体実装回路用基板１０はインタポーザである必然性はない。パッケージングされていない半導体チップをフェイスダウンで実装する基板であればよく、通常のプリント回路基板であってもよい。   The present invention is not limited to the above embodiments, and includes various developments and modifications within the scope of the technical idea. For example, the present invention can be applied not only to flip chips but also to various semiconductor chips that form underfill. For example, a CSP (Chip Size Package) bonded to a circuit board by BGA (Ball Grid Array) may be used. Further, the semiconductor mounting circuit board 10 is not only a resin-based board, but also other materials that may cause breakage of solder joints due to a difference in thermal expansion coefficient with a semiconductor chip, such as a metal board or a film board. There may be. Further, the inspection pattern may be not only a manufacturing method in which an inspection mark is deposited on a substrate, such as pattern printing, but also a method of removing the mark portion by a chemical method such as etching. For example, in the case of a resin-based substrate, the solder resist on the surface layer may be etched to expose the lower metal pattern, which may be used as an inspection mark. Further, the semiconductor mounting circuit board 10 is not necessarily an interposer. Any substrate that mounts unpackaged semiconductor chips face-down may be used, and an ordinary printed circuit board may be used.

本実施形態における半導体実装回路用基板１０の外観図である。It is an external view of the board | substrate 10 for semiconductor mounting circuits in this embodiment. 本実施形態におけるアンダーフィル外観検査の概念図である。It is a conceptual diagram of the underfill external appearance inspection in this embodiment. 本実施形態におけるアンダーフィル外観検査の自動化の概念図である。It is a conceptual diagram of automation of the underfill external appearance inspection in this embodiment. 検査マーク１２ａ〜１２ｄの具体的な位置を示す概念図である。It is a conceptual diagram which shows the specific position of inspection mark 12a-12d. 検査パターンの他の例を示す図である。It is a figure which shows the other example of a test | inspection pattern. 検査パターンの更に他の例を示す図である。It is a figure which shows the further another example of a test | inspection pattern. アンダーフィルの概念図である。It is a conceptual diagram of an underfill.

符号の説明Explanation of symbols

１ 半導体チップ
４ アンダーフィル
１０ 半導体実装回路用基板（基板、半導体実装基板、半導体実装用基板）
１１ 半導体チップ実装領域
１２ａ 検査パターン
１２ｂ 検査パターン
１２ｃ 検査パターン
１２ｄ 検査パターン
１２ａ′ 検査パターン
１２ｂ′ 検査パターン
１２ｃ′ 検査パターン
１２ｄ′ 検査パターン
１２ａ″ 検査パターン
１２ｂ″ 検査パターン
１２ｃ″ 検査パターン
１２ｄ″ 検査パターン
１３ カメラ（撮影手段）
１７ 二値化処理部（二値化画像変換手段）
１９ 良否判定部（判定手段）
２２ 報知手段
1 Semiconductor chip 4 Underfill 10 Semiconductor mounting circuit board (substrate, semiconductor mounting board, semiconductor mounting board)
11 semiconductor chip mounting area 12a inspection pattern 12b inspection pattern 12c inspection pattern 12d inspection pattern 12a ′ inspection pattern 12b ′ inspection pattern 12c ′ inspection pattern 12d ′ inspection pattern 12a ″ inspection pattern 12b ″ inspection pattern 12c ″ inspection pattern 12d ″ inspection pattern 13 Camera (photographing means)
17 Binarization processing unit (binarized image conversion means)
19 Pass / fail judgment unit (determination means)
22 Notification means

Claims (8)

半導体チップがフェイスダウン実装された基板と、前記半導体チップと前記基板の間に充填されたアンダーフィルとを含み、
前記基板上の半導体チップ実装領域に対応させて、前記基板表面及び前記アンダーフィルに対して識別可能な検査パターンが形成されたことを特徴とする半導体実装基板。 A substrate on which a semiconductor chip is mounted face down, and an underfill filled between the semiconductor chip and the substrate,
A semiconductor mounting substrate, wherein an inspection pattern that can be identified with respect to the surface of the substrate and the underfill is formed corresponding to a semiconductor chip mounting region on the substrate. 前記検査パターンは、前記基板表面及び前記アンダーフィルとのコントラスト差により画像識別可能であることを特徴とする請求項１記載の半導体実装基板。 The semiconductor mounting substrate according to claim 1, wherein the inspection pattern is image-identifiable by a contrast difference between the substrate surface and the underfill. 前記検査パターンは、前記アンダーフィルのフィレットが適正な長さの場合に、その検査パターンのすべてが当該アンダーフィルによって隠されてしまう位置及び形状であることを特徴とする請求項１記載の半導体実装基板。 2. The semiconductor mounting according to claim 1, wherein when the underfill fillet has an appropriate length, the inspection pattern has a position and a shape in which all of the inspection pattern is hidden by the underfill. substrate. 半導体チップをフェイスダウン実装し、前記半導体チップとの間にアンダーフィルが形成される半導体実装用基板において、
前記基板上の半導体チップ実装領域に対応して、前記基板表面及び前記アンダーフィルに対して識別可能な検査パターンが形成されていることを特徴とする半導体実装用基板。 In a semiconductor mounting substrate in which a semiconductor chip is mounted face down and an underfill is formed between the semiconductor chip,
A semiconductor mounting substrate, wherein a test pattern that can be identified with respect to the substrate surface and the underfill is formed corresponding to a semiconductor chip mounting region on the substrate. 前記検査パターンは、前記基板表面及び前記アンダーフィルとのコントラスト差により画像識別可能であることを特徴とする請求項４記載の半導体実装用基板。 5. The semiconductor mounting substrate according to claim 4, wherein the inspection pattern is image-identifiable by a contrast difference between the substrate surface and the underfill. 前記検査パターンは、前記アンダーフィルのフィレットが適正な長さの場合に、その検査パターンのすべてが当該アンダーフィルによって隠されてしまう位置及び形状であることを特徴とする請求項４記載の半導体実装用基板。 5. The semiconductor mounting according to claim 4, wherein when the underfill fillet has an appropriate length, the inspection pattern has a position and a shape in which all of the inspection pattern is hidden by the underfill. Substrate. 半導体チップがフェイスダウン実装され、前記半導体チップとの間にアンダーフィルが形成されている基板の外観検査方法であって、
前記基板上の半導体チップ実装領域に対応して、前記基板表面及び前記アンダーフィルに対し、検査パターンを識別することにより、前記アンダーフィル形成の良否を判定することを特徴とする外観検査方法。 A method for inspecting the appearance of a substrate in which a semiconductor chip is mounted face down and an underfill is formed between the semiconductor chip,
A visual inspection method for determining whether the underfill is good or bad by identifying an inspection pattern for the substrate surface and the underfill corresponding to a semiconductor chip mounting region on the substrate. 半導体チップがフェイスダウン実装され、前記半導体チップとの間にアンダーフィルを形成した後の基板の画像を撮影する撮影手段と、
前記撮影手段によって撮影された画像を二値化画像に変換する二値化画像変換手段と、
前記二値化画像中に、前記基板上の半導体チップ実装領域に対応して、前記基板表面及び前記アンダーフィルに対し、検査パターンが含まれているか否かを判定する判定手段と、
前記判定手段の判定結果を報知する報知手段と
を備えたことを特徴とする外観検査装置。 A photographing means for photographing an image of a substrate after a semiconductor chip is mounted face down and underfill is formed between the semiconductor chip,
Binarized image converting means for converting an image photographed by the photographing means into a binarized image;
In the binarized image, determination means for determining whether or not an inspection pattern is included for the substrate surface and the underfill corresponding to the semiconductor chip mounting region on the substrate;
An appearance inspection apparatus comprising: a notification unit that notifies a determination result of the determination unit.
JP2005101850A 2005-03-31 2005-03-31 Semiconductor mounting substrate, semiconductor mounting substrate, appearance inspection method and appearance inspection apparatus Active JP4235621B2 (en)

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WO2008065979A1 (en) * 2006-11-29 2008-06-05 Musashi Engineering, Inc. Method and device for placing liquid material
JP2009058484A (en) * 2007-09-03 2009-03-19 Nec Corp Fillet width inspecting apparatus for electronic component
US7622311B1 (en) * 2005-11-30 2009-11-24 Advanced Micro Devices, Inc. Inspection of underfill in integrated circuit package
CN108198766A (en) * 2017-12-29 2018-06-22 英特尔产品（成都）有限公司 Chip package defect inspection and processing method, system and storage device
JP2021184414A (en) * 2020-05-21 2021-12-02 三菱電機株式会社 Semiconductor device, power conversion device, semiconductor device inspection method, semiconductor device manufacturing method, learning device, and inference device
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Publication number Priority date Publication date Assignee Title
US7622311B1 (en) * 2005-11-30 2009-11-24 Advanced Micro Devices, Inc. Inspection of underfill in integrated circuit package
WO2008065979A1 (en) * 2006-11-29 2008-06-05 Musashi Engineering, Inc. Method and device for placing liquid material
JP2008132440A (en) * 2006-11-29 2008-06-12 Musashi Eng Co Ltd Method and apparatus for filling liquid material
KR101457459B1 (en) * 2006-11-29 2014-11-03 무사시 엔지니어링 가부시키가이샤 Method and device for placing liquid material
TWI471953B (en) * 2006-11-29 2015-02-01 Musashi Engineering Inc Liquid material filling method and device
JP2009058484A (en) * 2007-09-03 2009-03-19 Nec Corp Fillet width inspecting apparatus for electronic component
CN108198766A (en) * 2017-12-29 2018-06-22 英特尔产品（成都）有限公司 Chip package defect inspection and processing method, system and storage device
JP2021184414A (en) * 2020-05-21 2021-12-02 三菱電機株式会社 Semiconductor device, power conversion device, semiconductor device inspection method, semiconductor device manufacturing method, learning device, and inference device
JP7446156B2 (en) 2020-05-21 2024-03-08 三菱電機株式会社 Semiconductor devices, power conversion devices, semiconductor device testing methods, semiconductor device manufacturing methods, learning devices, and inference devices
KR20210157882A (en) 2020-06-22 2021-12-29 토와 가부시기가이샤 Resin molding equipment and manufacturing method of resin molded products
JP2022001419A (en) * 2020-06-22 2022-01-06 Ｔｏｗａ株式会社 Resin molding apparatus and manufacturing method of resin molded product
JP7003184B2 (en) 2020-06-22 2022-01-20 Ｔｏｗａ株式会社 Resin molding equipment and manufacturing method of resin molded products

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