JP2006278949A - Inspecting device of semiconductor integrated circuit and its inspecting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reliably break an oxide film of a pad surface on the entire surface of a wafer with a contact of a low load to obtain a stable contact in the wafer in a lump. <P>SOLUTION: This inspecting device has an inspecting board 4 opposing to a surface of a semiconductor wafer 1; a wiring board 5 containing a wiring layer 5a; a cylindrical bump 7 and a dummy bump 8 provided in a region corresponding to an external pad 2A of the semiconductor wafer 1 in an elastic sheet 6 and having a smooth distal end; and an anisotropic conductive rubber sheet 10 provided between the wiring board 5 and the elastic sheet 6, for electrically connecting one end of the wiring layer 5a to an isolation pattern 9. The other end of the wiring layer 5a is connected to a power supply and the inspecting device for supplying an inspecting voltage. The pads on the semiconductor wafer 1 with which the bump 7 and the dummy bump 8 come into contact, respectively, are connected to each other through the wiring 3, and a voltage is applied to between the bump 7 and the dummy bump 8 by an external power source to make a breakdown of the oxide film on a surface of the external pad 2A. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit inspection apparatus and a semiconductor integrated circuit inspection method for collectively inspecting electrical characteristics of a plurality of semiconductor integrated circuit elements formed on a semiconductor wafer at a wafer level.

  2. Description of the Related Art Conventionally, a semiconductor device is supplied in a state where a semiconductor chip (semiconductor integrated circuit element) and a lead frame are electrically connected by a bonding wire, and then the inner leads of the semiconductor chip and the lead frame are sealed with resin or ceramics. And mounted on a printed circuit board.

  However, due to the demand for downsizing and cost reduction of electronic devices, a method for mounting a semiconductor chip on a circuit board in a state of being cut out from a semiconductor wafer (bare chip) has been developed. It is desired to supply at a low price. In order to guarantee a predetermined quality for the bare chip, it is preferable to perform a burn-in inspection on a plurality of semiconductor integrated circuit elements formed on the semiconductor wafer in terms of cost reduction. Therefore, a plurality of semiconductors formed on a semiconductor wafer using an inspection substrate having a probe terminal at a position facing each external electrode (pad) of the plurality of semiconductor integrated circuit elements formed on the semiconductor wafer. 2. Description of the Related Art A semiconductor integrated circuit inspection apparatus that collectively inspects electrical characteristics of integrated circuit elements at a wafer level has been proposed.

  FIG. 7 shows a cross-sectional structure of a conventional semiconductor integrated circuit inspection apparatus. A plurality of external pads 102 are provided on the surface of a plurality of semiconductor integrated circuit elements formed on a semiconductor wafer 101 (for example, , See Patent Document 1).

  An inspection substrate 104 is provided so as to face the surface of the semiconductor wafer 101. The inspection substrate 104 includes a wiring substrate 105 having a wiring layer 105a, an elastic sheet 107 made of, for example, polyimide resin, the periphery of which is fixed to the wiring substrate 105 by a rigid ring, and external pads of the semiconductor wafer 101 on the elastic sheet 107. 102, a hemispherical bump 108 provided at a portion corresponding to 102, an isolated pattern 109 made of, for example, copper integrally provided on the opposite side of the bump 108 in the elastic sheet 107, and the wiring board 105 and the elastic An anisotropic conductive rubber sheet 110 provided between the sheet 107 and electrically connecting one end portion of the wiring layer 105 a of the wiring substrate 105 and the isolated pattern 109 is provided. The anisotropic conductive rubber sheet 110 is provided with conductive particles 110a arranged in a straight line. One end of the wiring layer 105a and the isolated pattern 109 are electrically connected by the conductive particles 110a. Conducted.

  The other end of the wiring layer 105a in the wiring substrate 105 is connected to a burn-in inspection device (not shown) that supplies an inspection voltage such as a power supply voltage, a ground voltage, or a signal voltage.

  Further, an annular seal member 112 made of an elastic body having a lip cross section is provided around the wafer holding portion 111 a that holds the semiconductor wafer 101 in the wafer tray 111.

  A method for collectively inspecting the electrical characteristics of a plurality of semiconductor integrated circuit elements formed on the semiconductor wafer 101 using the conventional semiconductor integrated circuit inspection apparatus configured as described above will be described below.

  First, with each external pad 102 formed on the semiconductor wafer 101 and each bump 108 of the inspection substrate 104 facing each other, the wafer tray 111 and the inspection substrate 104 are brought close to each other to bring the wafer tray 111 and the annular seal. A sealed space 113 is formed by the member 112 and the inspection substrate 104.

  Next, when the sealed space 113 is depressurized, the cross-sectional shape of the annular seal member 112 is elastically deformed into an arcuate shape, so that the inspection substrate 104 and the wafer tray 111 are brought closer to each other and the bump 108 and the inspection external pad 102 are Touch each other.

In this state, a test voltage is applied from a tester body (not shown) to a plurality of external voltages via the wiring layer 105a of the wiring substrate 105, the conductive particles 110a of the anisotropic conductive rubber sheet 110, the isolated pattern 109, and the bumps 108. In addition to being applied to a part of the pad 102, an output signal output from another external pad 102 is input to a tester, and the electrical characteristics of each semiconductor integrated circuit element are evaluated.
JP 2004-93451 A

  In the conventional semiconductor integrated circuit inspection apparatus, when the sealed space 113 is depressurized, the inspection substrate 104 and the wafer tray 111 come close to each other and the hemispherical bump 108 and the external pad 102 contact each other in an area of several square microns. To do.

  However, when the external pad 102 is made of, for example, aluminum and the surface oxide film is formed extremely thick on the surface of the external pad 102 only by the conventional contact area and the contact load due to the pressure reduction force, or on the semiconductor wafer 101, an extremely large number of When the external pad 102 is provided and an extremely large number of bumps 108 are provided correspondingly, the load value per one external pad 102 is reduced. As a result, there is a problem that it often occurs that the bump 108 and the external pad 102 are not sufficiently electrically connected.

  An object of the present invention is to make it possible to sufficiently reduce the contact resistance between probe terminals (bumps) provided on an inspection substrate and pad electrodes provided on a semiconductor wafer.

  In order to achieve the above object, the present invention provides a semiconductor integrated circuit inspection apparatus for inspecting semiconductor integrated circuits at a wafer level in a lump, and smoothes the front end surface of a probe terminal of the inspection apparatus, and also provides a front end surface (contact surface). The structure in which the surface oxide film formed on the surface of the pad electrode is destroyed by applying a voltage from the outside in advance before the inspection is performed between the probe terminal having a smoothed surface and the pad electrode formed on the wafer. And

  Specifically, a first semiconductor integrated circuit inspection apparatus according to the present invention includes a semiconductor wafer on which a plurality of semiconductor integrated circuit elements and a plurality of external pads electrically connected to the plurality of semiconductor integrated circuit elements are formed. Between the wafer tray and the wiring board, the wafer tray having a wiring layer that is provided so as to face the main surface of the semiconductor wafer held on the wafer tray and to which an inspection voltage is input from the outside. An annular seal member that forms a sealed space together with the wafer tray and the wiring board, an elastic sheet having a peripheral edge held on the peripheral edge of the wiring board, and a portion corresponding to each external pad in the elastic sheet, A plurality of probe terminals that are electrically connected to the wiring layer, and provided on the elastic sheet at portions corresponding to the respective external pads. A plurality of dummy probe terminals arranged to form a pair, and voltage applying means is connected between the probe terminals and the dummy probe terminals in pairs, and the plurality of probe terminals and the plurality of dummy probe terminals Each of the tips has a smooth shape.

  According to the first semiconductor integrated circuit inspection apparatus, between the probe terminal and the dummy probe terminal provided on the elastic sheet of the wiring board, a voltage applying means is connected for each pair of the terminals, and Since the tip portions of the plurality of probe terminals and dummy probe terminals have a smooth shape, a voltage higher than the inspection voltage is applied to the terminal pair consisting of the probe terminals and the dummy probe terminals by the voltage applying means before executing the inspection. Is applied, it is possible to easily destroy the surface oxide film formed on the surface of the external pad that is in contact with the probe terminal whose tip is smoothed. As a result, the contact resistance between the probe terminal provided on the inspection substrate and the external pad provided on the semiconductor wafer can be sufficiently reduced. Inspection without any problem can be realized.

  In the first semiconductor integrated circuit inspection apparatus, a semiconductor wafer is formed with wiring and a plurality of dummy pads electrically connected to each external pad by the wiring, and each dummy probe terminal is elastic. It is preferable that the sheet is provided in a portion corresponding to each dummy pad in the sheet.

  In the first semiconductor integrated circuit inspection apparatus, the probe terminal and the dummy probe terminal are preferably cylindrical.

  A second semiconductor integrated circuit inspection apparatus according to the present invention holds a semiconductor wafer formed with a plurality of semiconductor integrated circuit elements and a plurality of external pads electrically connected to the plurality of semiconductor integrated circuit elements on an upper surface. A wafer tray, a wiring substrate provided to face the main surface of the semiconductor wafer held on the wafer tray, and provided between the wafer tray and the wiring substrate, and a wiring substrate having a wiring layer to which an inspection voltage is input from the outside. An annular sealing member that forms a sealed space together with the wafer tray and the wiring substrate, and a plurality of anisotropic conductive rubbers that are provided on the wiring substrate and are provided at portions corresponding to the respective external pads and are electrically connected to the wiring layer And an anisotropic part disposed on the wiring board and corresponding to each of the plurality of external pads, and arranged in pairs with each of the plurality of electrode parts. A plurality of dummy electrode portions made of conductive rubber, and a voltage applying means is connected between the electrode portion and the dummy electrode portion for each pair, and each tip of the plurality of electrode portions and the plurality of dummy electrode portions. The part is characterized by contacting each external pad in a smooth shape by pressing.

  According to the second semiconductor integrated circuit inspection apparatus, a voltage applying means is connected to each pair of electrode portions between the electrode portion serving as a probe terminal provided on the wiring board and the dummy electrode portion, In addition, since the tip portions of the plurality of electrode portions and the dummy electrode portions come into contact with each external pad in a smooth shape by pressing, the electrode pair composed of the electrode portions and the dummy electrode portions is inspected by the voltage applying means before the inspection is executed. When a voltage higher than the voltage is applied, the tip of the electrode portion comes into contact with a smooth shape, so that the surface oxide film formed on the surface of the external pad can be easily destroyed. As a result, the contact resistance between the electrode portion provided on the inspection substrate and the external pad provided on the semiconductor wafer can be sufficiently reduced. Inspection without any problem can be realized.

  In the second semiconductor integrated circuit inspection apparatus, the semiconductor wafer is formed with wirings and a plurality of dummy pads electrically connected to the external pads by the wirings. It is preferable to be provided at a portion held by the substrate and corresponding to each dummy pad.

  In the second semiconductor integrated circuit inspection apparatus, the tip portions of the plurality of electrode portions and the plurality of dummy electrode portions are preferably in contact with the entire surface of each external pad by pressing.

  According to a first semiconductor integrated circuit inspection method of the present invention, a semiconductor wafer on which a plurality of semiconductor integrated circuit elements and a plurality of external pads electrically connected to the plurality of semiconductor integrated circuit elements are formed is held on an upper surface. A wafer tray, a wiring substrate provided to face the main surface of the semiconductor wafer held on the wafer tray, and provided between the wafer tray and the wiring substrate, and a wiring substrate having a wiring layer to which an inspection voltage is input from the outside. An annular seal member that forms a sealed space together with the wafer tray and the wiring substrate, an elastic sheet whose peripheral portion is held by the peripheral portion of the wiring substrate, and a portion corresponding to each external pad in the elastic sheet are provided, A plurality of probe terminals connected to each other and portions corresponding to each external pad in the elastic sheet, and each pair with each probe terminal. A plurality of dummy probe terminals arranged in this manner, and a voltage applying means is connected to each pair between the probe terminals and the dummy probe terminals, and each tip of the plurality of probe terminals and the plurality of dummy probe terminals. A semiconductor integrated circuit inspection method for collectively inspecting electrical characteristics of a plurality of semiconductor integrated circuit elements using a semiconductor integrated circuit inspection apparatus having a smooth portion, and includes a wafer tray, a seal member, and an inspection substrate. A step (a) of forming a sealed space inside the wafer tray, the seal member, and the inspection substrate; a plurality of probe terminals and external pads, and a plurality of dummy probe terminals and an external portion, each of which is depressurized and faces each other The probe terminal and the dummy probe end that are paired by the step (b) of contacting the pad and the voltage applying means, respectively. A step (c) of electrically connecting the probe terminal and the external pad which are in contact with each other by applying a voltage higher than the voltage for inspection between and (c), and after the step (c), A step (d) of collectively inspecting electrical characteristics of a plurality of semiconductor integrated circuit elements formed on the semiconductor wafer via probe terminals and external pads, which are opposed to each other. And

  In the first method for inspecting a semiconductor integrated circuit, the semiconductor wafer is formed with wiring and a plurality of dummy pads electrically connected to each external pad by the wiring. The dummy probe terminals are preferably brought into contact with the dummy pads facing each other.

  According to the second semiconductor integrated circuit inspection method of the present invention, a semiconductor wafer on which a plurality of semiconductor integrated circuit elements and a plurality of external pads electrically connected to the plurality of semiconductor integrated circuit elements are formed is held on the upper surface. A wafer tray, a wiring substrate provided to face the main surface of the semiconductor wafer held on the wafer tray, and provided between the wafer tray and the wiring substrate, and a wiring substrate having a wiring layer to which an inspection voltage is input from the outside. An annular sealing member that forms a sealed space together with the wafer tray and the wiring substrate, and a plurality of anisotropic conductive rubbers that are provided on the wiring substrate and are provided at portions corresponding to the respective external pads and are electrically connected to the wiring layer An anisotropic conductive material disposed on the wiring board and corresponding to each external pad, and arranged in pairs with each of the plurality of electrode parts. A plurality of dummy electrode portions made of rubber, and voltage application means are connected to each other between the electrode portions and the dummy electrode portions, and each tip portion of the plurality of electrode portions and the plurality of dummy electrode portions. Is intended for a semiconductor integrated circuit inspection method for collectively inspecting the electrical characteristics of a plurality of semiconductor integrated circuit elements using a semiconductor integrated circuit inspection apparatus that contacts each external pad in a smooth shape by pressing, a wafer tray, a seal A step (a) of forming a sealed space on the inside of the wafer tray, the seal member and the test substrate by the member and the test substrate; The step (b) of bringing the dummy electrode portion and the external pad into contact with each other and the voltage applying means between the electrode portion and the dummy electrode portion that make a pair are higher than the inspection voltage. A step (c) of electrically connecting between the electrode part and the external pad that are in contact with each other by applying a voltage; and after each step (c), And a step (d) of collectively inspecting electrical characteristics of a plurality of semiconductor integrated circuit elements formed on the semiconductor wafer via an external pad.

  In the second method for inspecting a semiconductor integrated circuit, the semiconductor wafer is formed with wiring and a plurality of dummy pads electrically connected to each external pad by the wiring. The dummy electrode portions are preferably brought into contact with the respective dummy pads facing each other.

  According to the semiconductor integrated circuit inspection apparatus and the semiconductor integrated circuit inspection method of the present invention, a plurality of external pads in which a probe terminal or an electrode for inspection is formed on a semiconductor wafer and electrically connected to a semiconductor integrated circuit element Since the contact resistance between the test substrate and the external pad is reliably connected, a plurality of semiconductor integrated circuits can be inspected without leakage at the wafer level.

(First embodiment)
A semiconductor integrated circuit device inspection apparatus according to a first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 shows a cross-sectional structure of the semiconductor integrated circuit inspection apparatus according to the first embodiment.

  As shown in FIG. 1, a plurality of semiconductor integrated circuit elements (not shown) are formed on a semiconductor wafer 1 to be inspected, and a plurality of external pads 2A and a plurality of dummy are formed on the surface of the semiconductor wafer 1. A pad 2B is provided. Here, the pair of external pads 2 </ b> A and the dummy pads 2 </ b> B are electrically connected through the wiring 3 formed on the semiconductor wafer 1.

  The semiconductor wafer 1 is placed on the upper surface of the wafer tray 11, and the inspection substrate 4 is disposed so as to face the surface of the semiconductor wafer 1.

  The inspection substrate 4 includes a wiring substrate 5 having a wiring layer 5a, an elastic sheet 6 made of, for example, polyimide resin, which is held by a peripheral edge of the wiring substrate 5 and a rigid ring (not shown), and the elastic sheet 6 Cylindrical bumps 7 and dummy bumps 8 provided at portions corresponding to the respective external pads 2A and dummy pads 2B of the semiconductor wafer 1 and having smooth ends, and opposite to the bumps 7 and the dummy bumps 8 on the elastic sheet 6. Further, an isolated pattern 9 made of, for example, copper provided integrally with the bump 7 and the dummy bump 8, and provided between the wiring substrate 5 and the elastic sheet 6, and one end portion of the wiring layer 5 a of the wiring substrate 5 and the isolated pattern 9 and an anisotropic conductive rubber sheet 10 that is electrically connected to 9. Here, the conductive particles 10a arranged in a linear shape are sealed inside the anisotropic conductive rubber sheet 10, and the sealed conductive particles 10a are compressed in the linear direction. The one end of the wiring layer 5a and the isolated pattern 9 are electrically connected.

  The other end of the wiring layer 5a of the wiring board 5 is connected to a burn-in inspection device (not shown) that supplies a test voltage such as a power supply voltage, a ground voltage, or a signal voltage.

  An annular seal member 12 made of an elastic body having a lip cross section is provided around the wafer holding portion 11 a that holds the semiconductor wafer 1 in the wafer tray 11.

  Hereinafter, a method for collectively inspecting electrical characteristics of a plurality of semiconductor integrated circuit elements formed on the semiconductor wafer 1 using the semiconductor integrated circuit inspection apparatus configured as described above will be described.

  First, the wafer tray 11 and the inspection substrate 4 are brought close to each other with each external pad 2A and each dummy pad 2B on the semiconductor wafer 1 facing each bump 7 and each dummy bump 8 of the inspection substrate 4 respectively. Thus, a sealed space 13 is formed by the wafer tray 11, the annular seal member 12, and the inspection substrate 4.

  Next, when the sealed space 13 is depressurized by a vacuum pump or the like, the cross-sectional shape of the annular seal member 12 is elastically deformed into an arcuate shape, so that the inspection substrate 4 and the wafer tray 11 further approach, and the bump 7 and the inspection are inspected. External pad 2A, and dummy bump 8 and dummy pad 2B are pressed and contacted, respectively.

  FIG. 2 shows an outline of a circuit configuration at the time of inspection using the inspection substrate 4 and the semiconductor wafer 1 shown in FIG. As shown in FIG. 2, the bumps 7 and the dummy bumps 8 provided on the wiring board 5 are connected to an external power supply 14 and a tester (inspection apparatus) 15 via a connection switching unit 18. The dummy bump 8 is grounded through a resistor.

  By the way, if the surface oxide film is thickly formed on the surface of each external pad 2A, each external pad 2A is not brought into conduction only by contacting the bump 7. Therefore, with the bump 7 and the dummy bump 8 in contact with the external pad 2A and the dummy pad 2B, respectively, first, a voltage higher than the inspection voltage between the bump 7 and the dummy bump 8 from the external power source 14 via the external pad 2A. Specifically, a voltage (for example, 7V) about twice the normal inspection voltage is applied. Here, as shown in FIG. 3, the bump 7 has a cylindrical shape and a smooth end surface, so that the contact area with the external pad 2 </ b> A is as large as several thousand square microns. Therefore, the dielectric breakdown easily occurs in the surface oxide film formed on the surface of the external pad 2A due to the voltage applied from the external power supply 14. Further, since the dummy bump 8 has the same shape as the bump 7, the dielectric breakdown is easily caused by the voltage from the external power supply 14 in the dummy pad 2 </ b> B that the dummy bump 8 contacts. As a result, the bump 7 and the dummy bump 8 can be electrically connected to the external pad 2A and the dummy pad 2B that are in contact with each other.

  Next, the wiring switching unit 18 switches the connection from the external power supply 14 to the tester 15. At the same time, the dummy bump 8 and the external wiring 16 are electrically separated. In this state, the tester 15 applies a test voltage to each element of the semiconductor wafer 1 to perform a predetermined test.

  With this configuration, a voltage can be applied between the probe terminal (bump 7) and the dummy probe terminal (dummy bump 8) via the external pad 2A and the dummy pad 2B, respectively, so that the surface oxide film of the external pad 2A can be easily broken. Moreover, since the tip end surface of the bump 7 which is a probe terminal is smooth, the contact area between the bump 7 and the external pad 2A can be increased. For this reason, the surface oxide film of the external pad 2A can be reliably broken even at a relatively low voltage (for example, about 5 V). As a result, good electrical continuity between the bump 7 as the probe terminal and the external pad 2A can be obtained.

  In other words, in the first embodiment, the external power supply 14 secures the continuity between the bump 7 and the external pad 2A in advance, so that there is no leakage with respect to the semiconductor elements on the entire surface of the semiconductor wafer 1 at the wafer level. An inspection can be performed.

  Here, the case where the bump 7 and the dummy bump 8 are in contact with the external pad 2A and the dummy pad 2B and electrically connected via the wiring 3 formed on the semiconductor wafer 1 has been described. Not limited. For example, the bump 7 and the dummy bump 8 may be connected to one external pad 2A. In this way, the semiconductor wafer 1 to be inspected is provided with the inspection dummy pad 2B and the wiring 3 for electrically connecting the dummy pad 2B and the external pad 2A in addition to the normal external pad 2A. There is no need to provide it.

(Second Embodiment)
Hereinafter, a semiconductor integrated circuit device inspection apparatus according to a second embodiment of the present invention will be described with reference to FIGS.

  FIG. 4 shows a cross-sectional structure of a semiconductor integrated circuit inspection apparatus according to the second embodiment.

  As shown in FIG. 4, a plurality of semiconductor integrated circuit elements (not shown) are formed on a semiconductor wafer 1 to be inspected, and a plurality of external pads 2A and a plurality of dummy are formed on the surface of the semiconductor wafer 1. A pad 2B is provided. Here, the pair of external pads 2 </ b> A and the dummy pads 2 </ b> B are electrically connected through the wiring 3 formed on the semiconductor wafer 1.

  The semiconductor wafer 1 is placed on the upper surface of the wafer tray 11, and the inspection substrate 4 is disposed so as to face the surface of the semiconductor wafer 1.

  The inspection substrate 4 is composed of a wiring substrate 5 having a wiring layer 5 a and an anisotropic conductive rubber sheet 10 fixed to the wiring substrate 5. Here, in the anisotropic conductive rubber sheet 10, the conductive particles arranged in a straight line are formed on the electrode portion 19 and the dummy electrode portion 20, each of which corresponds to the external pad 2 </ b> A and the dummy pad 2 </ b> B of the semiconductor wafer 1. 10a is provided.

  The other end of the wiring layer 5a of the wiring board 5 is connected to a burn-in inspection device (not shown) that supplies a test voltage such as a power supply voltage, a ground voltage, or a signal voltage.

  An annular seal member 12 made of an elastic body having a lip-shaped cross section is provided around the wafer holding portion 11 a in the wafer tray 11.

  Hereinafter, a method for collectively inspecting electrical characteristics of a plurality of semiconductor integrated circuit elements formed on the semiconductor wafer 1 using the semiconductor integrated circuit inspection apparatus configured as described above will be described.

  First, in the state where each external pad 2A and each dummy pad 2B on the semiconductor wafer 1 and each electrode part 19 and each dummy electrode part 20 in the anisotropic conductive rubber sheet 10 of the inspection substrate 4 face each other, the wafer tray 11 and the inspection substrate 4 are brought close to each other, and a sealed space 13 is formed by the wafer tray 11, the annular seal member 12, and the inspection substrate 4.

  Next, when the sealed space 13 is depressurized, the cross-sectional shape of the annular seal member 12 is elastically deformed into an arcuate shape, so that the inspection substrate 4 and the wafer tray 11 are further brought closer to each other, and the electrode in the anisotropic conductive rubber sheet 10 The part 19 and the external pad 2 for inspection, and the dummy electrode part 20 and the dummy pad 2B are in contact with each other.

  FIG. 5 shows an outline of a circuit configuration at the time of inspection using the inspection substrate 4 and the semiconductor wafer 1 shown in FIG. As shown in FIG. 5, the electrode part 19 and the dummy electrode part 20 provided on the wiring board 5 are connected to the external power source 14 and the tester 15 via the connection switching part 18. The dummy electrode portion 20 is grounded via a resistor.

  By the way, if the surface oxide film is formed thick on the surface of each external pad 2A, each external pad 2A does not conduct only by contacting the electrode portion 19 of the anisotropic conductive rubber sheet 10. Therefore, in a state where the electrode portion 19 and the dummy electrode portion 20 are in contact with the external pad 2A and the dummy pad 2B, respectively, first, an inspection is performed between the electrode portion 19 and the dummy electrode portion 20 via the external pad 2A by the external power source 14. A voltage higher than the voltage, for example, about twice the normal inspection voltage is applied. Here, as shown in FIG. 6, the electrode portion 19 is larger in width than the external pad 2A and contacts the entire exposed surface of the external pad 2A due to a load. Dielectric breakdown easily occurs in the surface oxide film formed on the surface of the pad 2A. In addition, since the dummy electrode portion 20 has the same shape and dimensions as the electrode portion 19, the dielectric breakdown can be easily caused by the voltage from the external power supply 14 in the dummy pad 2 </ b> B in contact with the dummy electrode portion 20. Occur. As a result, the electrode portion 19 and the dummy electrode portion 20 can be electrically connected to the external pad 2A and the dummy pad 2B that are in contact with each other. Further, since the electrode portion 19 is larger in width than the external pad 2A, even if the electrode 19 and the dummy electrode 20 which are probe terminals are slightly misaligned with respect to the external pad 2A and the dummy pad 2B, respectively, the contact area thereof Will not change.

  Next, the connection switching unit 18 switches the connection from the external power supply 14 to the tester 15. At the same time, the dummy electrode portion 20 and the external wiring 16 are electrically separated. In this state, the tester 15 applies a test voltage to each element of the semiconductor wafer 1 to perform a predetermined test.

  With this configuration, since a voltage can be applied between the probe terminal (electrode 19) and the dummy probe terminal (dummy electrode 20) via the external pad 2A, the surface oxide film of the external pad 2A can be easily broken. Since the electrode 19 as a terminal is made of a part of the anisotropic conductive rubber sheet 10, the contact area between the electrode 19 and the external pad 2A can be further increased. For this reason, the surface oxide film of the external pad 2A can be broken more reliably even at a relatively low voltage. Moreover, since metal bumps are not used, costs can be reduced.

  As described above, in the second embodiment, in order to ensure the electrical connection between the electrode portion 19 formed in advance on the anisotropic conductive rubber sheet 10 and the external pad 2A by the external power source 14, the semiconductor wafer is obtained at the wafer level. It is possible to realize a leak-free inspection for the semiconductor elements on the entire surface of 1.

  Here, the electrode portion 19 and the dummy electrode portion 20 formed on the anisotropic conductive rubber sheet 10 are in contact with the external pad 2A and the dummy pad 2B, respectively, and via the wiring 3 formed on the semiconductor wafer 1. However, the present invention is not limited to this. For example, the electrode part 19 and the dummy electrode part 20 may be configured to be connected to one external pad 2A. In this way, the semiconductor wafer 1 to be inspected is provided with the inspection dummy pad 2B and the wiring 3 for electrically connecting the dummy pad 2B and the external pad 2A in addition to the normal external pad 2A. There is no need to provide it.

  According to the semiconductor integrated circuit inspection apparatus and the semiconductor integrated circuit inspection method of the present invention, an inspection electrode terminal (probe terminal) is provided on a plurality of pads provided on a plurality of semiconductor integrated circuit elements formed on a semiconductor wafer. In this way, it is possible to perform inspection without leakage on the entire semiconductor element at the wafer level. In particular, the electrical characteristics of a plurality of semiconductor integrated circuit elements formed on the semiconductor wafer are collectively inspected at the wafer level. This is useful in a semiconductor integrated circuit inspection apparatus, a semiconductor integrated circuit inspection method, and the like.

1 is a partial cross-sectional view illustrating a semiconductor integrated circuit inspection apparatus according to a first embodiment of the present invention. 1 is a schematic circuit diagram showing an inspection apparatus for a semiconductor integrated circuit according to a first embodiment of the present invention. It is a fragmentary sectional view showing a probe terminal used for an inspection device of a semiconductor integrated circuit concerning a 1st embodiment of the present invention. It is a fragmentary sectional view which shows the test | inspection apparatus of the semiconductor integrated circuit which concerns on the 2nd Embodiment of this invention. It is a schematic circuit diagram which shows the test | inspection apparatus of the semiconductor integrated circuit which concerns on the 2nd Embodiment of this invention. It is a fragmentary sectional view showing a probe terminal used for an inspection device of a semiconductor integrated circuit concerning a 2nd embodiment of the present invention. It is a fragmentary sectional view which shows the inspection apparatus of the semiconductor integrated circuit which concerns on a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2A External pad 2B Dummy pad 3 Wiring 4 Inspection board 5 Wiring board 5a Wiring layer 6 Elastic sheet 7 Bump 8 Dummy bump 9 Isolated pattern 10 Anisotropic conductive rubber sheet 10a Conductive particle 11 Wafer tray 12 Seal ring 13 Sealing space 14 External Power supply 15 Tester 18 Connection switching part 19 Electrode part 20 Dummy electrode part

Claims (10)

A wafer tray for holding a semiconductor wafer formed on a top surface with a plurality of semiconductor integrated circuit elements and a plurality of external pads electrically connected to the plurality of semiconductor integrated circuit elements;
A wiring board having a wiring layer provided so as to face the main surface of the semiconductor wafer held on the wafer tray and to which an inspection voltage is input from the outside;
An annular seal member provided between the wafer tray and the wiring board, and forming a sealed space together with the wafer tray and the wiring board;
An elastic sheet having a peripheral edge held by the peripheral edge of the wiring board;
A plurality of probe terminals which are provided at portions corresponding to the respective external pads in the elastic sheet, and are electrically connected to the wiring layer;
A plurality of dummy probe terminals provided in portions corresponding to the respective external pads in the elastic sheet, and arranged so as to make a pair with the respective probe terminals;
Between the probe terminal and the dummy probe terminal, voltage application means is connected for each pair,
An inspection apparatus for a semiconductor integrated circuit, wherein the tip portions of the plurality of probe terminals and the plurality of dummy probe terminals have a smooth shape. The semiconductor wafer is formed with wiring and a plurality of dummy pads electrically connected to the external pads by the wiring,
2. The inspection apparatus for a semiconductor integrated circuit according to claim 1, wherein each of the dummy probe terminals is provided at a portion of the elastic sheet corresponding to each of the dummy pads.   3. The semiconductor integrated circuit inspection apparatus according to claim 1, wherein the probe terminal and the dummy probe terminal have a cylindrical shape. A wafer tray for holding a semiconductor wafer formed on a top surface with a plurality of semiconductor integrated circuit elements and a plurality of external pads electrically connected to the plurality of semiconductor integrated circuit elements;
A wiring board having a wiring layer provided so as to face the main surface of the semiconductor wafer held on the wafer tray and to which an inspection voltage is input from the outside;
An annular seal member provided between the wafer tray and the wiring board, and forming a sealed space together with the wafer tray and the wiring board;
An electrode portion made of a plurality of anisotropic conductive rubbers held on the wiring board and provided at a site corresponding to each external pad, and electrically connected to the wiring layer;
A plurality of dummy electrode portions made of anisotropic conductive rubber, which are provided on a portion corresponding to each of the plurality of external pads, held on the wiring board, and arranged in pairs with the plurality of electrode portions; Prepared,
Between the electrode part and the dummy electrode part, a voltage application means is connected for each pair,
An inspection device for a semiconductor integrated circuit, wherein the tip portions of the plurality of electrode portions and the plurality of dummy electrode portions are in contact with each external pad in a smooth shape by pressing. The semiconductor wafer is formed with wiring and a plurality of dummy pads electrically connected to the external pads by the wiring,
5. The semiconductor integrated circuit inspection apparatus according to claim 4, wherein each of the dummy electrode portions is provided on a portion that is held by the wiring board and corresponds to each of the dummy pads.   6. The semiconductor integrated circuit inspection device according to claim 4, wherein tips of the plurality of electrode portions and the plurality of dummy electrode portions are brought into contact with the entire surface of each external pad by pressing. A wafer tray for holding a semiconductor wafer on which a plurality of semiconductor integrated circuit elements and a plurality of external pads electrically connected to the plurality of semiconductor integrated circuit elements are formed on the upper surface, and a main of the semiconductor wafer held on the wafer tray A wiring board having a wiring layer provided to face the surface and having an inspection voltage input from the outside, is provided between the wafer tray and the wiring board, and forms a sealed space together with the wafer tray and the wiring board. An annular seal member, an elastic sheet having a peripheral edge held on the peripheral edge of the wiring board, and a plurality of electrically connected to the wiring layer provided at portions corresponding to the external pads in the elastic sheet The probe terminals are provided at portions corresponding to the external pads of the elastic sheet, and are paired with the probe terminals. A plurality of dummy probe terminals arranged in such a manner that a voltage application means is connected between the probe terminals and the dummy probe terminals in pairs, and the plurality of probe terminals and the plurality of dummy probe terminals A semiconductor integrated circuit inspection method for collectively inspecting electrical characteristics of the plurality of semiconductor integrated circuit elements using a semiconductor integrated circuit inspection apparatus having a smooth shape at each tip of the semiconductor integrated circuit,
A step (a) of forming a sealed space inside the wafer tray, the seal member and the inspection substrate by the wafer tray, the seal member and the inspection substrate;
Depressurizing the sealed space and bringing the plurality of probe terminals and the external pads and the plurality of dummy probe terminals and the external pads into contact with each other, respectively (b);
By applying a voltage higher than the inspection voltage between the probe terminal and the dummy probe terminal that make a pair by the voltage application means, the probe terminal and the external pad that are opposed to each other A step (c) of electrically connecting the gaps;
After the step (c), the electrical characteristics of the plurality of semiconductor integrated circuit elements formed on the semiconductor wafer are collectively inspected via the probe terminals and the external pads that face each other. A method for inspecting a semiconductor integrated circuit comprising the step (d). The semiconductor wafer is formed with wiring and a plurality of dummy pads electrically connected to the external pads by the wiring,
8. The method of testing a semiconductor integrated circuit according to claim 7, wherein in the step (b), the dummy probe terminals are brought into contact with the dummy pads facing each other. A wafer tray for holding a semiconductor wafer on which a plurality of semiconductor integrated circuit elements and a plurality of external pads electrically connected to the plurality of semiconductor integrated circuit elements are formed on the upper surface, and a main of the semiconductor wafer held on the wafer tray A wiring board having a wiring layer provided to face the surface and having an inspection voltage input from the outside, is provided between the wafer tray and the wiring board, and forms a sealed space together with the wafer tray and the wiring board. An annular seal member; and an electrode portion made of a plurality of anisotropic conductive rubbers provided on a portion held by the wiring board and corresponding to each external pad, and electrically connected to the wiring layer; Anisotropic conductivity provided on a portion corresponding to each external pad held on the wiring board and arranged to pair with each of the plurality of electrode portions A plurality of dummy electrode portions, and a voltage applying means is connected between the electrode portions and the dummy electrode portions, and each of the plurality of electrode portions and the plurality of dummy electrode portions. A semiconductor integrated circuit inspection method for collectively inspecting electrical characteristics of the plurality of semiconductor integrated circuit elements using a semiconductor integrated circuit inspection apparatus in which a front end portion is in contact with each external pad in a smooth shape by pressing. ,
A step (a) of forming a sealed space inside the wafer tray, the seal member and the inspection substrate by the wafer tray, the seal member and the inspection substrate;
Depressurizing the sealed space and bringing the plurality of the electrode portions and the external pads and the plurality of dummy electrode portions and the external pads into contact with each other, the step (b);
By applying a voltage higher than the voltage for inspection between the electrode part and the dummy electrode part that make a pair by the voltage applying means, the electrode part and the external pad facing each other A step (c) of electrically connecting the gaps;
After the step (c), the electrical characteristics of the plurality of semiconductor integrated circuit elements formed on the semiconductor wafer are collectively inspected through the electrode portions and the external pads that are opposed to each other. A method for inspecting a semiconductor integrated circuit comprising the step (d). The semiconductor wafer is formed with wiring and a plurality of dummy pads electrically connected to the external pads by the wiring,
10. The method of testing a semiconductor integrated circuit according to claim 9, wherein in the step (b), each of the dummy electrode portions is brought into contact with each of the dummy pads facing each other.

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