JP2006267814A - Display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a voltage drop and a signal delay by reducing a wiring resistance without affecting a transistor structure in a display panel. <P>SOLUTION: The display panel is equipped with a transistor array substrate 50 in which transistors 21 to 23 and a capacitor 24 are provided for a sub-pixel P of a single dot. In the transistor array substrate 50, a scanning line X and a supply line Z of a horizontal direction and a signal line Y of a vertical direction are laid. On a surface of the transistor array substrate 50, a common wiring line 62 and a power supply line 61 are protrusively provided. A sub-pixel electrode 20a is arranged between the common wiring line 62 and the power supply line 61 and an organic electroluminescence (EL) layer 20b is stacked on the sub-pixel electrode 20a. The organic EL layer 20b and the common wiring line 62 are covered by a counter electrode 20c. A sealing substrate 80 with conductivity provided on the common wiring line 62 is made conductive to the common wiring line 62 and the counter electrode 20c. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a display panel using a light emitting element.

  Organic electroluminescence display panels, which are light-emitting elements, can be broadly classified into passive drive type and active matrix drive type. Active matrix drive type organic electroluminescence display panels have high contrast and high contrast. It is superior to the passive drive method in terms of fineness.

  For example, in the conventional active matrix driving type organic electroluminescence display panel described in Patent Document 1, an organic electroluminescence element (hereinafter referred to as organic EL element) and a voltage signal corresponding to image data are applied to the gate. In addition, a driving transistor that supplies current to the organic EL element and a switching transistor that performs switching for supplying a voltage signal corresponding to image data to the gate of the driving transistor are provided for each pixel.

  In this organic electroluminescence display panel, when a scanning line is selected, the switching transistor is turned on, and at that time, a voltage representing a luminance is applied to the gate of the driving transistor via the signal line. As a result, the drive transistor is turned on, and a drive current having a magnitude corresponding to the level of the gate voltage flows from the power source to the organic EL element via the source-drain of the drive transistor, and the organic EL element corresponds to the current magnitude. Emits light with high brightness.

  At that time, the voltage applied to the gate of the drive transistor is stored in the storage capacitor, which is a capacitor provided in the circuit, and after the selection of the scanning line is completed until the next scanning line is selected. Then, since the storage capacitor applies a voltage to the gate of the driving transistor even when the switching transistor is turned off, the level of the gate voltage continues to be maintained, and the organic EL element follows the magnitude of the driving current according to the voltage. Continue to emit light at brightness.

  In order to drive such an organic electroluminescence display panel, a drive circuit is provided around the organic electroluminescence display panel, and a voltage is applied to a scanning line, a signal line, a power supply line, etc. laid on the organic electroluminescence display panel. Things have been done.

  In addition, in a conventional active matrix driving type organic electroluminescence display panel, wiring for passing a current through an organic EL element such as a power supply line is formed simultaneously with a thin film transistor patterning process using a thin film transistor material such as a switching transistor and a driving transistor. Patterned.

That is, in manufacturing an organic electroluminescence display panel, a thin film transistor electrode is shaped from the conductive thin film by performing a photolithography method and an etching method on the conductive thin film that is the source of the thin film transistor electrode. At the same time, the wiring connected to the electrode is processed. Therefore, when the wiring is formed from a conductive thin film, the wiring has the same thickness as the electrode of the thin film transistor.
JP-A-8-330600

  However, since the electrode of the thin film transistor is designed on the assumption that it is formed of a thin film and functions as a transistor as the name suggests, in other words, it is not designed on the assumption that a current flows through the light emitting element. When an electric current is caused to flow through the light emitting element, the electric resistance of the wiring is not sufficiently low, so that a voltage drop occurs or a delay of the current flow through the wiring occurs.

  In order to suppress the voltage drop and the current delay, it is desirable to reduce the resistance of the wiring. For this purpose, for example, a metal layer serving as at least one of a source electrode, a drain electrode, and a gate electrode is not changed in thickness. If the pattern is made wide enough to allow sufficient current to flow and low resistance wiring is used, the area where the wiring overlaps with other wiring, conductors, etc. in plan view increases, and parasitic capacitance occurs between them. End up. As a result, the current flow is slowed down. In particular, in the case of a so-called bottom emission structure in which EL light is emitted from the transistor array substrate side, the light emission from the EL element is blocked by the wiring, so that the aperture, which is a ratio of the light emitting area. The rate declined.

  Further, when the gate electrode, the source, and the drain electrode of the thin film transistor are made thicker in order to reduce the resistance, the etching accuracy of the gate electrode, the source, and the drain electrode is lowered, so that the transistor characteristics may be adversely affected.

  In this way, in order to reduce the resistance of the wiring while avoiding the decrease in the aperture ratio in the bottom emission structure, normally, relatively strict design conditions are imposed on the thickening of the wiring, and precise manufacturing accuracy is reduced. Desired. However, this makes it difficult to manufacture the display panel, and there is a problem that productivity is lowered.

  Accordingly, an object of the present invention is to reduce the voltage drop and the signal delay by reducing the resistance of the wiring in the display panel without affecting the transistor structure.

In order to solve the above problems, the display panel of the present invention is
A substrate,
A plurality of transistors provided on the substrate;
A plurality of wirings formed by a conductive layer different from the gate, source and drain of the plurality of transistors;
A plurality of pixel electrodes arranged on the substrate along the wirings between the wirings;
A light emitting layer formed on each of the pixel electrodes;
A counter electrode coated with the light emitting layer;
A sealing substrate electrically connected to the counter electrode;
Is provided.
It is preferable that the plurality of wirings protrude on a surface of the substrate facing the sealing substrate.
The counter electrode is preferably coated continuously from the light emitting layer to the plurality of wirings.
It is preferable that the counter electrode is electrically connected to the sealing substrate on the plurality of wirings.

  The sealing substrate is preferably formed with a conductive layer or a conductive material.

  Furthermore, it is preferable that the plurality of wirings include a common wiring connected to the counter electrode, and the common wiring is electrically connected to the sealing substrate.

  Further, the transistor includes a drive transistor in which one of a source and a drain is connected to a pixel electrode, a switch transistor that causes a write current to flow between the source and drain of the drive transistor, and a source-gate of the drive transistor during a light emission period. And a holding transistor for holding a voltage between them.

  Further, the plurality of wirings may have a power supply wiring connected to the other of the drain and the source of the driving transistor.

Further, the plurality of wirings may include a selection wiring for selecting the switch transistor.
Further, it is preferable that the plurality of wirings have a common wiring connected to the counter electrode.

  According to the present invention, since the wiring is formed by a conductive layer different from the gate, source / drain of the transistor, the wiring can be made thicker than the gate, source / drain of the transistor, and the resistance of the wiring is reduced. be able to. Therefore, even when a current is passed through the transistor / pixel electrode through the wiring, the voltage drop can be suppressed and the current delay can be suppressed without affecting the transistor structure.

  The best mode for carrying out the present invention will be described below with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples. Further, in the following description, the term electroluminescence is abbreviated as EL.

  The display panel 1 of the present invention is a bottom emission display panel, and emits light downward in FIG. In addition, in the present specification, “plan view” refers to a case where the display panel 1 is viewed from above in FIG.

[First Embodiment]
[Planar layout of display panel]
FIG. 1 is a schematic plan view showing a wiring structure of a display panel in the first embodiment. In FIG. 1, the state which removed the sealing substrate 80 mentioned later is shown. In this display panel 1, a pixel 3 of one pixel is arranged in a vertical direction with one dot of red subpixel Pr that emits red light, one dot of green subpixel Pg that emits green light, and 1 that emits blue light. Dot blue sub-pixel Pb. Such pixels 3 are arranged in a matrix on the insulating substrate 2.

  Specifically, when focusing on the horizontal arrangement, a plurality of red subpixels Pr are arranged in one line along the horizontal direction (row direction), and a plurality of green subpixels Pg are arranged in one line along the horizontal direction. Blue subpixels Pb are arranged in a line along the horizontal direction. Focusing on the arrangement in the vertical direction (column direction), a red subpixel Pr, a green subpixel Pg, a red subpixel Pr, a green subpixel Pg, and a blue subpixel Pb, which are repeatedly arranged in this order, are continuously arranged in the vertical direction. The combination of the blue subpixels Pb is the pixel 3. In the following description, the sub-pixel P represents an arbitrary sub-pixel among the red sub-pixel Pr, the green sub-pixel Pg, and the blue sub-pixel Pb, and the description of the sub-pixel P is a red sub-pixel Pr and a green sub-pixel. This applies to both the pixel Pg and the blue subpixel Pb.

  In addition, one signal line Yr, Yg, Yb extends along the vertical direction at one end side in the horizontal direction of each sub-pixel P. Hereinafter, a combination of the three signal lines Yr, Yg, and Yb is referred to as a signal line group 4. A group of signal lines 4 is provided for each column of pixels 3 in the vertical direction. That is, one column of subpixels Pr, Pg, and Pb arranged in the vertical direction is connected to the signal lines Yr, Yg, and Yb of the group of signal lines 4, respectively. When attention is paid to one signal line group 4, the three signal lines Yr, Yg, Yb are close to each other, but the interval between the signal line groups 4 in adjacent columns is the adjacent signal line in the same signal line group 4. It is wider than the interval of Yr, Yg, Yb.

  Here, the signal line Yr supplies a signal to all the red subpixels Pr of the pixels 3 arranged in the vertical direction, and the signal line Yg applies to all the green subpixels Pg of the pixels 3 arranged in the vertical direction. The signal line Yb supplies a signal to all the blue subpixels Pb of the pixels 3 arranged in the vertical direction.

  A plurality of scanning lines X extend in the horizontal direction, and a plurality of supply lines Z, a plurality of selection wirings 60, a plurality of power supply wirings 61, and a plurality of common lines are shared with respect to the scanning lines X. The wiring 62 is provided in parallel. One scanning line X, one supply line Z, one power supply wiring 61, one selection wiring 60, and one common wiring 62 per group of pixels in a row along the horizontal direction. And are provided. Specifically, the common wiring 62 is disposed between the red subpixel Pr and the green subpixel Pg adjacent in the vertical direction, and the scanning line X and the selection wiring 60 are the green subpixel Pg and the blue subpixel adjacent in the vertical direction. The supply line Z and the power supply wiring 61 are arranged between the blue subpixel Pb and the red subpixel Pr of the adjacent pixel 3. The selection wiring 60 and the power supply wiring 61 have the same film thickness.

  Here, the scanning lines X and the supply lines Z supply signals to all the sub-pixels Pr, Pg, and Pb of the pixels 3 arranged in one row along the horizontal direction. Further, in plan view, the scanning line X is electrically connected by being formed by stacking the selection wiring 60, and the power supply wiring 61 is formed by stacking the supply line Z to be electrically connected. Is electrically connected.

  In FIG. 1, subpixel electrodes 20 a (which will be described later) that function as the pixel electrodes of the pixels 3 are the anodes of the organic EL elements 20 at the positions of the subpixels Pr, Pg, and Pb that are shown in a rectangular shape that is long in the horizontal direction. Are respectively provided). That is, when viewed in plan with the display panel 1 as a whole, a plurality of subpixel electrodes 20a are arranged in a matrix, and one dot of subpixel P is determined by one subpixel electrode 20a.

  Accordingly, a plurality of subpixel electrodes 20 a are arranged in a line along the horizontal direction between the power supply wiring 61 and the adjacent common wiring 62, and a plurality of subpixel electrodes are arranged between the common wiring 62 and the adjacent selection wiring 60. 20a is arranged in one row along the horizontal direction, and a plurality of subpixel electrodes 20a are arranged in one row along the horizontal direction between the selection wiring 60 and the power supply wiring 61 of the adjacent pixel 3.

  Here, if m and n are integers of 2 or more, and m pixels 3 are arranged along the vertical direction and n pixels are arranged along the horizontal direction, the subpixel electrode 20a is subpixel along the vertical direction. The same number (3 × m) as the number of one column is arranged in the horizontal direction by the same number n as the number of one row of subpixels along the horizontal direction. In this case, the signal line group 4 is an n group, and the scanning lines X, the supply lines Z, the selection wirings 60, the power supply wirings 61, and the common wirings 62 are each m.

  Further, the sum of the selection wiring 60, the power supply wiring 61, and the common wiring 62 that also functions as a partition wall that dams an organic compound-containing liquid that becomes an organic EL layer 20 b of the organic EL element 20 to be described later in one row of subpixels is (3 However, (3 × m + 1) lines are required to partition the organic compound-containing liquid in all lines into sub-pixels for each line. Therefore, a (3 × m + 1) -th partition bulkhead dummy wiring 63 (see FIG. 8 described later) having the same height and the same length as the common wiring 62 is aligned with the selection wiring 60, the power supply wiring 61, and the common wiring 62. Parallel in the direction.

Note that the colors of the subpixels Pr, Pg, and Pb are determined by the emission color of the organic EL element 20. Further, in the following description, the pixel P _{i, j} represents the pixel in the _i- th row (1 ≦ i ≦ m) from the top and the j-th column (1 ≦ j ≦ n) from the left, and i and j Is used, it indicates that the pixel is in the i-th row or j-th column.

[Sub-pixel circuit configuration]
Next, the circuit configuration of the subpixels Pr, Pg, and Pb will be described with reference to the equivalent circuit diagram of FIG. All of the subpixels Pr, Pg, and Pb are configured in the same manner. Each of the subpixels Pr, Pg, and Pb has an organic EL element 20, an N-channel amorphous silicon thin film transistor (hereinafter simply referred to as a transistor) 21, and the like. 22 and 23 and a capacitor 24 are provided. Hereinafter, the transistor 21 is referred to as a switch transistor 21, the transistor 22 is referred to as a holding transistor 22, and the transistor 23 is referred to as a drive transistor 23.

In the switch transistor 21, the source 21s is, the red sub-pixel Pr _i, in _j the signal lines Yr _j, green sub-pixel Pg _i, in _j the signal line Yg _j, blue sub-pixel Pb _{i, j} in the signal line Yb _j the conductive respectively, the sub-pixel electrode 20a of the drain 21d organic EL element 20, electrically connected to the upper electrode 24B of the source 23s and the capacitor 24 of the driving transistor 23, a gate 21g is the gate 22g and the scan line X _i of the holding transistor 22 Conducted.

In the holding transistor 22 becomes conductive source 22s is the lower electrode 24A of the gate 23g and the capacitor 24 of the driving transistor 23, the drain 22d is electrically connected to the drain 23d and the supply line _{Z i} of the driving transistor 23, a gate 22g is switching transistor 21 It is electrically connected to the gate 21g and the scanning line X _i. Note that the drain 22d of the holding transistor 22 may be connected to the scanning line X _i instead of the supply line Z _i .

In the drive transistor 23, the source 23s is electrically connected to the subpixel electrode 20a of the organic EL element 20, the drain 21d of the switch transistor 21 and the upper layer electrode 24B of the capacitor 24, and the drain 23d is connected to the drain 22d of the holding transistor 22 and the supply line Z _i. The gate 23g is electrically connected to the source 22s of the holding transistor 22 and the lower layer electrode 24A of the capacitor 24. When the drain 22d of the holding transistor 22 is connected to the scanning line X _i , the drain 23d of the driving transistor 23 is not connected to the drain 22d of the holding transistor 22.

  The counter electrode 20 c serving as the cathode of the organic EL element 20 is electrically connected to the common wiring 62.

The source 21s of the switch transistor 21 of any red sub-pixel Pr _{i, j} of the pixel 3 arranged along the vertical direction is conducted to the common signal line Yr _j , and any of the pixels 3 arranged along the vertical direction. The source 21s of the switch transistor 21 of the green sub-pixel Pg _{i, j} is also conducted to the common signal line Yg _j and the switch transistor 21 of any blue sub-pixel Pb _{i, j} of the pixel 3 arranged along the vertical direction. also the source 21s is electrically connected to the common signal line Yb _j.

On the other hand, the gate 21g of the switch transistor 21 of any of the sub-pixels Pr _{i, j} , Pg _{i, j} , Pb _{i, j} of the pixel 3 arranged along the horizontal direction is also conducted to the common scanning line X _i , The gate 22g of the holding transistor 22 of any of the sub-pixels Pr _{i, j} , Pg _{i, j} , Pb _{i, j} of the pixel 3 arranged along the direction is also conducted to the common scanning line X _i along the horizontal direction. The drains 22d of the holding transistors 22 of any of the sub-pixels Pr _{i, j} , Pg _{i, j} , Pb _{i, j} of the pixels 3 arranged in this manner are electrically connected to the common supply line Z _i or the scanning line X _i , in the horizontal direction The drains 23d of the drive transistors 23 of any of the sub-pixels Pr _{i, j} , Pg _{i, j} , Pb _{i, j} of the pixels 3 arranged along are connected to the common supply line Z _i .

[Plane layout of pixels]
The planar layout of the pixel 3 will be described with reference to FIGS. 3 is a plan view mainly showing electrodes of the red subpixel Pr, FIG. 4 is a plan view mainly showing electrodes of the green subpixel Pg, and FIG. 5 is an electrode of the blue subpixel Pb. It is the top view which mainly showed. 3 to 5, illustration of the subpixel electrode 20a and the counter electrode 20c of the organic EL element 20 is omitted for easy viewing of the drawings. 3 to 5 show a state where a sealing substrate 80 described later is removed.

  As shown in FIG. 3, the red sub-pixel Pr is vertically partitioned in the vertical direction by a power supply wiring 61 and a common wiring 62. In the red sub-pixel Pr, the driving transistor 23 is viewed in plan view. Are arranged along the supply line Z and the power supply wiring 61, the switch transistor 21 is arranged along the common wiring 62, and the holding transistor 22 is arranged at the corner of the red subpixel Pr adjacent to the supply line Z. Yes. The drain 22d of the holding transistor 22 and the drain 23d of the driving transistor 23 are integrally formed with the supply line Z.

  As shown in FIG. 4, the green subpixel Pg is partitioned in the vertical direction by a common wiring 62 and a selection wiring 60, and in the green subpixel Pg, the driving transistor 23 is viewed in plan view. Are arranged along the common wiring 62, the switch transistor 21 is arranged along the scanning line X and the selection wiring 60, and the holding transistor 22 is arranged at the corner of the green subpixel Pg adjacent to the common wiring 62. Yes.

  As shown in FIG. 5, the blue subpixel Pb is partitioned in the vertical direction by a selection wiring 60 and a power supply wiring 61 in the next row. In such a blue subpixel Pb, the blue subpixel Pb is viewed in plan view. The drive transistor 23 is arranged along the scanning line X, the switch transistor 21 is arranged along the supply line Z and the power supply wiring 61 in the adjacent row, and the holding transistor 22 is a blue subpixel adjacent to the scanning line X. It arrange | positions at the corner | angular part of Pb.

  As shown in FIGS. 3 to 5, in any of the subpixels Pr, Pg, and Pb, the capacitor 24 is disposed along the left side of the signal line group 4 (not shown) in the right adjacent column. Further, the source 21s of the switch transistor 21 is connected to the signal line Yr in the red subpixel Pr shown in FIG. 3, and is connected to the signal line Yg in the green subpixel Pg shown in FIG. The blue subpixel Pb is connected to the signal line Yb.

  Note that when the entire display panel 1 is viewed in plan and attention is paid only to the switch transistors 21 of all the subpixels Pr, Pg, Pb, a plurality of switch transistors 21 are arranged in a matrix, and all the subpixels Pr, Pg, Focusing only on the holding transistor 22 of Pb, a plurality of holding transistors 22 are arranged in a matrix, and focusing on only the driving transistors 23 of all the subpixels Pr, Pg, Pb, a plurality of driving transistors 23 are arranged in a matrix. Has been.

[Layer structure of display panel]
The layer structure of the display panel 1 will be described with reference to FIGS. 6 is a cross-sectional view taken along the line VI-VI shown in FIGS. 3 to 5 in the thickness direction of the insulating substrate 2, and FIG. 7 is a line VII shown in FIG. It is arrow sectional drawing cut | disconnected in the thickness direction of the insulated substrate 2 along -VII.

  4 and FIG. 5 similar to the line VII-VII in FIG. 3 is also a cross-sectional view substantially similar to FIG. FIG. 6 shows the distance between the switch transistor 21 and the drive transistor 23 in the same sub-pixel shorter than the actual one. FIG. 7 shows the contact hole 64 and the lower layer electrodes 24A and 24B of the capacitor 24. The interval of is shown shortened from the actual. Further, since the holding transistor 22 has the same layer structure as that of the driving transistor 23, a cross-sectional view of the holding transistor 22 is omitted. In any of the subpixels Pr, Pg, Pb, the switch transistor 21, the holding transistor 22, and the driving transistor 23 have the same layer structure.

  The display panel 1 is obtained by laminating various layers on an insulating substrate 2 having optical transparency. The insulating substrate 2 is provided in the form of a flexible sheet or is provided in the form of a rigid plate.

  First, the layer structure of the transistors 21 to 23 will be described. As shown in FIG. 6, the switch transistor 21 includes a gate 21g formed on the insulating substrate 2, a gate insulating film 31 formed on the gate 21g, and a semiconductor facing the gate 21g across the gate insulating film 31. A film 21c, a channel protective film 21p formed on the central portion of the semiconductor film 21c, and an impurity semiconductor film 21a formed so as to be separated from each other on both ends of the semiconductor film 21c and partially overlapping the channel protective film 21p, 21b, a drain 21d formed on the impurity semiconductor film 21a, and a source 21s formed on the impurity semiconductor film 21b. Note that the drain 21d and the source 21s may have a single-layer structure or a stacked structure of two or more layers.

  The driving transistor 23 includes a gate 23g formed on the insulating substrate 2, a gate insulating film 31 formed on the gate 23g, a semiconductor film 23c facing the gate 23g with the gate insulating film 31 interposed therebetween, and a semiconductor film 23c. Impurity protective film 23a, 23b formed on the both sides of the semiconductor film 23c so as to be separated from each other and partially overlapped with the channel protective film 23p, and the impurity semiconductor film 23a It has a drain 23d formed thereon and a source 23s formed on the impurity semiconductor film 23b.

  When viewed in plan as shown in FIGS. 3 to 5, the channel width of the drive transistor 23 is widened because the source 23 s and the drain 23 d of the drive transistor 23 are provided in a comb shape. Note that the distance between the source 23s and the drain 23d is constant over the entire channel width. The drain 23d and the source 23s may have a single layer structure or a stacked structure of two or more layers.

  Although not shown, the holding transistor 22 includes a gate 22g formed on the insulating substrate 2, a gate insulating film 31 formed on the gate 22g, and a gate insulating film, like the switch transistor 21 and the drive transistor 23. A semiconductor film facing the gate 22g across the gate 31, a channel protective film formed on the central portion of the semiconductor film, and formed on both ends of the semiconductor film so as to be separated from each other, and partially overlaps the channel protective film An impurity semiconductor film, and a drain 22d and a source 22s formed on the impurity semiconductor film, respectively.

  In any of the subpixels Pr, Pg, and Pb, the switch transistor 21, the holding transistor 22, and the driving transistor 23 have the same layer structure.

As shown in FIG. 7, the capacitor 24 has a lower layer electrode 24A formed on the insulating substrate 2, a gate insulating film 31 formed on the lower electrode 24A, and a lower electrode sandwiching the gate insulating film 31 therebetween. And an upper layer electrode 24B facing 24A. The capacitor 24 has the same layer structure in any of the subpixels Pr, Pg, and Pb.
In each pixel 3, a connection line 65 connects the supply line Z and the drains 23d of the drive transistors 23 of all the subpixels Pr, Pg, and Pb. In each subpixel Pr, Pg, Pb, a gate connection line 66 connects the gate 21g of each switch transistor 21 and the gate 22g of each holding transistor 22.

  Regarding the relationship between each layer of the transistors 21 to 23 and the capacitor 24 and the signal line Y, the scanning line X, and the supply line Z, as shown in FIGS. 3 to 7, the switch transistors 21 of all the subpixels Pr, Pg, and Pb. The gate 21g of the holding transistor 22, the gate 22g of the holding transistor 22, the gate 23g of the driving transistor 23, the lower layer electrode 24A of the capacitor 24, the connection line 65, the gate connection line 66, and all the signal lines Yr, Yg, Yb are on the insulating substrate 2. In addition, the conductive films formed on the entire surface are collectively formed by patterning by a photolithography method and an etching method.

  Hereinafter, the gate 21g of the switch transistor 21, the gate 22g of the holding transistor 22, the gate 23g of the driving transistor 23, the lower layer electrode 24A of the capacitor 24, the connection line 65, and the gate 22g of the holding transistor 22 of each subpixel Pr, Pg, Pb. The conductive film that is the source of the gate connection line 66 and the signal lines Yr, Yg, and Yb that connect the two is called a gate layer.

  The gate insulating film 31 is a film common to the switch transistor 21, the holding transistor 22, the driving transistor 23, and the capacitor 24 of all the subpixels Pr, Pg, and Pb, and is formed over the entire surface. Accordingly, the gate insulating film 31 includes the gate 21g of the switch transistor 21, the gate 22g of the holding transistor 22, the gate 23g of the driving transistor 23, the lower layer electrode 24A of the capacitor 24, the connection line 65, the gate connection line 66, and the signal lines Yr, Yg. , Yb is coated.

  The drain 21d and source 21s of the switch transistor 21 of all the subpixels Pr, Pg, and Pb, the drain 22d and source 22s of the holding transistor 22, the drain 23d and source 23s of the driving transistor 23, the upper layer electrode 24B of the capacitor 24, and all the scans. The line X and the supply line Z are collectively formed by patterning a conductive film formed on the entire surface of the gate insulating film 31 by a photolithography method and an etching method.

  In the following, the drain 21d and source 21s of the switch transistor 21, the drain 22d and source 22s of the holding transistor 22, the drain 23d and source 23s of the driving transistor 23, the upper layer electrode 24B of the capacitor 24, the source of the scanning line X and the supply line Z This conductive film is called a drain layer.

  As described above, the drain 22d of the holding transistor 22 and the drain 23d of the driving transistor 23 are integrally formed with the supply line Z. Further, one contact hole 67 is formed at a portion of the gate insulating film 31 where the connecting line 65 overlaps with an integrally formed portion of the driving transistor 23 of the red subpixel Pr with the drain 23d, and the driving transistor of the green subpixel Pg. One contact hole 67 is formed at each of the locations where the drain 23d of the 23 and the connection line 65 overlap and at the location where the drain 23d and the connection line 65 of the blue subpixel Pb and the driving transistor 23 overlap each other. , Pg, and Pb, the drain 23 d of the drive transistor 23 is electrically connected to the connection line 65 through the contact hole 67.

  Further, one contact hole 68 is formed at a position overlapping the signal line Y of the gate insulating film 31 for each subpixel P of one dot, and the source 21s of the switch transistor 21 is in contact with any of the subpixels Pr, Pg, and Pb. The signal lines Yr, Yg, and Yb are electrically connected through the holes 68, respectively.

  One contact hole 69 is formed at a position overlapping the scanning line X of the gate insulating film 31, and the gate 21g of the switch transistor 21 and the gate 22g of the holding transistor 22 are in contact with each other in any of the subpixels Pr, Pg, and Pb. The scanning line X is conducted through the hole 69 and the gate connection line 66. In addition, one contact hole 70 is formed in one dot subpixel P at a position overlapping the lower electrode 24A of the gate insulating film 31, and the source 22s of the holding transistor 22 is the driving transistor in any of the subpixels Pr, Pg, and Pb. 23 is electrically connected to the gate 23g of the capacitor 23 and the lower electrode 24A of the capacitor 24.

  All the sub-pixels Pr, Pg, and Pb switch transistors 21, holding transistors 22 and drive transistors 23, and all the scanning lines X and supply lines Z are protective insulating films such as silicon nitride or silicon oxide formed on the entire surface. 32. In addition, although mentioned later for details, the protective insulating film 32 is divided | segmented into the rectangular shape in the location which overlaps with the scanning line X and the supply line Z. FIG.

  A planarization film 33 is stacked on the protective insulating film 32, and unevenness due to the steps of the switch transistor 21, the holding transistor 22, the drive transistor 23, the scanning line X, and the supply line Z is eliminated by the planarization film 33. That is, the surface of the planarizing film 33 is flat. The planarizing film 33 is obtained by curing a photosensitive insulating resin such as polyimide, and preferably has a thickness of 2 μm or more. In addition, although mentioned later for details, the planarization film | membrane 33 is divided | segmented into the rectangular shape in the location which overlaps with the scanning line X and the supply line Z. FIG.

  In this embodiment, since the display panel 1 is used as a bottom emission type, that is, the insulating substrate 2 is used as a display surface, a transparent material is used for the gate insulating film 31, the protective insulating film 32, and the planarizing film 33. . A stacked structure from the insulating substrate 2 to the planarizing film 33 is referred to as a transistor array substrate 50.

  An insulating line 51 parallel to the scanning line X is formed between the red subpixel Pr and the green subpixel Pg on the surface of the planarizing film 33, that is, on the surface of the transistor array substrate 50. The insulating line 51 includes an inorganic compound such as silicon nitride, and a common wiring 62 narrower than the insulating line 51 is stacked on the insulating line 51. Since the common wiring 62 is formed by a plating method, the common wiring 62 is sufficiently thicker than the signal line Y, the scanning line X, and the supply line Z and protrudes from the surface of the planarization film 33. The common wiring 62 preferably includes at least one of gold, silver, copper, and nickel.

  A liquid repellent conductive layer 54 having water repellency and oil repellency is formed on the surface of the common wiring 62. In the liquid repellent conductive layer 54, for example, the hydrogen atom (H) of the mercapto group (—SH) of triazyltrithiol represented by the following chemical formula is reduced and released, and the sulfur atom (S) is present on the surface of the common wiring 62. Oxidized and adsorbed.

  Since the liquid repellent conductive layer 54 is a film made of an extremely thin molecular layer in which triazyltrithiol molecules are regularly arranged on the surface of the common wiring 62, electricity can be conducted in the thickness direction. In addition, in order to make water repellency and oil repellency remarkable, instead of triazyltrithiol, 1 or 2 mercapto groups of triazyltrithiol may be substituted with fluorinated alkyl groups. However, if the carbon atoms of the fluorinated alkyl group are bifurcated or bifurcated, the amount of the triazylthiol compound bonded to the common wiring 62 is reduced due to steric hindrance, so the carbon atoms are linear. Is preferred. The triazylthiol compound that becomes the liquid repellent conductive layer 54 has a property of being selectively bonded to a metal such as the common wiring 62 when applied as a solution containing the triazylthiol compound.

  In the portions of the protective insulating film 32 and the planarizing film 33 that overlap each supply line Z, a long groove 34 that is opened along the horizontal direction is recessed, and further, the protective insulating film 32 and the planarizing film 33 are formed. A long groove 35 opened in the horizontal direction is provided in a portion overlapping each scanning line X. The protective insulating film 32 and the planarizing film 33 are divided into rectangular shapes by the grooves 34 and 35. A power supply wiring 61 is buried in the groove 34, and the power supply wiring 61 is electrically connected by being stacked on the supply line Z in the groove 34. The selection wiring 60 is buried in the groove 35, and the selection wiring 60 is electrically connected by being stacked on the scanning line X in the groove 35.

  Since the selection wiring 60 and the power supply wiring 61 are formed by electrolytic plating using the scanning line X or the supply line Z as a base electrode, they are more sufficient than the signal lines Yr, Yg, Yb, the scanning line X, and the supply line Z. Thick. Furthermore, the thickness of the selection wiring 60 and the power supply wiring 61 is thicker than the total thickness of the protective insulating film 32 and the planarization film 33, and protrudes from the surface of the planarization film 33. Both the selection wiring 60 and the power supply wiring 61 preferably include at least one of gold, silver, copper, and nickel.

  A hydrophobic insulating film 52 having water repellency / oil repellency is formed on the surface of the selection wiring 60, and a hydrophobic insulating film 53 having water repellency / oil repellency is formed on the surface of the power supply wiring 61. . Both of the hydrophobic insulating films 52 and 53 are made of a fluororesin electrodeposition paint (trade name Elecoat Nicelon, Elecoat Niceron CTR, manufactured by Shimizu Corporation), and selectively supply voltage to the selective wiring 60 to perform electrodeposition coating. The film is formed. Since the hydrophobic insulating films 52 and 53 are coated to a sufficient thickness, the selection wiring 60 and the power supply wiring 61 are electrically insulated from each other.

  The liquid repellent conductive layer 54 is coated on the common wiring 62 after the surfaces of the selection wiring 60 and the power supply wiring 61 are covered with the hydrophobic insulating films 52 and 53, respectively. That is, when the solution containing the triazylthiol compound that becomes the liquid repellent conductive layer 54 is applied to the entire surface, the surfaces of the selection wiring 60 and the power supply wiring 61 are not exposed by the hydrophobic insulating films 52 and 53, Not combined with all compounds. Further, the triazylthiol compound is not coated to such an extent that liquid repellency is exhibited even on the subpixel electrode 20a having a metal oxide such as ITO, which will be described later, so that even if the subpixel electrode 20a has already been formed. Only the common wiring 62 is selectively coupled.

  On the planarizing film 33 above the signal line group 4, the connection line 65, and the gate connection line 66, the insulating film 55 as a bank extends in the vertical direction along the signal line group 4 and the like in plan view. Are stacked.

  A plurality of subpixel electrodes 20 a are arranged in a matrix on the surface of the planarizing film 33, that is, on the surface of the transistor array substrate 50. The subpixel electrode 20 a is an electrode that functions as an anode of the organic EL element 20. That is, it is preferable that the work function of the subpixel electrode 20a is relatively high and holes are efficiently injected into the organic EL layer 20b described later. In addition, the subpixel electrode 20a is transmissive to visible light in the case of bottom emission.

These subpixel electrodes 20a are obtained by patterning a transparent conductive film formed on the entire surface of the planarizing film 33 by a photolithography method or an etching method. As the subpixel electrode 20a, for example, tin-doped indium oxide (ITO), zinc-doped indium oxide, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), or cadmium-tin oxide ( CTO) is the main component.

  One contact hole 64 is formed for each of the subpixels Pr, Pg, and Pb at a portion that overlaps the subpixel electrode 20a of the planarizing film 33 and the protective insulating film 32, and a conductive pad is embedded in the contact hole 64. . In any subpixel Pr, Pg, Pb, the subpixel electrode 20a is electrically connected to the upper layer electrode 24B of the capacitor 24, the drain 21d of the switch transistor 21, and the source 23s of the drive transistor 23. The conductive pad is formed together with the power supply wiring 61, and particularly preferably formed by electrolytic plating using the upper layer electrode 24B as a base electrode.

  An organic EL layer 20b of the organic EL element 20 is formed on the subpixel electrode 20a. The organic EL layer 20b is a light-emitting layer in a broad sense, and the organic EL layer 20b contains a light-emitting material (phosphor) that is an organic compound. The organic EL layer 20b has a two-layer structure in which a hole transport layer and a narrow light-emitting layer are sequentially stacked from the subpixel electrode 20a. The hole transport layer is made of PEDOT (polythiophene) which is a conductive polymer and PSS (polystyrene sulfonic acid) which is a dopant, and the light-emitting layer in a narrow sense is made of a polyfluorene-based light-emitting material.

  In the case of the red subpixel Pr, the organic EL layer 20b emits red light, in the case of the green subpixel Pg, the organic EL layer 20b emits green light, and in the case of the blue subpixel Pb, the organic EL layer 20b. 20b emits blue light.

  In addition to the two-layer structure, the organic EL layer 20b may have a three-layer structure that becomes a hole transport layer, a narrow light-emitting layer, and an electron transport layer in order from the subpixel electrode 20a, or a narrow light-emitting layer. It may be a single layer structure composed of the above, or a laminated structure in which an electron or hole injection layer is interposed between appropriate layers in these layer structures, or another laminated structure.

  The organic EL layer 20b of each color has a plurality of subpixel electrodes 20a arranged in the horizontal direction between two of the selection wiring 60, the power supply wiring 61, and the common wiring 62 that are adjacent to each other in the vertical direction. The film is formed so as to cover it. That is, the red light emitting organic EL layer 20b is between the power supply wiring 61 and the common wiring 62, the green light emitting organic EL layer 20b is between the common wiring 62 and the selection wiring 60, and the blue light emitting organic EL layer 20b is the selection wiring. 60 and the power supply wiring 61 are each formed into a strip shape. The organic EL layer 20b is provided independently for each sub-pixel electrode 20a, and when viewed in plan, a plurality of organic EL layers 20b may be arranged in a matrix.

  The organic EL layer 20b is formed by a wet coating method (for example, an ink jet method) after coating the hydrophobic insulating films 52 and 53 or the liquid repellent conductive layer 54 on the selection wiring 60, the power supply wiring 61, and the common wiring 62. In this case, an organic compound-containing liquid containing an organic compound that becomes the organic EL layer 20b is applied to the subpixel electrode 20a, but the thick wiring selection wiring 60 having a sufficiently high top between the subpixel electrodes 20a adjacent in the vertical direction. Since the power supply wiring 61 and the common wiring 62 are projected from the surface of the transistor array substrate 50, the organic compound-containing liquid applied to the subpixel electrode 20a leaks to the subpixel electrode 20a adjacent in the vertical direction. There is no.

  Further, since the selection wiring 60, the power supply wiring 61, and the common wiring 62 are coated with a water- and oil-repellent hydrophobic insulating film 52, a hydrophobic insulating film 53, and a liquid-repellent conductive layer 54, respectively, the sub-pixel electrode 20a is coated. The organic compound-containing liquid applied to the subpixel electrode 20a is repelled from the applied organic compound-containing liquid, and the vicinity of the end of the liquid-repellent conductive layer 54 and the hydrophobic insulating films 52 and 53 with respect to the center of the subpixel electrode 20a. Since it is not deposited extremely thick in the vicinity of the end portion, the organic EL layer 20b formed by drying the organic compound-containing liquid can be formed with a uniform film thickness in the surface.

  On the organic EL layer 20b, a counter electrode 20c that functions as a cathode of the organic EL element 20 is formed. The counter electrode 20c is formed so as to continuously cover the upper surface and the side surface of the common wiring 62, and energizes the common wiring 62 with the liquid repellent conductive layer 54 interposed therebetween. As described above, the counter electrode 20 c is electrically connected to the common wiring 62. On the other hand, since the selection wiring 60 is coated with the hydrophobic insulating film 52 and the power supply wiring 61 is coated with the hydrophobic insulating film 53 sufficiently thick, the counter electrode 20c is not connected to either the selection wiring 60 or the power supply wiring 61. Is also insulated.

  The counter electrode 20c is made of a material having a work function lower than that of the subpixel electrode 20a. For example, the counter electrode 20c is made of a simple substance or an alloy containing at least one of magnesium, calcium, lithium, barium, indium, and a rare earth metal. Is preferred. Further, the counter electrode 20c may have a laminated structure in which layers of the above various materials are laminated, and in addition to the above layers of various materials, a metal layer that is not easily oxidized is deposited in order to reduce sheet resistance. Specifically, it may have a laminated structure. Specifically, a low-work function high-purity barium layer provided on the interface side in contact with the organic EL layer 20b, and an aluminum layer provided so as to cover the barium layer; And a laminated structure in which a lower layer is provided with a lithium layer and an upper layer is provided with an aluminum layer.

  In the present embodiment, as shown in FIG. 7, the counter electrode 20c is divided without being covered by the insulating film 55 above the signal line group 4, and has a stripe shape extending in the vertical direction. Has been. Thus, since the plurality of counter electrodes 20c do not overlap with the signal lines Yr, Yg, Yb in plan view, the parasitic capacitance between the signal lines Yr, Yg, Yb overlaps. It is extremely small compared.

  For this reason, even if the write current is a minute current required to emit light from each organic EL element 20, the charge can be quickly charged to the parasitic capacitance of each signal line Yr, Yg, Yb, and the current is delayed. Therefore, the signal lines Yr, Yg, and Yb are steadily flowing and the potential between the gate and the source of the driving transistor 23 can be quickly brought into a state where the driving current flows.

  A protective film 56 is formed on the counter electrode 20c. The protective film 56 is an inorganic film or an organic film that covers the counter electrode 20 c other than the tops of the selection wiring 60, the power supply wiring 61, and the common wiring 62. Therefore, deterioration of the counter electrode 20c is prevented by the protective film 56.

  On the counter electrode 20 c that covers the tops of the selection wiring 60, the power supply wiring 61, and the common wiring 62, a flat sealing substrate 80 is attached so as to cover almost the entire surface of the display panel 1. In this embodiment, the sealing substrate 80 includes a sealing glass 81, a conductive layer 82 provided on the surface to be attached to the counter electrode 20c, and a conductive adhesive layer 83 applied to the surface thereof. And have. Instead of using the sealing glass 81 and the conductive layer 82, it is also possible to use a light-reflective conductive material such as a metal plate as a unit.

  In the present embodiment, the conductive layer 82 is formed on the entire surface of the sealing glass 81 as a conductive material film having a sheet resistance lower than that of the counter electrode 20c such as copper tin plating. The adhesive layer 83 is formed of an anisotropic conductive adhesive. As the anisotropic conductive adhesive, for example, Ni / Au plated conductive particles are dispersed in an epoxy resin binder. Is preferably used.

  The sealing substrate 80 is attached to the counter electrode 20 c that covers the selection wiring 60, the power supply wiring 61, and the common wiring 62 through the adhesive layer 83. That is, all of the counter electrodes 20 c on each common wiring 62 are electrically connected to the conductive layer 82 through the conductive adhesive layer 83 by the protruding step of the common wiring 62. Therefore, since the counter electrode 20c of all the pixels 3 is electrically connected to the low resistance conductive layer 82 and the common wiring 62, the counter electrode 20c of all the pixels 3 includes at least the low resistance conductive layer 82 and the common wiring 62. The common voltage Vcom output from one side is input. Since such a common wiring 62 is provided for each pixel 3, the counter electrode 20 c has a low resistance due to the common wiring 62 and the conductive layer 82. Therefore, either the conductive layer 82 or the common wiring 62 is common. When the voltage Vcom is output, the counter electrode 20c has a uniform voltage distribution in the surface of the display panel 1. Note that the selection wiring 60 and the power supply wiring 61 are originally insulated from the counter electrode 20 c by the hydrophobic insulating films 52 and 53, and thus insulated from the conductive layer 82 of the sealing substrate 80. Although the adhesive layer 83 is formed on the entire surface of the conductive layer 82, only the portion facing the selection wiring 60, the power supply wiring 61, and the common wiring 62 may be selectively formed.

  In addition, an inert gas such as nitrogen is sealed in the space between the sealing substrate 80 and the organic EL element 20.

[Driving method of display panel]
FIG. 8 is a schematic plan view showing the wiring structure of the display panel. 8 and FIG. 10 described later show a state where the sealing substrate 80 is removed. The subpixels Pr, Pg, and Pb are expressed in a so-called vertically long shape, but actually, as shown in FIGS. 1 and 3 to 5.

In the display panel 1, as shown in FIG. 8, a selection driver 90 to which the scanning lines X _{1 to} X _m and the selection wirings 60, 60,... Are connected is arranged on the first peripheral portion of the insulating substrate 2. The power supply driver 91 to which the electrically insulated supply lines Z _{1 to} Z _m and the power supply wirings 61, 61,... Are connected is provided on the second peripheral edge which is the peripheral edge facing the first peripheral edge of the insulating substrate 2. Has been placed. Hereinafter, when a voltage is applied to the scanning lines X _{1 to} X _m and the supply lines Z _{1 to} Z _m , the voltage is similarly applied to the selection wirings 60, 60,. This means that it is performed.

  The display panel 1 is driven by the active matrix method as follows.

As shown in FIG. 9, a high by the connected selection driver 90 to the scan lines X ₁ to X _m, in order (next scan line X _m scanning lines X ₁₎ from the scan line X ₁ to scan line X _m The scanning lines X _{1 to} X _m are sequentially selected by sequentially outputting level shift pulses. The switch transistor 21 is selected by selecting the scanning lines X _{1 to} X _m . Further, during this selection period, the power supply driver 91 connected to the supply lines Z _{1 to} Z _m causes the drive transistor 23 connected to the supply line Z _i of the pixel in the row corresponding to the selected scanning line X _i to A write power supply voltage VL for applying a write current is applied, and a drive power supply voltage VH for applying a drive current to the organic EL element 20 is applied via the drive transistor 23 during the subsequent light emission period.

That is, the power supply driver 91 synchronizes with the selection driver 90 in order from the supply line Z ₁ to the supply line Z _m (the supply line Z ₁ is next to the supply line Z _m ) (low level of the organic EL element 20). The supply lines Z _{1 to} Z _m are sequentially selected by sequentially outputting the write power supply voltage VL having a lower level than the voltage of the counter electrode. Further, when the selection driver 90 selects each of the scanning lines X _{1 to} X _m , a data driver (not shown) connected to each signal line group 4 (signal lines Yr, Yg, Yb) is a write current. A sink current (current signal) is caused to flow to all signal lines Yr ₁ , Yg ₁ , Yb _{1 to} Yr _n , Yg _n , Yb _n through the source and drain of the driving transistors 23 in a predetermined row.

  At that time, the counter electrode 20c and the common wiring 62 group are connected to the outside by the conductive layer 82 of the sealing substrate 80 (not shown in FIG. 8), and are set to a constant common potential Vcom (for example, ground = 0 volts). It is kept.

In each selection period, the potential of the data driver side, feed interconnections 61, 61, ... and the supply lines Z ₁ to Z _m output to the and below the write feed voltage VL the write feed voltage VL below the common potential Vcom Is set to Therefore, as shown in FIG. 2, since the organic EL element 20 does not flow from the organic EL element 20 to the signal lines Yr, Yg, Yb at this time, a write current (drawing current) having a current value corresponding to the gradation by the data driver. Flows to the signal lines Yr, Yg, Yb as shown by the arrow A. In FIG. 2, the arrow A and the arrow B described later are shown only for the blue subpixel Pb _{i, j} , but the same applies to the red subpixel Pr _{i, j} and the green subpixel Pg _{i, j.} .

That is, in the subpixel P _{i, j} , the signal lines Yr _j , Yg _j , and Yb _j are connected to the signal lines Yr _j , Yg _j , and Yb _j from the power supply wiring 61 and the supply line Z _i through the source and drain of the driving transistor 23 and between the source and drain of the switch transistor 21. The directed write current (drawing current) flows. In this way, the current value of the current flowing between the source and drain of the drive transistor 23 is uniquely controlled by the data driver, and the data driver has a write current (drawing current) according to the gradation input from the outside. Set the current value.

While the write current (pull-out current) is flowing, i-th row of P _i, 1 to P _i, the voltage between the gate 23g- source 23s of the driving transistor 23 of the _n each signal line Yr _1, Yg _{1 , Yb 1 ~Yr n, Yg n} , the current value of the write current (pull-out current) flowing to the Yb _n, i.e. between the drain 23d- source 23s of the driving transistor 23 independently of the change over time in the Vg-Ids characteristic of the driving transistor 23 Is forcibly set to match the current value of the write current (drawing current) flowing through the capacitor 24, and the capacitor 24 is charged with a charge having a magnitude according to the level of this voltage. The value is converted into a voltage level between the gate 23g and the source 23s of the driving transistor 23.

In the subsequent light emission period, the scanning line X _i becomes a low level, and the switch transistor 21 and the holding transistor 22 are turned off. However, the charge on the electrode 24A side of the capacitor 24 is confined by the holding transistor 22 in the off state and floats. Even if the voltage of the source 23s of the drive transistor 23 is modulated when the voltage shifts from the selection period to the light emission period, the potential difference between the gate 23g and the source 23s of the drive transistor 23 is maintained as it is.

In this light emission period, the potential of the supply line Z _i and the power supply wiring 61 connected thereto becomes the drive power supply voltage VH, which is higher than the potential Vcom of the counter electrode 20c of the organic EL element 20, thereby connecting to the supply line Z _i and the supply line Z _i. A driving current flows in the direction of arrow B from the supplied power supply wiring 61 to the organic EL element 20 through the driving transistor 23, and the organic EL element 20 emits light. Since the current value of the drive current depends on the voltage between the gate 23g and the source 23s of the drive transistor 23, the current value of the drive current in the light emission period is equal to the current value of the write current (drawing current) in the selection period.

  It is also possible to drive the display panel 1 by another method using an active matrix method. FIG. 10 is a schematic plan view showing a wiring structure of a display panel driven by the second method.

As shown in FIG. 10, the second display panel 1 has a structure in which a selection driver 90 to which the scanning lines X _{1 to} X _m are connected is arranged on the first peripheral edge of the insulating substrate 2, and the power supply wiring 61. , 61,... Are connected to each other so that the lead wiring 92 formed integrally with the power supply wirings 61, 61,... Is a peripheral edge facing the first peripheral edge of the insulating substrate 2. It is arranged in the part. The routing wiring 92 receives clock signals from both the terminal portion 92d and the terminal portion 92e located at the third peripheral portion and the fourth peripheral portion orthogonal to the first peripheral portion and the second peripheral portion, respectively. .

  The active matrix driving method of the second display panel 1 is as follows.

That is, as shown in FIG. 11, an external oscillation circuit outputs a clock signal to the power supply wirings 61, 61,... And the supply lines Z _{1 to} Z _m through the terminal portion 92 d and the terminal portion 92 e through the wiring 92. To do. The scanning lines X ₁ to X _m by sequentially outputting the high-level shift pulse sequentially (the next scan line X _m scanning lines X ₁₎ from the scanning line X ₁ by the selection driver 90 to the scan line X _m Are sequentially selected, but when the selection driver 90 outputs a high level, that is, on-level shift pulse, one of the scanning lines X _{1 to} X _m , the clock signal of the oscillation circuit becomes low level. In addition, when the selection driver 90 selects each of the scanning lines X _{1 to} X _m , the data driver sends a drawing current (current signal) as a write current to all the signal lines via the source and drain of the driving transistor 23. Yr ₁ , Yg ₁ , Yb _{1 to} Yr _n , Yg _n , Yb _n are passed.

  At that time, the counter electrode 20c and the common wiring 62 group are connected to the outside by the conductive layer 82 of the sealing substrate 80 (not shown in FIG. 8), and are set to a constant common potential Vcom (for example, ground = 0 volts). It is kept. The common potential Vcom is output by one or both of the common wiring 62 group and the conductive layer 82.

In the selection period of the scan line X _i, from the shift pulse to the i-th scanning line X _i is output, the switch transistor 21 and holding transistor 22 are turned on. In each selection period, the potential of the data driver side, feed interconnections 61, 61, ... and the low level of the supply lines Z ₁ to Z _m and the clock signal following a low level of the clock signal output to the following common potential Vcom Is set to

Accordingly, at this time, since the organic EL element 20 does not flow to the signal line lines Yr _j , Yg _j , Yb _j , as shown in FIG. 2, the write current having a current value corresponding to the gradation by the data driver is used. As shown by the arrow A, the (drawing current) flows through the signal lines Yr ₁ , Yg ₁ , Yb _{1 to} Yr _n , Yg _n , Yb _n and is driven from the power supply wiring 61 and the supply line Z _i in the subpixel P _{i, j} . A write current (extraction current) directed to the signal lines Yr _j , Yg _j , Yb _j flows between the source and drain of the transistor 23 and between the source and drain of the switch transistor 21. In this way, the current value of the current flowing between the source and drain of the drive transistor 23 is uniquely controlled by the data driver, and the data driver has a write current (drawing current) according to the gradation input from the outside. Set the current value.

While the write current (pull-out current) is flowing, i-th row of P _i, 1 to P _i, the voltage between the gate 23g- source 23s of the driving transistor 23 of the _n each signal line Yr _1, Yg _{1 , Yb 1 ~Yr n, Yg n} , the current value of the write current (pull-out current) flowing to the Yb _n, i.e. between the drain 23d- source 23s of the driving transistor 23 independently of the change over time in the Vg-Ids characteristic of the driving transistor 23 Is forcibly set to match the current value of the write current (drawing current) flowing through the capacitor 24, and the capacitor 24 is charged with a charge having a magnitude according to the level of this voltage. The value is converted into a voltage level between the gate 23g and the source 23s of the driving transistor 23.

In the subsequent light emission period, the scanning line X _i becomes a low level, and the switch transistor 21 and the holding transistor 22 are turned off. However, the charge on the electrode 24A side of the capacitor 24 is confined by the holding transistor 22 in the off state and floats. Even if the voltage of the source 23s of the drive transistor 23 is modulated when the voltage shifts from the selection period to the light emission period, the potential difference between the gate 23g and the source 23s of the drive transistor 23 is maintained as it is.

During this light emission period, during which the row is not a selection period, that is, the clock signal is high when the potential of the power supply wiring 61 and the supply line Z _i is higher than the potential Vcom of the counter electrode 20 c of the organic EL element 20 and the power supply wiring 61. During the level, the drive current flows in the direction of arrow B from the higher potential power supply line 61 and the supply line Z _i to the organic EL element 20 through the source and drain of the drive transistor 23, and the organic EL element 20 emits light. .

Since the current value of the drive current depends on the voltage between the gate 23g and the source 23s of the drive transistor 23, the current value of the drive current in the light emission period is equal to the current value of the write current (drawing current) in the selection period. In the light emission period, during the selection period of any row, that is, when the clock signal is at a low level, the potential of the power supply wiring 61 and the supply line Z _i is equal to or lower than the potential Vcom of the counter electrode 20c and the power supply wiring 61. Therefore, no drive current flows through the organic EL element 20 and no light is emitted.

  In any of the driving methods, the switch transistor 21 functions to turn on (selection period) and off (light emission period) the current between the source 23s of the driving transistor 23 and the signal line Y. The holding transistor 22 is in a state in which a current can flow between the source 23s and the drain 23d of the driving transistor 23 during the selection period, and holds the voltage applied between the gate 23g and the source 23s of the driving transistor 23 during the light emission period. It functions as a thing. The drive transistor 23 drives the organic EL element 20 by causing a current having a magnitude corresponding to the gradation to flow through the organic EL element 20 when the supply line Z and the power supply wiring 61 become high level during the light emission period. It functions as a thing.

[Width, cross-sectional area and resistivity of power supply wiring and common wiring]
Hereinafter, the width, cross-sectional area, and resistivity of the power supply wiring and the common wiring of the display panel 1 of the first embodiment are defined. The same applies to the second embodiment described later. Here, the desirable width and cross-sectional area of the power supply wiring 61 and the common wiring 62 when the number of pixels of the display panel 1 is WXGA (768 × 1366) are defined. Note that the desirable width and the like for the common wiring 62 described below is for the case where the sealing substrate 80 is not provided, and those conditions are relaxed when the sealing substrate 80 is provided.

  FIG. 12 is a graph showing current-voltage characteristics of the driving transistor 23 and the organic EL element 20 of each subpixel. In FIG. 12, the vertical axis represents the current value of the write current flowing between the source 23s and the drain 23d of one drive transistor 23 or the current value of the drive current flowing between the anode and the cathode of one organic EL element 20. The axis is the voltage between the source 23s and the drain 23d of one drive transistor 23 (at the same time, the voltage between the gate 23g and the drain 23d of one drive transistor 23).

  In the figure, solid line Ids max is a write current and drive current at the maximum luminance gradation (brightest display), and alternate long and short dash line Ids mid is an intermediate luminance between the highest luminance gradation and the lowest luminance gradation. The two-dot chain line Vpo is a threshold value, that is, a pinch-off voltage between the unsaturated region (linear region) and the saturated region of the driving transistor 23, and the three-dot chain line Vds is the driving transistor 23. The write current flowing between the source 23 s and the drain 23 d of the organic EL element 20, and the broken line Iel is the drive current flowing between the anode and the cathode of the organic EL element 20.

  Here, the voltage VP1 is a pinch-off voltage of the driving transistor 23 at the maximum luminance gradation, and the voltage VP2 is a source-drain voltage when a writing current of the maximum luminance gradation flows through the driving transistor 23. VELmax (voltage VP4−voltage VP3) is a voltage between the anode and the cathode when the organic EL element 20 emits light with the driving current of the maximum luminance gradation whose current value is equal to the writing current of the maximum luminance gradation. The voltage VP2 ′ is a source-drain voltage when the driving transistor 23 receives an intermediate luminance gradation write current, and the voltage (voltage VP4′−voltage VP3 ′) is an organic EL element 20 having an intermediate luminance gradation. This is the anode-cathode voltage when light is emitted with a drive current of an intermediate luminance gradation whose current value is equal to the write current.

Since both the drive transistor 23 and the organic EL element 20 are driven in the saturation region, a value VX obtained by subtracting the voltage Vcom during the light emission period of the common wiring 62 from the voltage VH during the light emission period of the power supply wiring 61 is expressed by the following formula ( 1) is satisfied.
VX = Vpo + Vth + Vm + VEL (1)

  Vth (equal to VP2−VP1 at the maximum luminance) is a threshold voltage of the drive transistor 23, VEL (equal to VELmax at the maximum luminance) is an anode-cathode voltage of the organic EL element 20, and Vm is The allowable voltage is displaced according to the gradation.

  As is apparent from the figure, the higher the luminance gradation of the voltage VX, the higher the voltage (Vpo + Vth) required between the source and drain of the transistor 23 and the voltage VEL required between the anode and cathode of the organic EL element 20. Becomes higher. Therefore, the allowable voltage Vm becomes lower as the luminance gradation becomes higher, and the minimum allowable voltage Vmmin becomes VP3−VP2.

  The organic EL element 20 generally deteriorates with time regardless of the low-molecular EL material and the high-molecular EL material, and increases in resistance. It has been confirmed that the anode-cathode voltage after 10,000 hours is about 1.4 times the initial voltage. That is, the voltage VEL increases with time even at the same luminance gradation. For this reason, the higher the allowable voltage Vm at the beginning of driving, the more stable the operation over a long period of time. Therefore, the voltage VX is set so that the voltage VEL is 8V or higher, more preferably 13V or higher.

  This allowable voltage Vm includes not only the increase in resistance of the organic EL element 20 but also a voltage drop due to the power supply wiring 61.

  When the voltage drop is large due to the wiring resistance of the power supply wiring 61, the power consumption of the display panel 1 is remarkably increased. Therefore, the voltage drop of the power supply wiring 61 is particularly preferably set to 1 V or less.

  As a result of considering the pixel width Wp which is the length of one pixel in the row direction, the number of pixels in the row direction (1366), and the extended portion of the lead-out wiring 92 etc. outside the pixel region, the panel size of the display panel 1 is 32. In the case of inches and 40 inches, the total lengths of the routing wires are 706.7 mm and 895.2 mm, respectively. Here, when the line width WL of the power supply wiring 61 and the line width WL of the common wiring 62 are increased, the area of the organic EL layer 20b is structurally reduced, and further, a parasitic capacitance with other wirings is generated, resulting in further voltage drop. Therefore, it is desirable to suppress the width WL of the power supply wiring 61 and the line width WL of the common wiring 62 to one fifth or less of the pixel width Wp.

Considering this, when the panel size of the display panel 1 is 32 inches and 40 inches, the width WL is within 34 μm and 44 μm, respectively. In addition, the maximum film thickness Hmax of the power supply wiring 61 and the common wiring 62 is 1.5 times the minimum processing dimension 4 μm of the transistors 21 to 23, that is, 6 μm in consideration of the aspect ratio. Thus the maximum cross-sectional area Smax of the feed interconnection 61 and common interconnection 62 is 32-inch 40-inch respectively 204Myuemu ^2, a 264μm ^2.

  For such a 32-inch display panel 1, in order to make each maximum voltage drop of the power supply wiring 61 and the common wiring 62 less than 1 V when fully lit so that the maximum current flows, as shown in FIG. The wiring resistivity ρ / cross-sectional area S of each of the power supply wiring 61 and the common wiring 62 needs to be set to 4.7 Ω / cm or less. FIG. 14 shows the correlation between the cross-sectional area of each of the power supply wiring 61 and the common wiring 62 of the 32-inch display panel 1 and the current density. Note that the resistivity allowed at the maximum cross-sectional area Smax of the power supply wiring 61 and the common wiring 62 is 9.6 μΩcm at 32 inches and 6.4 μΩcm at 40 inches.

  For the 40-inch display panel 1, in order to set the maximum voltage drop of the power supply wiring 61 and the common wiring 62 to 1 V or less when all lights up so that the maximum current flows, as shown in FIG. The wiring resistivity ρ / cross-sectional area S of each of the wiring 61 and the common wiring 62 needs to be set to 2.4 Ω / cm or less. FIG. 16 shows the correlation between the cross-sectional area of each of the power supply wiring 61 and the common wiring 62 of the 40-inch display panel 1 and the current density.

The failure life MTF that does not operate due to the failure of the power supply wiring 61 and the common wiring 62 satisfies the following formula (2).
MTF = A exp (Ea / K _b T) / ρJ ² (2)

Ea is the activation energy, K _b T = 8.617 × 10 ⁻⁵ eV, ρ is the resistivity of the power supply wiring 61 and the common wiring 62, and J is the current density.

The failure life MTF of the power supply wiring 61 and the common wiring 62 is limited by an increase in resistivity or electromigration. When the power supply wiring 61 and the common wiring 62 are set to Al (Al alone or an alloy such as AlTi or AlNd) and the MTF is calculated at an operating temperature of 85 ° C. for 10,000 hours, the current density J is 2.1 × 10 ⁴ A / It is necessary to make it cm ² or less. Similarly, when the power supply wiring 61 and the common wiring 62 are set to Cu, the power supply wiring 61 and the common wiring 62 need to be 2.8 × 10 ⁶ A / cm ² or less. It is assumed that materials other than Al in the Al alloy have a lower resistivity than Al.

In consideration of these points, in the 32-inch display panel 1, the cross-sectional areas of the Al-based power supply wiring 61 and the common wiring 62 are such that the power supply wiring 61 and the common wiring 62 do not fail in 10,000 hours in the fully lit state. S is required to be 57 μm ² or more from FIG. 14, and similarly, the cross sectional areas S of the Cu power supply wiring 61 and the common wiring 62 are 0.43 μm ² or more from FIG.

In the 40-inch display panel 1, the cross-sectional areas S of the Al-based power supply wiring 61 and the common wiring 62 so that the power supply wiring 61 and the common wiring 62 do not break down in 10,000 hours in the full lighting state are 92 μm from FIG. requires ² or more, as well as the sectional area S of the feed interconnection 61 and common interconnection 62 of Cu, it is necessary from FIG. 16 0.69 .mu.m ² or more.

Assuming that the Al-based power supply wiring 61 and the common wiring 62 have an Al-based resistivity of 4.00 μΩcm, the 32-inch display panel 1 has a wiring resistivity ρ / cross-sectional area S of 4.7 Ω / cm or less as described above. Therefore, the minimum cross-sectional area Smin is 85.1 μm ² . At this time, since the wiring width WL of the power supply wiring 61 and the common wiring 62 is within 34 μm as described above, the minimum film thickness Hmin of the power supply wiring 61 and the common wiring 62 is 2.50 μm.

Further, in the 40-inch display panel 1 with the Al-based power supply wiring 61 and the common wiring 62, the wiring resistivity ρ / cross-sectional area S is 2.4 Ω / cm or less as described above, so the minimum cross-sectional area Smin is 167 μm ² . At this time, since the wiring width WL of the power supply wiring 61 and the common wiring 62 is within 44 μm as described above, the minimum film thickness Hmin of the power supply wiring 61 and the common wiring 62 is 3.80 μm.

In the Cu power supply wiring 61 and the common wiring 62, if the Cu resistivity is 2.10 μΩcm, the 32-inch display panel 1 has the wiring resistivity ρ / cross-sectional area S of 4.7 Ω / cm or less as described above. The minimum cross-sectional area Smin is 44.7 μm ² . At this time, since the wiring width WL of the power supply wiring 61 and the common wiring 62 is within 34 μm as described above, the minimum film thickness Hmin of the power supply wiring 61 and the common wiring 62 is 1.31 μm.

In addition, in the 40-inch display panel 1 of the Cu power supply wiring 61 and the common wiring 62, the wiring resistivity ρ / cross-sectional area S is 2.4Ω / cm or less as described above, so the minimum cross-sectional area Smin is 87.5 μm ^2. . At this time, since the wiring width WL of the power supply wiring 61 and the common wiring 62 is within 44 μm as described above, the minimum film thickness Hmin of the power supply wiring 61 and the common wiring 62 is 1.99 μm.

  From the above, in order to operate the display panel 1 normally and with low power consumption, it is preferable to set the voltage drop in the power supply wiring 61 and the common wiring 62 to 1 V or less. When the wiring 61 and the common wiring 62 are Al-based 32-inch panels, the film thickness H is 2.50 μm to 6 μm, the width WL is 14.1 μm to 34.0 μm, and the resistivity is 4.0 μΩcm to 9.6 μΩcm. In a 40-inch panel in which the wiring 61 and the common wiring 62 are Al-based, the film thickness H is 3.80 μm to 6 μm, the width WL is 27.8 μm to 44.0 μm, and the resistivity is 4.0 μΩcm to 9.6 μΩcm.

  In general, in the case of the Al-based power supply wiring 61 and the common wiring 62, the film thickness H is 2.50 μm to 6 μm, the width WL is 14.1 μm to 44.0 μm, and the resistivity is 4.0 μΩcm to 9.6 μΩcm.

  Similarly, in a 32-inch panel in which the power supply wiring 61 and the common wiring 62 are Cu, the film thickness H is 1.31 μm to 6 μm, the width WL is 7.45 μm to 34 μm, and the resistivity is 2.1 μΩcm to 9.6 μΩcm. In a 40-inch panel in which the power supply wiring 61 and the common wiring 62 are Cu, the film thickness H is 1.99 μm to 6 μm, the width WL is 14.6 μm to 44.0 μm, and the resistivity is 2.1 μΩcm to 9.6 μΩcm.

  In general, in the case of the Cu power supply wiring 61 and the common wiring 62, the film thickness H is 1.31 μm to 6 μm, the width WL is 7.45 μm to 44 μm, and the resistivity is 2.1 μΩcm to 9.6 μΩcm.

  Therefore, when Al-based material or Cu is applied as the power supply wiring 61 and the common wiring 62, the power supply wiring 61 and the common wiring 62 of the display panel 1 have a film thickness H of 1.31 μm to 6 μm and a width WL of 7.45 μm. 44 μm and resistivity becomes 2.1 μΩcm to 9.6 μΩcm.

〔effect〕
As described above, the magnitudes of the currents flowing through the supply lines Z _{1 to} Z _m are the sum of the magnitudes of the drive currents flowing through the 3 × n organic EL elements 20 connected to the supply lines Z _i in one row. Therefore, when the selection period for driving a moving image with the number of pixels equal to or higher than VGA (Video Graphics Array: display resolution of 640 × 480 size) is set, the parasitic capacitance of each of the supply lines Z _{1 to} Z _m increases. In other words, in the wiring composed of the thin film constituting the gate electrode or the source / drain electrodes of the thin film transistors such as the transistors 21 to 23, a resistance is required to flow the write current (that is, the drive current) to the 3 × n organic EL elements 20. too high.

However, in this embodiment, the power supply wirings 61 and 61 connected to the supply lines Z _{1 to} Z _m by a thick film layer different from the gate electrode, the source, and the drain electrode of the thin film transistors of the subpixels P _{1,1 to} P _{m, n.} ,... Is reduced, so that the voltage drop due to each of the power supply wirings 61, 61,... Is reduced, and even in a short selection period, a sufficient write current (drawing current) can flow without delay.

  Further, since the resistance of the power supply wirings 61, 61, ... is reduced by increasing the thickness of the power supply wirings 61, 61, ..., the width of the power supply wirings 61, 61, ... can be reduced. Therefore, in the case of bottom emission, the decrease in pixel aperture ratio can be minimized.

Similarly, the magnitude of the drive current flowing through the common line 62 during the light emission period is the same as the magnitude of the write current (drawing current) flowing through the power supply line 61 during the selection period, but the common line 62 includes the subpixel P _{1. , 1 to} P _{m, n} , the conductive layer different from the conductive layer constituting the gate electrode, source, and drain electrode of the thin film transistor is used, so that the thickness of the common wiring 62 can be reduced. can do.

  Further, by making all the common wirings 62 conductive with the conductive sealing substrate 80, it becomes possible to further reduce the resistance of the entire system of the common wiring 62 and the sealing substrate 80, and the common wiring 62. -Since it is only necessary to consider the resistivity and the like of the entire system of the sealing substrate 80, the strict design conditions for the film thickness H and the width WL of the common wiring 62 as described above are eased, and the display panel 1 is easier to manufacture. Become.

  Furthermore, by providing the conductive sealing substrate 80, the voltage of the counter electrode 20c can be made uniform in the plane even when the counter electrode 20c itself is thinned to have a higher resistance. Therefore, even if the same potential is applied to all the subpixel electrodes 20a, the light emission intensity of any organic EL layer 20b becomes substantially equal, and the in-plane light emission intensity can be made uniform.

  In the display panel 1 of the two driving methods described above, in the display panel 1, the power supply wirings 61, 61,... Are the lead wiring 92 on the second peripheral edge of the insulating substrate 2, the terminal portion. Since the potential is equalized by the clock signal from the external oscillation circuit via the terminal 92d and the terminal portion 92e, it is possible to quickly supply the current from the organic EL elements 20, 20,.

Incidentally, the first and second counter electrodes 20c of the EL display panel 1, signal lines _{Yr 1, Yg 1, Yb 1} ~Yr n, Yg n, are arranged so as not to overlap with Yb _n in plan view since the counter electrode 20c and the signal lines line _{Yr 1, Yg 1, Yb 1} ~Yr n, Yg n, the parasitic capacitance between the Yb _n have extremely small as compared with the case of overlap. Therefore, even a minute current required to write current to emit each organic EL element 20, respectively, can quickly charge the parasitic capacitance of each signal line lines _{Yr j, Yg j, Yb j} , signal lines line Yr ₁ without _{delay, Yg 1, Yb 1 ~Yr n} , Yg n, since flows are constant into Yb _n, of the driving transistor 23 gate - quickly state in which the drive current flows potential between the source Can be.

[Second Embodiment]
A display panel 1 according to the second embodiment will be described with reference to FIGS. In addition, about the display panel 1 in 2nd Embodiment, the same code | symbol is attached | subjected to the part same as any part of the display panel 1 in 1st Embodiment, and description about the same part is carried out. Omitted.

[Planar layout of display panel]
FIG. 17 is a schematic plan view showing the wiring structure of the display panel in the second embodiment. FIG. 17 shows a state where the sealing substrate 80 is removed. In this display panel 1 as well, in the same manner as in the first embodiment, one pixel pixel 3 is arranged in a horizontal direction with one dot red sub-pixel Pr emitting red light and one dot green sub-light emitting green light. It consists of a pixel Pg and a single blue sub-pixel Pb that emits blue light. Such pixels 3 are arranged in a matrix on the insulating substrate 2.

  Specifically, focusing on the vertical arrangement, a plurality of red subpixels Pr are arranged in a line along the vertical direction (column direction), and a plurality of green subpixels Pg are arranged in a line along the vertical direction. Blue subpixels Pb are arranged in a line along the vertical direction. Focusing on the arrangement in the horizontal direction (row direction), the red subpixel Pr, the green subpixel, which are repeatedly arranged in the order of the red subpixel Pr, the green subpixel Pg, and the blue subpixel Pb, are arranged in the horizontal direction. A combination of Pg and blue subpixel Pb is pixel 3.

  In the following description, the sub-pixel P represents an arbitrary sub-pixel among the red sub-pixel Pr, the green sub-pixel Pg, and the blue sub-pixel Pb, and the description of the sub-pixel P is a red sub-pixel Pr and a green sub-pixel. This applies to both the pixel Pg and the blue subpixel Pb.

  Further, the signal line Yr is provided at one end in the horizontal direction of the red subpixel Pr, the signal line Yg is provided at one end in the horizontal direction of the green subpixel Pg, and the signal line Yb is provided at one end in the horizontal direction of the blue subpixel Pb. It extends along the vertical direction.

  Here, the signal line Yr supplies a signal to all the red subpixels Pr of the pixels 3 arranged in the vertical direction, and the signal line Yg applies to all the green subpixels Pg of the pixels 3 arranged in the vertical direction. The signal line Yb supplies a signal to all the blue subpixels Pb of the pixels 3 arranged in the vertical direction.

  In parallel with the signal lines Yr, Yg, Yb, a plurality of power supply wirings 61 and a plurality of common wirings 62 alternately extend to one end side of the subpixel P.

  A plurality of scanning lines X extend along the horizontal direction, and a plurality of supply lines Z are provided in parallel to the scanning lines X. One scanning line X and one supply line Z are provided for three groups of pixels in one row along the horizontal direction. Here, the scanning line X and the supply line Z supply signals to all the sub-pixels Pr, Pg, and Pb of the pixels 3 arranged in the horizontal direction. The supply line Z extending in the horizontal direction and the power supply wiring 61 extending in the vertical direction are electrically connected.

  Although not shown in FIG. 17, subpixel electrodes 20 a that are anodes of the organic EL elements 20 are respectively provided at the positions of the subpixels Pr, Pg, and Pb that are shown in a rectangular shape that is elongated in the horizontal direction. Is provided. A plurality of subpixel electrodes 20 a are arranged in a line along the vertical direction between the power supply wiring 61 and the adjacent common wiring 62.

  Here, if m and n are integers of 2 or more, and the pixel 3 is arranged in m pixels along the vertical direction and n pixels along the horizontal direction, the subpixel electrode 20a is subpixel along the vertical direction. The same number (3 × n) of the subpixels as one row is arranged in the horizontal direction by the same number m as the number of one column.

[Sub-pixel circuit configuration]
Next, as for the circuit configuration of the subpixels Pr, Pg, and Pb, as shown in the equivalent circuit diagram of FIG. 18, all the subpixels Pr, Pg, and Pb are configured in the same manner. An organic EL element 20, a switch transistor 21, a holding transistor 22, a driving transistor 23, and a capacitor 24 are provided in Pg and Pb.

  As can be seen by comparing FIG. 2 which is an equivalent circuit diagram in the first embodiment and FIG. 18, in the second embodiment, the circuit configuration is equivalent except that the selection wiring 60 is not provided. Since there is, explanation is omitted.

[Plane layout of pixels]
A planar layout of the pixel 3 will be described with reference to FIG. FIG. 19 is a plan view showing the electrodes of the red subpixel Pr and the green subpixel Pg, but the same applies to the blue subpixel Pb. Further, in order to make the drawing easy to see, illustration of the subpixel electrode 20a, the counter electrode 20c, and the sealing substrate 80 of the organic EL element 20 is omitted.

  As shown in FIG. 19, the driving transistor 23 and the switch transistor 21 are arranged along the power supply wiring 61 and the common wiring 62 in a plan view, and the holding transistor 22 is a corner portion of the subpixel P adjacent to the scanning line X. Is arranged. The drain 22d of the holding transistor 22 and the drain 23d of the driving transistor 23 are integrally formed with the supply line Z. The supply line Z and the power supply wiring 61 are electrically connected through a contact hole 71.

  Further, the capacitor 24 is arranged in the subpixel P along the power supply wiring 61, the common wiring 62, or the supply line Z. The source 21s of the switch transistor 21 is connected to the signal line Yr in the red subpixel Pr, connected to the signal line Yg in the green subpixel Pg, and connected to the signal line Yb in the blue subpixel Pb. Yes.

[Layer structure of display panel]
The layer structure of the display panel 1 will be described with reference to FIGS. Here, FIG. 20 is a cross-sectional view taken in the direction of the arrow of the insulating substrate 2 along the plane XX-XX shown in FIG.

  The display panel 1 is obtained by laminating various layers on an insulating substrate 2 having optical transparency. The insulating substrate 2 is provided in the form of a flexible sheet or is provided in the form of a rigid plate.

  Next, regarding the layer structures of the transistors 21 to 23, the capacitor 24, the organic EL element 20, and the like, the position of the contact hole 64 can be understood by comparing FIG. 19 with FIGS. 3 to 5 of the first embodiment. The signal line Y, the scanning line X, and the supply line Z are basically the same in structure, although the positional relationship with the transistors 21 to 23 is different. The description will be omitted.

  Also in this embodiment, since the display panel 1 is used as a bottom emission type, that is, the insulating substrate 2 is used as a display surface, a transparent material is used for the gate insulating film 31, the protective insulating film 32, and the planarizing film 33. Is used. A stacked structure from the insulating substrate 2 to the planarizing film 33 is referred to as a transistor array substrate 50.

  As described above, in this embodiment, the plurality of power supply wirings 61 and the plurality of common wirings 62 alternately extend to one end side of the subpixel P in parallel with the signal lines Yr, Yg, Yb. .

  As shown in FIG. 20, the power supply wiring 61 is formed by leaving the subpixel electrodes 20a on the transistor array substrate 50 so as to extend every other subpixel P between the adjacent subpixels P in the vertical direction. It is formed by electrolytic plating, and is formed sufficiently thicker than the signal lines Yr, Yg, Yb, the scanning line X, and the supply line Z. The power supply wiring 61 preferably includes at least one of copper, aluminum, gold, and nickel. A hydrophobic insulating film 53 having water repellency and oil repellency is formed on the surface of the power supply wiring 61. The hydrophobic insulating film 53 is made of a fluororesin electrodeposition coating, and is formed by electrodeposition coating.

  In addition, an insulating line 51 extending in the vertical direction is formed between adjacent subpixels P on the surface of the transistor array substrate 50 where the power supply wiring 61 is not formed, and a common wiring 62 is formed above the insulating line 51. Are stacked. Since the common wiring 62 is formed by a plating method, the common wiring 62 is sufficiently thicker than the signal line Y, the scanning line X, and the supply line Z and protrudes from the surface of the planarization film 33. The common wiring 62 preferably includes at least one of gold, silver, copper, and nickel.

  A liquid repellent conductive layer 54 having water repellency and oil repellency is formed on the surface of the common wiring 62. In the liquid repellent conductive layer 54, the hydrogen atom (H) of the thiol group (—SH) of triazyltrithiol represented by the above chemical formula is reduced and released, and the sulfur atom (S) is oxidized and adsorbed on the surface of the common wiring 62. It is a thing. As described above, a film made of an extremely thin molecular layer in which triazyltrithiol molecules are regularly arranged on the surface of the common wiring 62 is formed.

  A protective film 56 is formed on the counter electrode 20 c of the organic EL element 20. The protective film 56 is an inorganic film or an organic film that covers the counter electrode 20 c other than the tops of the selection wiring 60, the power supply wiring 61, and the common wiring 62. Therefore, deterioration of the counter electrode 20c is prevented by the protective film 56.

  On the counter electrode 20 c that covers the tops of the selection wiring 60, the power supply wiring 61, and the common wiring 62, a flat sealing substrate 80 is attached so as to cover almost the entire surface of the display panel 1. The sealing substrate 80 of this embodiment is the same as the sealing substrate 80 of the first embodiment in its structure and function, and a description thereof will be omitted.

[Driving method of display panel]
In the display panel 1 of the present embodiment, as shown in FIG. 19, the supply line Z extending in the horizontal direction between the subpixels P and the power supply wiring 61 extending in the vertical direction are electrically connected by the contact hole 71. Yes. Therefore, the driving method as shown in FIG. 9 of the first embodiment cannot be used, but the active matrix driving method of the second display panel 1 shown in FIG. 11, that is, a common method using a clock signal. It can be driven using driving. Since this driving method is the same as that described with reference to FIG. 11, the description thereof is omitted here.

[Width, cross-sectional area and resistivity of power supply wiring and common wiring]
The width, cross-sectional area, and resistivity of the power supply wiring and common wiring are also the same as described in the first embodiment, and thus description thereof is omitted.

〔effect〕
Since it has the above structure and function, the display panel 1 which concerns on this embodiment can also exhibit all the effects of the display panel which concerns on the said 1st Embodiment. Further, as a bank line that protrudes from the transistor array substrate 50 and constitutes the organic EL element 20 portion, the selection wiring 60 is not used as in the first embodiment, and the power supply wiring 61 and the common wiring 62 are used. Therefore, the RGB pixel configuration can be made very simple.

  In addition, since the selection wiring 60 is not used, the number of the power supply wiring 61 and the common wiring 62 is 1.5 times that of the display panel 1 of the first embodiment, and the necessary current can be increased. Since the power can be supplied to the common wiring 62 and supplied to the common wiring 62, the resistance of the power supply wiring 61 and the common wiring 62 can be substantially reduced when viewed as a whole.

[Modification 1]
The present invention is not limited to the first and second embodiments described above, and various improvements and design changes may be made without departing from the spirit of the present invention.

  In each of the above embodiments, the transistors 21 to 23 are described as N-channel field effect transistors. The transistors 21 to 23 may be P-channel field effect transistors. In that case, in the circuit configurations of FIGS. 2 and 18, the relationship between the sources 21s, 22s, and 23s of the transistors 21 to 23 and the drains 21d, 22d, and 23d of the transistors 21 to 23 is reversed. For example, when the drive transistor 23 is a P-channel field effect transistor, the drain 23 d of the drive transistor 23 is conducted to the subpixel electrode 20 a of the organic EL element 20, and the source 23 s is conducted to the supply line Z and the power supply wiring 61. To do.

[Modification 2]
In each of the above embodiments, three transistors 21 to 23 are provided for one dot sub-pixel P. However, one or more transistors are provided for one dot sub-pixel P, and active using these transistors. The present invention can be applied to any display panel that can be driven.

[Modification 3]
In the first embodiment, the selection wiring 60 is protruded between the row of green subpixels Pg in the horizontal direction and the blue subpixel Pb. However, a common wiring similar to the common wiring 62 is protruding. It may be configured to be. In that case, the groove 35 is not provided under the common wiring, and the liquid repellent conductive layer similar to the liquid repellent conductive layer 54 is in a state in which the common wiring is insulated from the scanning line X. It is possible to coat the surface and connect the common wiring to the counter electrode 20c.

[Modification 4]
In the above embodiment, the signal line Y is patterned from the gate layer, but the signal line Y may be patterned from the drain layer. In this case, the scanning line X and the supply line Z are patterned from the gate layer, and the signal line Y is higher than the scanning line X and the supply line Z.

[Modification 5]
Moreover, in the said embodiment, although light emission of the organic EL element 20 was radiate | emitted from the board | substrate 2 via the subpixel electrode 20a, it is not restricted to this, A light-reflection metal film in a lower layer and metal oxides, such as ITO, in an upper layer The light of the organic EL element 20 may be emitted from the sealing glass 81 side by using a subpixel electrode 20a on which a film is disposed and using a transparent electrode such as ITO for the conductive layer 82. At this time, the adhesive layer 83 may be thinly coated so as not to lower the transmittance, or may be provided only at a position corresponding to the common wiring 62.

It is the top view which showed the pixel of the display panel in 1st Embodiment. 3 is an equivalent circuit diagram of a subpixel P. FIG. It is the top view which showed the electrode of red subpixel Pr. It is the top view which showed the electrode of the green sub pixel Pg. It is the top view which showed the electrode of the blue sub pixel Pb. It is arrow sectional drawing cut | disconnected in the thickness direction of the insulated substrate along the broken line VI-VI shown by FIGS. FIG. 4 is a cross-sectional view taken along the arrow line VII-VII shown in FIG. 3 cut in the thickness direction of the insulating substrate. It is the schematic plan view which showed the wiring structure of the display panel in 1st Embodiment. 2 is a timing chart for explaining a method of driving the display panel of FIG. 1. It is the schematic plan view which showed the wiring structure of the 2nd display panel. 11 is a timing chart for explaining a method of driving the display panel of FIG. 10. It is a graph which shows the current-voltage characteristic of the drive transistor and organic EL element of each sub pixel. It is a graph which shows the correlation of each maximum voltage drop of the electric power supply wiring and common wiring of 32 inch display panel, and wiring resistivity (rho) / sectional area S. FIG. It is a graph which shows the correlation of each cross-sectional area and electric current density of electric power feeding wiring and common wiring of a 32-inch display panel. It is a graph which shows the correlation of each maximum voltage drop of electric power feeding wiring of a 40-inch display panel, and common wiring, and wiring resistivity (rho) / sectional area S. FIG. It is a graph which shows the correlation of each cross-sectional area and electric current density of electric power feeding wiring and common wiring of a 40-inch display panel. It is the top view which showed the pixel of the display panel in 2nd Embodiment. 3 is an equivalent circuit diagram of a subpixel P. FIG. 3 is a plan view showing electrodes of subpixels P. FIG. FIG. 20 is a cross-sectional view taken along the arrow line XX-XX shown in FIG. 19 cut in the thickness direction of the insulating substrate.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Display panel 2 Insulating substrate 20a Subpixel electrode 20b Organic EL layer 20c Counter electrode 21 Switch transistor 22 Holding transistor 23 Drive transistor 21d, 22d, 23d Drain 21s, 22s, 23s Source 21g, 22g, 23g Gate 61 Power supply wiring 62 Common wiring 80 Sealing substrate 82 Conductive layer P, Pr, Pg, Pb Subpixel

Claims (10)

A substrate,
A plurality of transistors provided on the substrate;
A plurality of wirings formed by a conductive layer different from the gate, source and drain of the plurality of transistors;
A plurality of pixel electrodes arranged on the substrate along the wirings between the wirings;
A light emitting layer formed on each of the pixel electrodes;
A counter electrode coated with the light emitting layer;
A sealing substrate electrically connected to the counter electrode;
A display panel comprising:   The display panel according to claim 1, wherein the plurality of wirings protrude on a surface of the substrate facing the sealing substrate.   The display panel according to claim 1, wherein the counter electrode is continuously coated from the light emitting layer to the plurality of wirings.   The display panel according to claim 3, wherein the counter electrode is electrically connected to the sealing substrate on the plurality of wirings.   The display panel according to claim 1, wherein the sealing substrate is formed with a conductive layer or a conductive material.   6. The display according to claim 1, wherein the plurality of wirings include a common wiring connected to the counter electrode, and the common wiring is electrically connected to the sealing substrate. panel.   The transistor includes a drive transistor in which one of a source and a drain is connected to a pixel electrode, a switch transistor for passing a write current between the source and drain of the drive transistor, and between the source and gate of the drive transistor during a light emission period. The display panel according to claim 1, further comprising a holding transistor that holds a voltage.   The display panel according to claim 7, wherein the plurality of wirings include a power supply wiring connected to the other of the drain and the source of the driving transistor.   The display panel according to claim 7, wherein the plurality of wirings include a selection wiring for selecting the switch transistor.   The display panel according to claim 7, wherein the plurality of wirings have a common wiring connected to the counter electrode.

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