JP2006258635A - Testing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a signal transmission efficiency from a plurality of memories wherein an output signal from a test device is stored to a plurality of operation parts for performing operation processing to the output signal. <P>SOLUTION: This testing device for testing the test device is equipped with the plurality of memories connected to output pins of the test device, for storing the output signal outputted from a corresponding output pin; the plurality of operation parts provided corresponding to the plurality of memories; bus wiring to which the plurality of operation parts and the plurality of memories are connected; a plurality of switches provided between each operation part on the bus wiring; and a switch control part for switching whether the bus wiring is divided into plurally divided bus wiring or not by controlling the plurality of switches. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a test apparatus for testing a device under test such as a semiconductor circuit.

  2. Description of the Related Art Conventionally, a test apparatus for testing a device under test such as a semiconductor circuit is known which includes a plurality of memories for storing output signals output from the device under test in parallel. The memory stores image data output from a plurality of image sensors such as CCDs. The test apparatus determines the quality of the image sensor based on the image data stored in the memory. A conventional test apparatus includes a plurality of arithmetic units corresponding to a plurality of memories. The plurality of memories and the plurality of arithmetic devices are respectively connected via a bus.

  Since related patent documents and the like are not currently recognized, the description thereof is omitted.

  However, when a plurality of memories and a plurality of arithmetic devices are connected to a single bus, a set of memories and arithmetic devices can simultaneously use the buses. Since the plurality of arithmetic units use the bus by time division, for example, the processing speed is slow. For this reason, the device under test could not be efficiently tested.

  Therefore, an object of the present invention is to provide a test apparatus that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

  In order to solve the above-described problems, in the first embodiment of the present invention, a test apparatus for testing a device under test, which is connected to an output pin of the device under test and outputs an output signal output from a corresponding output pin. A plurality of memories to be stored, a plurality of arithmetic units provided corresponding to the plurality of memories, a bus wiring to which the plurality of arithmetic units and the plurality of memories are connected, and each arithmetic unit on the bus wiring A test apparatus is provided that includes a plurality of switches provided in the switch and a switch control unit that switches whether the bus wiring is divided into a plurality of divided bus wirings by controlling the plurality of switches.

  Each calculation unit includes a wiring use detection unit that detects whether another calculation unit is using the divided bus wiring to which the calculation unit is connected, and a wiring use detection unit that connects the divided bus wiring to another When it is determined that the arithmetic unit is not in use, an input / output unit may be provided that exchanges signals with the memory connected to the divided bus wiring.

  The wiring use detection unit detects that the other control unit connected to the divided bus line has not used the divided bus line for a predetermined period, and the switch control unit detects a plurality of switches. Until the at least one connection state is switched, it may be determined that the other arithmetic unit does not use the divided bus wiring. The test apparatus may test a plurality of devices under test, and the switch control unit may divide the bus wiring for each device under test.

  The above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

  Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the scope of claims, and all combinations of features described in the embodiments are included. It is not necessarily essential for the solution of the invention.

  FIG. 1 is a diagram illustrating an example of a configuration of a test apparatus 100 according to an embodiment of the present invention. The test apparatus 100 is an apparatus for testing a device under test (DUT), and includes a plurality of memories (10-1 to 10-4, hereinafter collectively referred to as 10), a bus wiring 20, and a plurality of switches (14-1 to 14-1). 14-4, hereinafter collectively referred to as 14), a plurality of arithmetic units (16-1 to 16-2, hereinafter collectively referred to as 16), an overall control unit 18, and a switch control unit 12.

  The plurality of memories 10 are provided in parallel, each connected to an output pin of the device under test, and receives an output signal output from the corresponding output pin. The device under test is an image sensor such as a CCD, for example, and each memory 10 stores image data output from a corresponding output pin.

  The plurality of arithmetic units 16 are provided in parallel corresponding to the plurality of memories 10. The plurality of arithmetic units 16 and the plurality of memories 10 are connected to the bus wiring 20. The bus wiring 20 exchanges signals between the arithmetic unit 16 and the memory 10. The calculation unit 16 performs predetermined calculation processing on the image data stored in the memory 10 and outputs the result to the overall control unit 18. The overall control unit 18 determines pass / fail of the device under test based on the data received from the calculation unit 16.

  The plurality of switches 14 are provided between the respective arithmetic units 16 on the bus wiring 20 and switch whether or not to transmit data at the position of the bus wiring 20 where each switch 14 is provided. As shown in FIG. 1, the switch 14 may be provided for each arithmetic unit 16 or may be provided for each predetermined number of arithmetic units 16. The switch control unit 12 switches whether to divide the bus wiring 20 into a plurality of divided bus wirings by controlling the plurality of switches 14.

  For example, when the arithmetic unit 16-1 does not access the memory 10 other than the memory 10-1, the switch control unit 12 opens the switch 14-1, short-circuits the other switch 14, and switches the bus wiring 20 Divide at 14-1. Thereby, the arithmetic unit 16-1 can access the memory 10-1 at a desired timing. The arithmetic units 16-2 to 16-4 access the memories 10-2 to 10-4 in a time division manner.

  As described above, when each arithmetic unit 16 does not access the memory 10 other than the predetermined memory 10, the bus wiring 20 is divided so as to separate the arithmetic unit 16 from the other memory 10, thereby The data transfer efficiency from 10 to the arithmetic unit 16 can be improved.

  FIG. 2 is a diagram illustrating an example of the operation of the test apparatus 100. The test apparatus 100 in this example tests two devices under test 200-1 and 200-2. Each device under test 200 outputs a signal to the two memories 10.

  The switch control unit 12 divides the bus wiring 20 for each device under test 200. That is, the bus wiring 20 is divided so as to separate the memories 10 connected to different devices under test 200. In this example, the memory 10-1 and the memory 10-2 are connected to the device under test 200-1, and the memory 10-3 and the memory 10-4 are connected to the device under test 200-2. In this case, the switch control unit 12 short-circuits the switch 14-1 between the memory 10-1 and the memory 10-2 and the switch 14-3 between the memory 10-3 and the memory 10-4. In addition, the switch control unit 12 opens the switch 14-2 between the memory 10-2 and the memory 10-3.

  In addition, the overall control unit 18 calculates the image data stored in the plurality of memories 10 connected to the divided bus lines in one of the calculation units 16 connected to the divided bus lines. You may be allowed to do. In this way, by dividing the bus wiring 20 for each device under test 200, it is not necessary to use each divided bus wiring in a time division manner, and the respective image data output by each device under test 200 is obtained. The data can be transmitted to the arithmetic unit 16 at the transmission speed of the bus wiring 20. Therefore, each device under test 200 can be efficiently tested.

  FIG. 3 is a diagram illustrating an example of the configuration of the calculation unit 16. The calculation unit 16 includes an input / output unit 22, a wiring use detection unit 24, and a calculation circuit 26. The arithmetic circuit 26 is a circuit that performs arithmetic processing on given image data, for example. The input / output unit 22 is provided between the arithmetic circuit 26 and the bus wiring 20 and transmits and receives signals. The wiring use detection unit 24 detects whether or not another calculation unit 16 is using the divided wiring to which the calculation unit 16 is connected. When the wiring use detection unit 24 determines that the other bus unit 16 is not using the divided bus line, the input / output unit 22 transmits a signal to and from the memory 10 connected to the divided bus line. Give and receive.

  Even when a plurality of calculation units 16 are connected to the divided bus wiring, if the calculation speed in the calculation unit 16 is sufficiently higher than the data transmission speed in the bus wiring 20, the divided bus wiring is connected to the divided bus wiring. With respect to each data stored in the plurality of memories 10, a single arithmetic unit 16 can perform arithmetic processing. In this case, the overall control unit 18 causes one calculation unit 16 to perform calculation processing.

  In this case, since the other arithmetic unit 16 does not perform arithmetic processing until the test of the device under test 200 is completed, the wiring use detection unit 24 is configured so that the other arithmetic unit 16 connected to the divided bus wiring is When it is detected that the divided bus wiring is not used for a predetermined period, until the switch control unit 12 switches at least one connection state of the plurality of switches 14, the other arithmetic units 16 are connected to the divided bus. It may be determined that no wiring is used. When the test of each device under test 200 is completed, the switch control unit 12 switches the connection state of the switch 14 in order to test the next device under test 200. That is, by detecting the control state of the switch 14, it can be detected that the test of the device under test 200 has been completed.

  FIG. 4 is a diagram illustrating an example of the configuration of the bus wiring 20 and the switch 14. The bus wiring 20 in this example includes a wiring 32 and a wiring 34 having different signal transmission directions. The wiring 32 transmits a signal from the switch 14-1 to the switch 14-2, and the wiring 34 transmits a signal from the switch 14-2 to the switch 14-1.

  The switch 14 includes an AND circuit 30-1 provided on the wiring 32 and an AND circuit 30-2 provided on the wiring 34. The logical product circuit 30-1 outputs a logical product of the signal transmitted through the wiring 32 and the control signal supplied from the switch control unit 12. Further, the logical product circuit 30-2 outputs a logical product of the signal transmitted through the wiring 34 and the control signal given from the switch control unit 12. The switch control unit 12 outputs an L logic control signal when the switch 14 is opened, and outputs an H logic control signal when the switch 14 is short-circuited.

  In addition, the bus wiring 20 includes OR circuits 28-2, 28-4, and 28-6 for the respective arithmetic units 16. The OR circuit 28-2 is provided on the wiring 32 and superimposes the signal output from the arithmetic unit 16 on the signal transmitted on the wiring 32. The OR circuit 28-4 is provided on the wiring 34 and superimposes the signal output from the arithmetic unit 16 on the signal transmitted on the wiring 34. The OR circuit 28-6 outputs a logical sum of signals transmitted through the wiring 32 and the wiring 34 to the arithmetic unit 16-2.

  In addition, the bus wiring 20 includes a logical sum circuit 28-1, a logical sum circuit 28-3, and a logical sum circuit 28-5 for each memory 10. The OR circuit 28-2 is provided on the wiring 32 and superimposes a signal output from the memory 10 on a signal transmitted on the wiring 32. The OR circuit 28-5 is provided on the wiring 34 and superimposes a signal output from the memory 10 on a signal transmitted on the wiring 34. The OR circuit 28-1 outputs a logical sum of signals transmitted through the wiring 32 and the wiring 34 to the memory 10.

  With such a configuration, a plurality of switches 14 can be easily provided on the bus wiring 20. The bus wiring 20 may further include flip-flops provided at predetermined intervals on the wiring 32 and the wiring 34. For example, a flip-flop may be provided in each of the wiring 32 and the wiring 34 for each switch 14. Each flip-flop is supplied with an operation clock having a predetermined frequency. With such a configuration, the phase shift of the transmission signal due to the transmission delay in the bus wiring 20 can be reduced.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  As is clear from the above, according to the present invention, the bus wiring can be arbitrarily divided and used according to the operation of the test apparatus, so that the efficiency of transmitting the signal stored in the memory can be improved. .

It is a figure which shows an example of a structure of the test apparatus 100 which concerns on embodiment of this invention. 4 is a diagram illustrating an example of the operation of the test apparatus 100. FIG. 3 is a diagram illustrating an example of a configuration of a calculation unit 16. FIG. 2 is a diagram illustrating an example of the configuration of a bus wiring 20 and a switch 14. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Memory, 12 ... Switch control part, 14 ... Switch, 16 ... Operation part, 18 ... General control part, 20 ... Bus wiring, 22 ... Input / output part, 24... Wiring use detection unit, 26... Arithmetic circuit, 28... OR circuit, 30 .. AND circuit, 32 .. wiring, 34. , 200 ... Device under test

Claims (4)

A test apparatus for testing a device under test,
A plurality of memories connected to output pins of the device under test and storing output signals output by the corresponding output pins;
A plurality of arithmetic units provided corresponding to the plurality of memories;
Bus wiring to which the plurality of arithmetic units and the plurality of memories are connected;
On the bus wiring, a plurality of switches provided between the arithmetic units,
A test apparatus comprising: a switch control unit that switches whether to divide the bus wiring into a plurality of divided bus wirings by controlling the plurality of switches. Each said calculation part is
A wiring use detection unit for detecting whether or not the other calculation unit is using the divided bus wiring to which the self is connected;
Input / output for exchanging signals with the memory connected to the divided bus line when the wiring use detection unit determines that the other divided arithmetic unit is not using the divided bus line The test apparatus according to claim 1, further comprising: When the wiring use detection unit detects that the other calculation unit connected to the divided bus line does not use the divided bus line for a predetermined period, the switch control unit The test apparatus according to claim 2, wherein the other calculation unit determines that the divided bus wiring is not used until at least one connection state of the plurality of switches is switched. The test apparatus tests a plurality of the devices under test,
The test apparatus according to claim 1, wherein the switch control unit divides the bus wiring for each device under test.

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