JPS62123571A - Picture signal processor - Google Patents

Abstract

PURPOSE:To process a large quantity of picture information at a high speed by using an image processor to control a display means and a memory where the display picture information is written via a local bus. CONSTITUTION:A host processor 8 gives a command and a parameter to an image processor 9 and the picture information is read out of a picture memory 10 via a main bus 12. Then the picture information is written into a frame memory 11 via a local bus 15 and an access is given to the memory 11 via the bus 15. The picture information one written is read out to undergo the magnification/reduction or revolution, etc. Then the picture information can be written again to another area of the memory 11 via the bus 15. Thus the load of the processor 8 is greatly reduced. Furthermore the using period of the bus 12 is shortend and therefore the processor 8 can give an access to the memory 10 or the memory 11 with high efficiency. As a result, a large quantity of picture information can be processed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image signal processing device that performs processing to enlarge, reduce, or rotate an image from two-dimensional image information.

2. Description of the Related Art Conventionally, this type of device has been applied, for example, to a document/image file system, etc., and as shown in FIG. a large-capacity image memory 1 for storing image information); a CPU 2; reduction hardware 3 for extracting and reducing the stored information in the image memory 1 via the CPU 2; and storing information from the reduction hardware 3. small-capacity frame memory 4 and CR controlled by the CPU.
T controller 5, a CRT 6 that displays the reduced display information taken out from the frame memory 4 by the CRT controller 5 as it is, and an image memory 1. CPU2. The main lot 7 that connects the reduction hardware 3 and the CRT controller 5 is installed.

Problems to be Solved by the Invention However, in such an image signal processing apparatus, since the reduction hardware 3 is used, the reduction ratio is fixed. Further, in the above device, the image information is stored in the frame memory 4 without using the reduction hardware 3, and the image is enlarged or reduced by changing the read address (or clock) by the CRT controller 5 via the CPU 2. Although it is possible,
Since the data on the frame memory 4 does not change, the format is fixed and only simple magnifications (for example, 2x, 3x, 172x, etc.) can be obtained. In addition, in any of the above cases, the main bus 7 must be used when transferring image data from the image memory 1 to the frame memory 4 via the CPU 2, and the main bus 7 must also be used for processing such as enlargement and reduction. have to use the bus. Therefore, the main bus occupancy time becomes longer, and the load on the processor increases, making it difficult to process a large amount of image data at high speed.

Means for Solving the Problems It is an object of the present invention to solve the above-mentioned problems and provide an image signal processing device capable of high-speed processing. An image signal processing device comprising a frame memory for storing at least a part of information in the image memory as display image information, a display means for displaying the display image information in the frame memory, and a control means for controlling both the memories and the display means. The control means includes a host processor and an image processor, and the image processor includes a storage means for storing image information in the image memory read through the main bus, and an enlargement of the read image stored by the storage means. The host processor has processing means for performing reduction or rotation processing, and means for storing processing information from the processing means in a frame memory via a local bus, and has a function of controlling the image processor via the main bus.

Embodiment of the Invention FIG. 2 is a block diagram showing an embodiment of an image signal processing apparatus according to the present invention applied to a document file system.

In FIG. 2, 8 is a host processor that controls the entire system, 9 is an image processor, IO is an image memory, and 11 is a frame memory. These host processor 8, image processor 9, image memory 10, and frame memory 11 are connected to each other via a main bus 12.

13 is a CRT; 14 is a CRT controller for controlling the CRT 13; the CRT controller 14, image processor 9, and frame memory 11 are connected to each other via a local bus 15;

Since the image signal processing device is configured as described above,
Host processor 8 controls image processor 9 and CRT controller 14 via main bus 12, and also controls image memory lO and frame memory 11.
can be accessed.

The image processor 9 can access the image memory 10 via the main bus 12, and can also access the frame memory 11 via the local bus 15.

The image processor 9 receives commands and parameters from the host processor 8 to access the image memory IO or the frame memory 11, and to perform image enlargement, reduction, rotation, or rask operations on image information stored in the image memory 10. etc. The address of the image memory 10 and the address of the frame memory 11 are stored in the memory in the host processor 8, and the image processor 9 uses the address of both the memories 10 and 11 given from the host processor 8 according to the difference in the addresses of the memories 10 and 11. The memories 10 and 11 can be discriminated and an access bus can be selected.

For example, the image processor 9 accesses the image memory 10 via the main bus 12 in response to commands and parameters given from the host processor 8, reads image information therein, performs enlargement processing, and The enlarged image information written to the frame memory 11 is accessed via the frame memory 11 and written into the frame memory ll.
For example, the CRT controller 1 via the local bus 15
4, it can be read out and displayed on CR, T13. Also, for example, the image processor 9 reads image information in the image memory 10 via the main bus 12, writes it into the frame memory 11 via the local bus 15, and then writes the image information into the frame memory 11 via the local bus 15. The image information that has been accessed and written is read out, subjected to processing such as enlargement, reduction, or rotation, and then transferred to the frame memory 1 again via the local bus 15.
It is also possible to write to other areas of 1. As described above, by giving commands and parameters from the host processor 8 to the image processor 9, the image processor 9 reads the image information in the image memory 10 and performs processing such as enlarging, reducing one rotation, and rask operation. Write to frame memory 11. therefore,
The burden on the host processor 8 is significantly reduced. Also,
Since the period of use of the main bus 12 is shortened, the host processor 8 can efficiently access the image memory 10 or the frame memory 11, thus speeding up the processing of large amounts of image information.

A specific example of the configuration of the image processor 9 will be shown below with reference to FIGS. 3 and 4, and details of the enlargement/reduction and rotation processes will be explained.

In FIG. 3, 30 is an S register that stores the inverse number 17M of the set magnification M, 31 is an S register that stores data read out from the image memory 10 or frame memory 11, and 32 is a register for starting sampling for enlargement/reduction. An A register stores the bit address (of the S register 31), and an S register 33 stores the data sampled from the S register 31.

A C register 34 stores an address in the frame memory 11 to which the data (one word) stored in the S register 33 is to be written.

Next, image data reduction processing using such a configuration will be explained with reference to FIG. 5.

First, in step 51, the inverse number 17M of the enlargement/reduction magnification factor M is stored in the S register. Then, step S
At step 2, the sampling start bit address of the S register 31 is stored in the A register.

Next, in step S3, the write start address in the frame memory at which the data stored in the S register is to be written is stored in the C register.

Next, in step S4, the image data in the image memory or frame memory is read out and stored in the -S register. Next, in step S5, the bit indicated by the A register is selected from among the S register data, and the data is shifted into the S register (starting from the MSB). Next, in step S7, the contents of the C register are incremented by one.

Next, in step S7, it is determined whether the C register is overflowing. If there is an overflow, the process advances to step 510. If there is no overflow, the process advances to step S8. In step S8, the A register and the S register are added and the result is stored in the A register. Next, in step S9, it is determined whether the A register has overflowed. If there is an overflow, the process returns to step S4; if not, the process returns to step S5.

In step 510, it is determined whether all words of image data in the image memory or frame memory have been sampled. If the process has ended, the process ends, and if it has not finished, the process advances to step S11. In step 511,
1 is added to the contents of the address register of the memory storing the image data, and the process returns to step S4.

FIG. 4 shows a specific configuration for rotation processing.

4, the difference from the configuration in FIG. 3 is that an intermediate buffer 35 is provided instead of the S register, and each time data is stored in each column in the intermediate buffer 35, a C
The reason is that a register 36 is provided for incrementing the contents of the register by one. The other configurations are the same as those in FIG. 3.

Next, image data rotation processing using such a configuration will be described with reference to FIG. 6.

First, in step S21, the bit address for starting writing to the frame memory is stored in the C register.Next, in step 522, the address of the intermediate buffer is reset. Next, in step 523, the bit address of the S register for starting sampling is stored in the A register.

Next, in step S24, the reciprocal of the magnification M is set to 17M.
is stored in the S register. Next, in step 525, the data read from the image memory or frame memory is stored in the S register. Next, the bit indicated by the A register is selected from among the data in the S register, and the data is manually shifted into the intermediate buffer starting from the MSB.

Next, in step S27, the address of the intermediate buffer is incremented by one. Then, in step S28, A
Add the contents of the S register to the register and save the result to A.
Store in register. Then in step 529 A
Determine whether a register has overflowed.

If there is no overflow, the process returns to step 526, and if there is an overflow, the process proceeds to step 530. In step 530, the contents of the C register are incremented by one. Next, in step 531, it is determined whether the C register has overflowed. If there is no overflow, the process returns to step 523, and if there is an overflow, the process proceeds to step S32.

In step S32, it is determined whether all words of the image data have been sampled. If it has finished, it will finish,
If the process has not ended, the process advances to step S33. Step S
In step S33, a predetermined number is added to the address counter of the memory storing the image data, and the process returns to step S25.

FIG. 7 is a diagram for explaining the concept of generating a read address for a memory storing image data in the case of enlargement or reduction processing. Note that the same applies to the memory into which the read image data is written. In FIG. 7, reference numeral 70 indicates a memory that stores image data, and 71 indicates a reading direction in the memory 70. As shown in Figure 7, first,
The read start address ST is stored in the address register of the memory 70. Next, 1 is added to the address register SRCADOR of the memory 70, and 1 is subtracted from the horizontal image size (word). As a result, one word is read out in the horizontal direction. Then L
Repeat the same operation until becomes 0. This completes the horizontal reading of one word. If L becomes 0,
The horizontal size (word) of the image space is added to the readout start address, and 1 is subtracted from the vertical image size (number of masters) N. The above process is repeated until N becomes 0. When N becomes 0, the work ends.

FIG. 8 shows the procedure for generating read addresses during rotation processing. As shown in FIG. 8, first, a read start address ST is stored in the address register SRCADDR of the memory 70. Next, the horizontal size of the image space is increased by 47,000' from the address register of the memory 70, and 1 is subtracted from the vertical image size N.

This operation is repeated until N becomes 0. When N becomes 0, 1 is added to the readout start address and 1 is subtracted from the horizontal image size. The above operations are repeated until L becomes O, and when L becomes O, the operation is completed.

As described in detail, according to the present invention, the display means and the memory for writing image information for display are controlled by the image processor via the local bus, so that the main bus and host processor can be used extremely efficiently. can be used to process large amounts of image information at high speed.

Further, when enlarging/reducing an image, by using a DDA method using the reciprocal of the magnification, the image can be enlarged/reduced without giving an unnatural impression.

[Brief Description of the Drawings] Fig. 1 is a block diagram of a conventional image signal processing device, Fig. 2 is a block diagram showing an embodiment of an image signal processing device according to the present invention, and Figs. 3 and 4 are A diagram showing an example of a specific working procedure of an image processor. Figure 7 is a diagram to explain the concept of generating a read address for a memory storing image data in the case of enlargement or reduction processing. Figure 8 is a diagram showing a similar example of rotation. FIG. 3 is a diagram for explaining the concept of read address generation during processing. 8... Host processor, 9... Image processor, IO... Image memory, 11... Frame memory, 12... Main bus, 13...CRT. 14...CRT controller, 15...
・Local bus. Fig. 1 Fig. 2

Claims (1)

[Scope of Claims] An image memory for storing image information, a frame memory for storing at least part of the information in the image memory as display image information, a display means for displaying the display image information in the frame memory, In an image signal processing device having both memories and a control means for controlling the display means, the control means has an image processor constituted by a host processor and firmware, and the image processor is connected to the image processor via a main bus. a storage means for storing read image information in the image memory; a processing means for enlarging, reducing or rotating the read image stored by the storage means using a reciprocal of a magnification as a coefficient; An image signal processing device comprising means for storing processing information in the frame memory via a local bus, and wherein the host processor has a function of controlling the image processor via a main bus.