JP2003021665A - Test circuit for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test circuit for a semiconductor integrated circuit having an efficient test mode without requiring much cost, capable of easily observing a signal of a signal wire inside the semiconductor integrated circuit by controlling generation of a connection control signal from the outside. SOLUTION: This test circuit for the semiconductor integrated circuit is equipped with a control signal generation part 11 for receiving a test mode setting signal 15 from the outside, and outputting a test bus connection control signal 16 corresponding to the test mode setting signal 15, a test bus 20 for transferring data at the test mode time, an IQ cell 30 connected to the test bus 20, a connection control circuit 12 for connecting the test bus 20 to the signal wire 14 corresponding to the test bus connection control signal 16, control wires 13a, 13b for connecting the test bus 20 to the signal wire 14 through the connection control circuit 12, and a PAD 40 connected to the IO cell 30, for connecting an external function block or the like.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit for a semiconductor integrated circuit, and more particularly, it has an efficient test mode, and an additional circuit for the test mode does not deteriorate the performance of the semiconductor integrated circuit during normal operation and is externally connected. The present invention relates to a test circuit for a semiconductor integrated circuit that can easily observe a signal on a signal line inside the semiconductor integrated circuit by controlling the generation of a connection control signal.

[0002]

2. Description of the Related Art Conventionally, a semiconductor integrated circuit has a ROM (Read Only Memory) when the rule is not so large.
Except for special circuits such as y), it was possible to test relatively easily without adding a special test circuit.

For example, ROM, RAM (Random Access)
Memory), instruction register, instruction decoder, AUL input register, ALU, ALU output register, data bus buffer, and CPU internal bus is included in the CPU itself.
One semiconductor integrated circuit, which externally executes an instruction to the instruction register via the data bus buffer and the CPU internal bus, and outputs the execution operation to the outside via the data bus buffer. Then, the method of observing was done relatively well.

[0004]

However, in the conventional test circuit for a semiconductor integrated circuit, when the semiconductor integrated circuit is a large functional block inside, for example, when the semiconductor integrated circuit is a CPU, its internal operation is performed. It cannot be directly observed from outside the semiconductor integrated circuit. Therefore, there is a problem that it is difficult to sufficiently test the internal operation, and the observability of the test result is significantly and impaired.

Further, there is a method in which a signal line in the semiconductor integrated circuit is connected to a test bus by using a test dedicated register and a test mode setting signal stored in the test dedicated register to test the signal line. There is a problem in that the provision of a test-dedicated register adds cost.

Therefore, an object of the present invention is to have a test mode that is inexpensive and efficient, and the additional circuit for testing does not deteriorate the performance of the semiconductor integrated circuit during normal operation.
It is an object of the present invention to provide a test circuit for a semiconductor integrated circuit that can easily observe a signal on a signal line inside the semiconductor integrated circuit by controlling the generation of a connection control signal from the outside.

[0007]

In order to solve the above problems, a test circuit for a semiconductor integrated circuit according to the present invention receives a test mode setting signal and sends a test bus connection control signal in accordance with the test mode setting signal. A control signal generating means for outputting, a test bus for transferring data in the test mode, an IO (Input / Output) cell connected to the test bus for inputting and outputting data to and from the outside, and an output from the control signal generating means. A control circuit that connects the test bus and a signal line to which data is transferred inside the semiconductor integrated circuit in accordance with the test bus connection control signal, and the control circuit controls the test bus and the signal line. The control signal generating means connected by a line is a storage means provided inside the semiconductor integrated circuit, and stores a test bus connection control signal in advance.

The control signal generating means is a register or a RAM (Random A) provided inside the semiconductor integrated circuit.
It is preferable that the test bus connection control signal is stored in advance. At this time, the test mode setting signal may be the address of the control signal generating means in which the test bus connection control signal is stored.

Further, the control line is preferably arranged at a position orthogonal to the test bus.

Further, it is preferable that the input timing of the test mode setting signal is controlled by the system clock of the semiconductor integrated circuit.

Since the connection control circuit connects the test bus and the signal line with the control line, and the test bus connection control signal is stored in advance in the control signal generating means which is a storage means provided inside the semiconductor integrated circuit, the cost is reduced. It has an efficient and efficient test mode, and an additional circuit for testing does not deteriorate the performance of the semiconductor integrated circuit during normal operation, and controls the generation of connection control signals from the outside to control the signals inside the semiconductor integrated circuit. The signal on the line can be easily observed.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a test circuit for a semiconductor integrated circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a semiconductor integrated circuit including a test circuit of the present invention. In FIG. 1, a semiconductor integrated circuit including a test circuit of the present invention is an IC (Integrated Circuit).
a control signal generator 11 provided inside the cuit) 10 for receiving a test mode setting signal 15 from the outside of the IC 10 and outputting a test bus connection control signal 16 in response to the test mode setting signal 15; A test bus 20 that transfers data in the mode, and an IO (Input / Outpu) that is connected to the test bus 20 and that inputs and outputs data to and from the outside.
t) The cell 30 and the test bus connection control signal 16 provided inside the IC 10 and output from the control signal generator 11
According to the connection control circuit 12 for connecting the test bus 20 and the signal line 14 to which data is transferred inside the IC 10.
And control lines 13a and 13b connecting the test bus 20 and the signal line 14 via the connection control circuit 12, and the IO cell 3
PA connected to 0 to connect external function blocks, etc.
And D40.

Here, the control signal generating section 11 includes an IC 10
Is a storage medium provided inside and stores the test bus connection control signal 16 in advance.

In FIG. 1, when the test mode setting signal 15 given from the outside becomes active, the control signal generator 11 outputs the test bus connection control signal 16 as active and outputs the connection control circuit 12 to the test bus. 20 and the signal line 14 which is an internal bus. Thereby, from the outside of the IC 10, the IO cell 30, the test bus 20, the control line 13a, the connection control circuit 12, the control line 13 are provided.
It is possible to directly observe the signal line (internal bus) 14 through the route of b and the signal line (internal bus) 14. Also,
It is also possible to directly set an instruction from the outside to each functional block inside the IC 10 connected to the signal line (internal bus) 14 using this path. During normal operation, the test mode setting signal 15 is deactivated, the test bus connection control signal 16 is deactivated from the control signal generator 11, and the connection control circuit 12 connects the signal line (internal bus) 14 and the test bus 20. To cancel.

Here, the test bus connection control signal 16 is stored in the control signal generator 11, and the test mode setting signal 15 is set to the address of the control signal generator 11 in which the test bus connection control signal 16 is stored. Can be

By connecting the signal line 14 to be observed in advance to the test bus 20 via the connection control circuit 12,
It became possible to observe each signal.

Further, by including the test circuit in the circuit of the semiconductor integrated circuit itself, it becomes unnecessary to consider the configuration of the dedicated test circuit at the time of designing.

Further, by using the control lines 13a and 13b, it becomes possible to dynamically change the observation target.

The control line 13a is preferably arranged at a position orthogonal to the test bus 20. This facilitates circuit design and reduces the influence on the placement of other logic.

FIG. 2 is a diagram showing another embodiment of a semiconductor integrated circuit including the test circuit of the present invention. In FIG.
This is a case where the control signal generator 11 of FIG. 1 is a register 51 provided inside the IC 10. Where register 5
1 stores the test bus connection control signal 16 in advance.

FIG. 3 is a diagram showing another embodiment of a semiconductor integrated circuit including the test circuit of the present invention. In FIG.
This is a case where the control signal generator 11 of FIG. 1 is a RAM (Random Access Memory) 61 provided inside the IC 10. Here, the RAM 61 stores the test bus connection control signal 16 in advance.

By pre-storing the test bus connection control signal 16 in the register 51 or the RAM 61 inside the IC 10, the circuit designer can easily monitor the signal without cost. Further, this test need only perform mapping at the time of testing the register 51 and the RAM 61, that is, addressing of the test bus connection control signal 16.

FIG. 4 is a diagram showing another form of a semiconductor integrated circuit including the test circuit of the present invention. In FIG.
This is a case where the test mode setting signal 15 input to the control signal generator 11 is controlled at the timing of the system clock 17 input to the buffer 18.

By controlling the input timing of the test mode setting signal 15 by the system clock 17 of the IC 10, it is possible to observe the definite data at each timing.

[0026]

As described above, according to the test circuit of the semiconductor integrated circuit of the present invention, the connection control circuit connects the test bus and the signal line with the control line, and the memory provided inside the semiconductor integrated circuit. Since the test bus connection control signal is stored in the medium in advance, it has a low-cost and efficient test mode, and the additional circuit for testing does not deteriorate the performance of the semiconductor integrated circuit during normal operation and can be connected from the outside. It has become possible to easily observe the signal on the signal line inside the semiconductor integrated circuit by controlling the generation of the control signal.

That is, each signal can be observed by connecting the signal line to be observed in advance to the test bus via the connection control circuit. Further, by including the test circuit in the circuit of the semiconductor integrated circuit itself, it is not necessary to consider the configuration of the dedicated test circuit at the time of designing. In addition, it became possible to change the observation target dynamically by using the control line. Since the control line is arranged at a position orthogonal to the test bus, the circuit design is facilitated and the influence on the arrangement of other logic can be reduced.

Further, by pre-storing the test bus connection control signal in the register or RAM in the semiconductor integrated circuit, the circuit designer can easily monitor the signal without cost. It was

Further, by controlling the input timing of the test mode setting signal by the system clock of the semiconductor integrated circuit, it becomes possible to observe fixed data at each timing.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor integrated circuit including a test circuit of the present invention.

FIG. 2 is a diagram showing another embodiment of a semiconductor integrated circuit including a test circuit of the present invention.

FIG. 3 is a diagram showing another embodiment of a semiconductor integrated circuit including a test circuit of the present invention.

FIG. 4 is a diagram showing another embodiment of a semiconductor integrated circuit including a test circuit of the present invention.

[Explanation of symbols]

10 IC 11 Control signal generator 12 Connection control circuit 13a, 13b control line 14 signal lines 15 Test mode setting signal 16 Test bus connection control signal 17 system clock 18 buffers 20 test bus 30 IO cells 40 PAD

Claims (6)

[Claims] 1. A control signal generating means for receiving a test mode setting signal and outputting a test bus connection control signal according to the test mode setting signal, a test bus for transferring data in a test mode, and the test bus. An IO (Input / Output) cell that is connected to and that inputs and outputs data to and from the outside; and a test bus connection control signal that is output from the control signal generation means, in accordance with the test bus and the semiconductor integrated circuit. A connection control circuit that connects a signal line to which data is transferred internally, wherein the connection control circuit connects the test bus and the signal line with a control line, and the control signal generation means is the A test circuit for a semiconductor integrated circuit, which is a storage unit provided inside the semiconductor integrated circuit and stores a test bus connection control signal in advance. 2. The semiconductor integrated circuit according to claim 1, wherein the control signal generating means is a register provided inside the semiconductor integrated circuit, and stores a test bus connection control signal in advance. Circuit test circuit. 3. The control signal generating means is a RAM (Random Access Memo) provided inside the semiconductor integrated circuit.
2. The test circuit for a semiconductor integrated circuit according to claim 1, wherein the test circuit connection control signal is stored in advance. 4. The semiconductor integrated circuit according to claim 1, wherein the test mode setting signal is an address of the control signal generating means in which the test bus connection control signal is stored. Test circuit. 5. The control line is arranged at a position orthogonal to the test bus.
5. A test circuit for a semiconductor integrated circuit as described in 4 above. 6. The test circuit for a semiconductor integrated circuit according to claim 1, wherein an input timing of the test mode setting signal is controlled by a system clock of the semiconductor integrated circuit.