JP2006245168A - Manufacturing method of wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a high density wiring board in which micronized wiring patterns are stacked at a low cost with good efficiency. <P>SOLUTION: A negative pattern is formed on the first main surface of a copper matrix 1 using a permanent resist layer 2. A barrier metal layer 3 and copper layers 4-1 and 4-2 are stacked on an exposed surface of the copper matrix 1 by way of the permanent resist layer 2. Then the copper matrix 1 is removed from a second main surface side by selective etching to form a bump 9 of a truncated cone, constituting a single layer wiring board. First and second single layer wiring boards having the same structure are stacked and integrally pressed by way of a pre-preg layer 6. Then the copper matrix 1 is stacked on the second main surface side and a copper panel layer 12 is stacked by way of the pre-preg layer 6, and a wiring pattern is formed on the copper panel layer 12 to form a multilayer wiring board. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method of manufacturing a wiring board, and more particularly to a method of manufacturing a wiring board having conductive bumps for interlayer connection / mounting in a multilayer printed wiring board.

  In recent years, with the miniaturization of electronic devices, miniaturization of wiring patterns on wiring boards on which electronic components such as semiconductor elements are mounted and mounted, or high density with multilayer wiring, and high reliability of circuit functions are required. Sexualization is desired.

  By the way, as a method for forming conductive bumps for interlayer connection / mounting in a multilayer printed circuit board, a method using a conductive paste or a method using etching is known.

  The former forms a conical paste bump group by press-fitting silver paste onto a conductor plate through a printing mask having a plurality of through holes, and then forms a prepreg as a precursor of the insulating plate. Lamination, pressing and penetration are performed, a copper foil is laminated thereon, and a circuit pattern is formed on the copper foil by etching (see Patent Document 1).

  In the latter, a Cu—Ni—Cu three-layer clad material is used as a material, a Cu—Ni layer is selectively etched from one side to form bumps, and a prepreg layer is laminated thereon. Next, this prepreg layer is pressed, and the tip of the bump pattern is penetrated in the thickness direction of the prepreg-based insulator layer. After that, the top portion of the bump tip exposed through is polished and flattened, and a copper foil is laminated and pressed thereon to be integrated, and a circuit pattern is formed on the copper foil by selective etching (Patent Document). 2).

Furthermore, instead of the Cu-Ni-Cu three-layer clad material, the surface of the copper-clad laminate on which the circuit pattern is formed is entirely plated with Ni for an etching barrier, and then a copper panel is plated with a necessary thickness. And a method of forming bumps on the copper panel plating layer by etching is also known.
JP 2003-204162 A JP 2004-327856 A

  Since the method using the conductive paste forms bumps using a printing mask, it is difficult to sufficiently cope with a high-density circuit pattern.

  The method using etching is effective for miniaturization of the circuit pattern. However, since the Cu-Ni-Cu three-layer clad material is used as a material, the cost is increased, and the top of the bump tip is made of copper. There is a problem that it is difficult to tightly bond the foil material, and there are restrictions on the material surface.

  Further, the method of performing Ni and copper panel plating for the etching barrier on the surface of the copper clad laminate on which the circuit pattern is formed is not only mass-produced, but the time required for forming the panel copper plating layer is relatively long. In this case, the variation tends to occur and a problem arises in the multilayering.

  Accordingly, an object of the present invention is to provide a manufacturing method capable of solving the above-described problems and efficiently manufacturing a high-density wiring board in which miniaturized wiring patterns are multilayered at low cost. is there.

In the method for manufacturing a wiring board according to the present invention, the first main surface of the flat metal base material having the first and second main surfaces facing each other includes a bump forming region on the first main surface by a permanent resist layer. Forming a negative pattern of the conductor circuit of
Forming an etching barrier layer on the surface of the metal base material exposed by this step;
Forming the conductor circuit pattern by forming a metal layer by electroplating on the etching barrier layer formed by this step;
Forming a prepreg layer on one main surface of the metal base material including the metal layer and the permanent resist forming the conductor circuit pattern formed by this step;
Forming an etching resist layer on the second main surface of the metal base material on which a prepreg layer is formed by this step, at a position corresponding to a position where a bump of the conductor circuit is to be formed;
Etching of the metal base material is started from the second main surface side where the etching resist layer is formed by this step, and the metal base material is etched until the etching barrier layer formed on the conductor circuit pattern is exposed. Removing and forming columnar bumps;
A step of forming a prepreg layer on the second main surface side of the metal base material on which columnar bumps are formed by this step;
It is characterized by comprising.

The wiring board manufacturing method of the present invention includes a bump forming region by a permanent resist layer on the first main surface of the flat metal base material having the first and second main surfaces facing each other. Forming a negative pattern of the first conductor circuit;
Forming an etching barrier layer on the surface of the metal base material exposed by this step;
Forming the conductor circuit pattern by forming a metal layer by electroplating on the etching barrier layer formed by this step;
Forming a prepreg layer on one main surface of the metal base material including the metal layer and the permanent resist forming the conductor circuit pattern formed by this step;
Forming an etching resist layer on the second main surface of the metal base material on which a prepreg layer is formed by this step, at a position corresponding to a position where a bump of the conductor circuit is to be formed;
Etching of the metal base material is started from the second main surface side where the etching resist layer is formed by this step, and the metal base material is etched until the etching barrier layer formed on the conductor circuit pattern is exposed. Removing and forming columnar bumps;
A step of forming a prepreg layer on the second main surface side of the metal base material on which columnar bumps are formed by this step;
A step of laminating a metal foil on the prepreg layer formed by this step and pressurizing and integrating,
Forming a second conductor circuit pattern including a bump connection region in the metal foil layer formed by this step;
It is characterized by having.

Further, according to the method of manufacturing a wiring board of the present invention, a bump is formed on the first main surface of the flat first metal base material having the first and second main surfaces facing each other by a permanent resist layer. Forming a negative pattern of a conductor circuit including a region;
Forming an etching barrier layer on the surface of the first metal base material exposed by this step;
Forming the conductor circuit pattern by forming a metal layer by electroplating on the etching barrier layer formed by this step;
Forming a first prepreg layer on one principal surface of the first metal base material including the metal layer forming the conductor circuit pattern formed by this step and the permanent resist;
A step of forming a negative pattern of a conductor circuit including a bump formation region on the first main surface of a flat plate-like second metal base material having first and second main surfaces facing each other by a permanent resist layer. When,
Forming an etching barrier layer on the surface of the second metal base material exposed by this step;
Forming the conductor circuit pattern by forming a metal layer by electroplating on the etching barrier layer formed by this step;
In this step, the second metal base material on which the conductor circuit pattern is formed, the first main surface is the first metal base material, and the first main surface is the first prepreg layer. Laminating so as to oppose each other via, and pressurizing and integrating,
An etching resist layer is formed on the second main surface of the first and second metal base materials integrated by this step at a position corresponding to a position where a bump of the conductor circuit is to be formed. Process,
The etching of the metal base material is started from the second main surface side where the etching resist layer is formed by this step, and the metal base material is removed until the etching barrier layer formed on the conductor circuit pattern is exposed. Etching to remove and forming columnar bumps;
Forming a second prepreg layer on the second main surface side of the first and second metal base material on which columnar bumps are formed by this step;
A step of laminating a metal foil on the second prepreg layer formed by this step and pressurizing and integrating,
Forming a second conductor circuit pattern including a bump connection region in the metal foil layer formed by this step;
It is characterized by having.

  Furthermore, in the method for manufacturing a wiring board according to the present invention, the copper base material is a copper or phosphor bronze base material having a thickness of 35 μm to 200 μm, more preferably 70 μm to 150 μm, and forms the conductor circuit pattern. The metal layer is a copper or phosphor bronze layer, and the metal foil is copper or phosphor bronze foil.

  Furthermore, in the method for manufacturing a wiring board according to the present invention, the etching barrier layer is a nickel layer.

  Furthermore, in the method for manufacturing a wiring board according to the present invention, after the step of laminating and integrating the copper foil on the prepreg layer, the copper foil is subjected to surface polishing, followed by copper plating, and a copper panel layer. And a second conductor circuit pattern including the bump connection region is formed on the copper panel layer formed by this step.

  Furthermore, in the method for manufacturing a wiring board according to the present invention, after the step of forming the columnar bumps, the etching resist layer is removed, and the exposed copper bumps and the conductor circuit pattern are formed on the copper layer. The surface is roughened by processing, and then the second prepreg layer is formed.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method which can manufacture efficiently the cheap high-density wiring board by which the refined | miniaturized wiring pattern was multilayered can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to process drawings. 1 to 12 are process diagrams for explaining a method of manufacturing a wiring board according to the present invention, and are cross-sectional views of the wiring board in each process.

  First, a photosensitive permanent resist layer 2 having a thickness of 12.5 μm to 25 μm is applied to one main surface of a copper base material 1 having a thickness of 70 μm to 150 μm as shown in FIG. The photosensitive permanent resist layer 2 is, for example, an epoxy solder resist. The permanent resist layer 2 is exposed by irradiating light through an exposure mask (not shown) corresponding to the circuit pattern, and a circuit pattern to be formed is developed and cured as shown in FIG. An inverted negative pattern is formed.

  Next, as shown in FIG. 3, for example, Ni is electroplated on the surface of the copper base material 1 exposed by removing the permanent resist layer 2 to form an etching barrier metal layer 3.

  Next, as shown in FIG. 4, copper plating layers 4-1 and 4-2 are formed on the etching barrier metal layer 3 by electrolytic plating, and the recesses corresponding to the circuit pattern formed by the permanent resist layer 2 are formed by copper. Filled with plating layers 4-1 and 4-2. Here, the circuit pattern to be formed is formed by copper plating layers 4-1 and 4-2, the copper plating layer 4-1 is a wiring pattern region, and the copper plating layer 4-2 is a bump formation for interlayer connection. It is an area. Here, the minimum pitch of the copper plating layer 4-1 forming the wiring pattern is about 0.3 mm. In this manner, the single-layer wiring board 5-1 on which the wiring pattern is potentially formed is formed. A method of forming a wiring pattern by electrolytic plating using such a permanent resist mask is known as a so-called additive method.

  The exposed surfaces of the copper plating layers 4-1 and 4-2 formed on the single-layer wiring board 5-1 are roughened by surface treatment, and the prepreg layer 6 is formed thereon.

  Next, as shown in FIG. 6, a second single-layer wiring board 5-2 having the same structure as that of the first single-layer wiring board 5-1 is manufactured. It is laminated on the prepreg layer 6 on the single-layer wiring board 5-1. This is pressed and integrated from above and below to form a laminated body 7 with a double-sided copper base material.

  Next, as shown in FIG. 7, etching is performed at a predetermined position on the second main surface of the first and second copper base materials 1 and 1 forming the laminated body 7, that is, at a position where a bump is to be formed. Resist layers 8 and 8 are applied, and the copper base materials 1 and 1 are selectively removed with, for example, an ammonia alkaline etchant, and the etching barrier metal layer 3 on the copper plating layer 4-2 as shown in FIG. The truncated cone-shaped bumps 9 and 9 are formed. Here, the diameter of the bottom of the bumps 9 is 75 to 125 μm.

  Next, as shown in FIG. 9, the etching resist layers 8 and 8 left on the tops of the bumps 9 and 9 and the etching barrier metal layer 3 left on the copper plating layer 4-1 were peeled and exposed. The tops of the bumps 9 and the periphery of the side surfaces and the surface of the copper plating layer 4-1 are roughened by surface treatment.

  Next, as shown in FIG. 10, on the surfaces of the bumps 9 and 9 and the copper plating layer 4-1 formed on the upper and lower surfaces of the laminate 7, a plane having almost the same height as the tops of the bumps 9 and 9 is formed. In this manner, the second prepreg layers 10 and 10 are filled and formed. And after laminating | stacking the copper foil 11 on this 2nd prepreg layer 10 and 10, it integrates with a press and the laminated body 7 'covered with the 2nd prepreg layer 10 and 10 is formed. By this pressing step, the copper foil 11 protrudes from the portion corresponding to the top of the bumps 9 and 9 and does not form a flat surface as a whole.

  Next, as shown in FIG. 11, for example, the surface of the copper foil 11 is etched by SUEP (Super Uniform Etching Process), and then flattened by polishing, and a copper thin film layer is formed thereon by electroless plating. Further, a copper panel plating layer 12 having a thickness necessary for forming the second circuit wiring pattern is formed thereon by electrolytic plating.

  After the etching resist is applied on the copper panel plating layer 12 formed in this way, an exposure mask constituting a negative circuit pattern is formed by exposure and development processes, and the copper panel plating layer 12 is formed through this exposure mask. Are selectively removed by etching to form second circuit wiring patterns 13-1 and 13-2 as shown in FIG. Here, the second circuit wiring pattern 13-1 indicates a wiring pattern region, and the pattern 13-2 is a bump connection region.

  In this way, the wiring substrate 14 having a four-layer structure is obtained.

  According to the embodiment of the present invention described above, since the wiring pattern is formed on the copper base material 1 by the additive method, a pattern having a rectangular cross section in which there is no difference in the finished dimensions of the top and bottom of the pattern. It is possible to form a fine pattern. In addition, by supplying power from the copper base material 1, it is possible to use normal electrolytic plating without using electroless plating as in the conventional additive method. Therefore, it is not necessary to use a special permanent resist material. In addition, it is possible to obtain a wiring pattern having a strong adhesive force with a base material in a short plating time, and to improve production efficiency.

  Further, according to the embodiment of the present invention, even if there is a defective portion in a potential wiring pattern, it can be easily reworked by scraping or applying the permanent resist material.

  Furthermore, the copper base material 1 on which the wiring pattern is formed is a single metal material such as copper or phosphor bronze, and does not have a clad structure, so the cost of the material is low.

  Furthermore, according to the embodiment of the present invention, the thickness of the copper base material 1 is substantially constant, and the etching for bump formation is stopped at the permanent resist 2 and the barrier metal layer 3. Since the bump 9 having a stable diameter can be formed, a fine wiring pattern including the bump can be formed on a relatively thick conductive substrate.

  Furthermore, according to the embodiment of the present invention, since the circuit wiring pattern 4-1 and the bump 9 for interlayer connection can be formed on the same copper base material 1 by the same etching process, high productivity can be obtained. .

  Furthermore, according to the embodiment of the present invention, when manufacturing a multilayered wiring board, the thick copper base materials 1 and 1 are pressed in a state of being laminated on the outermost layer, and thereafter etching for bump formation is performed. Therefore, scratches, dents, and dust adhering during the laminating press do not affect the production yield of the surface pattern.

  Furthermore, according to the embodiment of the present invention, when forming the surface wiring layer of the multilayered wiring board, the bump and the wiring pattern are connected by the copper panel plating that forms the wiring pattern, so that a landless design is possible. Thus, high-density wiring can be achieved.

  Furthermore, when forming the surface wiring layer, the copper foil is laminated and pressed on the surface of the prepreg, and then the copper foil and the prepreg residue (glass fiber and resin) on the top of the bump are completely removed by surface polishing, and electroless on it Because copper plating and electrolytic copper plating (copper panel plating) are performed, there is no influence of surface defects during lamination press, and special treatment is required to maintain the adhesion between the bump top and copper foil do not do.

  Although the present invention has been described above by the embodiments, the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the technical idea described in the claims of the present invention. .

  For example, in the embodiment of the present invention, a multilayer wiring board having a four-layer structure has been described. However, in the present invention, a copper panel layer 12 is formed on a single-layer wiring board 5-1 via a prepreg layer 6, and this copper By forming the surface wiring pattern on the panel layer 12, it can be applied to the case of manufacturing a multilayer wiring board having a two-layer structure.

  Furthermore, according to the present invention, it is also possible to form a multilayer wiring board having an arbitrary number of layers by appropriately combining these.

  In the embodiment of the present invention, the copper base material is used as the substrate. However, the present invention is not limited to copper, and is applicable to the case of using phosphor bronze or other metal base materials.

  Furthermore, in the embodiment of the present invention, the multilayer wiring boards having a four-layer structure are connected to each other by bumps between the upper and lower two-layer wirings, but not all the four-layer wirings are connected to each other. However, for such a requirement, the four-layer wirings can be connected to each other by a conventionally known through hole or conductive paste bump.

It is process drawing which shows embodiment of this invention, and is principal part sectional drawing which shows the state which provided the permanent resist layer in the copper base material surface. It is process drawing which shows embodiment of this invention, and is principal part sectional drawing which shows the state in which the negative pattern was formed with the permanent resist layer. It is process drawing which shows embodiment of this invention, and is principal part sectional drawing which shows the state which provided the nickel plating layer selectively in the copper base material surface in which the negative pattern was formed. FIG. 4 is a process diagram showing an embodiment of the present invention, wherein a copper plating layer constituting a wiring pattern including a bump formation region is selectively provided on a nickel plating layer on a copper base material surface on which a negative pattern is formed, and a first single unit is formed. The principal part sectional drawing which shows the state used as the layer board | substrate. It is process drawing which shows embodiment of this invention, and is principal part sectional drawing which shows the state which laminated | stacked the prepreg layer on the surface of the copper base material in which the wiring pattern was formed. It is process drawing which shows embodiment of this invention, and is principal part sectional drawing which shows the state which laminated | stacked and integrated the 1st and 2nd single layer board | substrate through the prepreg layer, and formed the double-sided copper base material tension laminated body. It is process drawing which shows embodiment of this invention, and is principal part sectional drawing which shows the state which provided the etching resist in the predetermined position of the outer surface copper base material of a laminated body. It is process drawing which shows embodiment of this invention, and is principal part sectional drawing which shows the state which selectively etched away the outer surface copper base material of the laminated body masked with the etching resist. It is process drawing which shows embodiment of this invention, and is principal part sectional drawing which shows the state which roughened the surface of the bump and wiring pattern of a laminated body. It is process drawing which shows embodiment of this invention, and shows the state which laminated | stacked the prepreg layer on the surface by which the bump and wiring pattern of the laminated body were formed, and also laminated and pressed the copper foil on the surface. FIG. It is process drawing which shows embodiment of this invention, and is principal part sectional drawing which shows the state by which the copper panel layer was formed by plating on the copper foil laminated | stacked on the surface of the laminated body. It is process drawing which shows embodiment of this invention, and is principal part sectional drawing which shows the state by which the circuit pattern was formed in the copper panel layer formed in the surface of a laminated body.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Copper base material 2 ... Permanent resist layer 3 ... Laminated body 4-1, 4-2 ... Copper plating layer Plating resist layer 5-1 ... Single layer wiring board 6 ... 1st prepreg layer 7 ... Laminate 7 8 ... Etching resist layer 9 ... Bump 10 ... Second prepreg layer 11 ... Copper foil 12 ... Copper panel plating layer 13-1, 13-2 ... Second circuit wiring pattern 14 ... Wiring substrate having a four-layer structure

Claims (11)

Forming a negative pattern of a first conductor circuit including a bump forming region on the first main surface of a flat metal base material having first and second main surfaces facing each other by a permanent resist layer; When,
Forming an etching barrier layer on the surface of the metal base material exposed by this step;
Forming the conductor circuit pattern by forming a metal layer by electroplating on the etching barrier layer formed by this step;
Forming a prepreg layer on one main surface of the metal base material including the metal layer and the permanent resist forming the conductor circuit pattern formed by this step;
Forming an etching resist layer on the second main surface of the metal base material on which a prepreg layer is formed by this step, at a position corresponding to a position where a bump of the conductor circuit is to be formed;
Etching of the metal base material is started from the second main surface side where the etching resist layer is formed by this step, and the metal base material is etched until the etching barrier layer formed on the conductor circuit pattern is exposed. Removing and forming columnar bumps;
A step of forming a prepreg layer on the second main surface side of the metal base material on which columnar bumps are formed by this step;
A method of manufacturing a wiring board, comprising:   2. The wiring according to claim 1, wherein the metal base material is a copper or phosphor bronze base material having a thickness of 35 μm to 200 μm, and the metal layer forming the conductor circuit pattern is a copper or phosphor bronze layer. A method for manufacturing a substrate.   3. The method of manufacturing a wiring board according to claim 2, wherein the etching barrier layer is a nickel layer. Forming a negative pattern of a first conductor circuit including a bump forming region on the first main surface of a flat metal base material having first and second main surfaces facing each other by a permanent resist layer; When,
Forming an etching barrier layer on the surface of the metal base material exposed by this step;
Forming the conductor circuit pattern by forming a metal layer by electroplating on the etching barrier layer formed by this step;
Forming a prepreg layer on one main surface of the metal base material including the metal layer and the permanent resist forming the conductor circuit pattern formed by this step;
Forming an etching resist layer on the second main surface of the metal base material on which a prepreg layer is formed by this step, at a position corresponding to a position where a bump of the conductor circuit is to be formed;
Etching of the metal base material is started from the second main surface side where the etching resist layer is formed by this step, and the metal base material is etched until the etching barrier layer formed on the conductor circuit pattern is exposed. Removing and forming columnar bumps;
A step of forming a prepreg layer on the second main surface side of the metal base material on which columnar bumps are formed by this step;
A step of laminating a metal foil on the prepreg layer formed by this step and pressurizing and integrating,
Forming a second conductor circuit pattern including a bump connection region in the metal foil layer formed by this step;
A method of manufacturing a wiring board, comprising:   The copper base material is a copper or phosphor bronze base material having a thickness of 35 μm to 200 μm, the metal layer forming the conductor circuit pattern is a copper or phosphor bronze layer, and the metal foil is copper or phosphor bronze foil The method for manufacturing a wiring board according to claim 4, wherein:   6. The method of manufacturing a wiring board according to claim 5, wherein the etching barrier layer is a nickel layer. A step of forming a negative pattern of a conductor circuit including a bump formation region on the first main surface of a flat plate-shaped first metal base material having first and second main surfaces facing each other by a permanent resist layer. When,
Forming an etching barrier layer on the surface of the first metal base material exposed by this step;
Forming the conductor circuit pattern by forming a metal layer by electroplating on the etching barrier layer formed by this step;
Forming a first prepreg layer on one principal surface of the first metal base material including the metal layer forming the conductor circuit pattern formed by this step and the permanent resist;
A step of forming a negative pattern of a conductor circuit including a bump formation region on the first main surface of a flat plate-like second metal base material having first and second main surfaces facing each other by a permanent resist layer. When,
Forming an etching barrier layer on the surface of the second metal base material exposed by this step;
Forming the conductor circuit pattern by forming a metal layer by electroplating on the etching barrier layer formed in this step;
In this step, the second metal base material on which the conductor circuit pattern is formed, the first main surface is the first metal base material, and the first main surface is the first prepreg layer. Laminating so as to oppose each other via, and pressurizing and integrating,
An etching resist layer is formed on the second main surface of the first and second metal base materials integrated by this process at a position corresponding to a position where a bump of the conductor circuit is to be formed. Process,
The etching of the metal base material is started from the second main surface side where the etching resist layer is formed by this step, and the metal base material is removed until the etching barrier layer formed on the conductor circuit pattern is exposed. Etching to remove and forming columnar bumps;
Forming a second prepreg layer on the second main surface side of the first and second metal base material on which columnar bumps are formed by this step;
A step of laminating a metal foil on the second prepreg layer formed by this step and pressurizing and integrating,
Forming a second conductor circuit pattern including a bump connection region in the metal foil layer formed by this step;
A method of manufacturing a wiring board, comprising:   The copper base material is a copper or phosphor bronze base material having a thickness of 35 μm to 200 μm, the metal layer forming the conductor circuit pattern is a copper or phosphor bronze layer, and the metal foil is copper or phosphor bronze foil The method for manufacturing a wiring board according to claim 7.   9. The method of manufacturing a wiring board according to claim 8, wherein the etching barrier layer is a nickel layer.   After the step of laminating and pressing the copper foil on the prepreg layer, the copper foil is subjected to surface polishing, followed by copper plating to form a copper panel layer. The copper formed by this step 10. The method for manufacturing a wiring board according to claim 9, wherein a second conductor circuit pattern including the bump connection region is formed on the panel layer.   After the step of forming the columnar bumps, the etching resist layer is peeled off, the exposed surface of the copper layer forming the columnar bumps and the conductor circuit pattern is roughened, and then, The method for manufacturing a wiring board according to claim 10, wherein a second prepreg layer is formed.

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