US20100147559A1

US20100147559A1 - Carrier used in the manufacture of substrate and method of manufacturing substrate using the carrier

Info

Publication number: US20100147559A1
Application number: US12/382,359
Authority: US
Inventors: Ki Hwan Kim; Jin Yong An; Myung Sam Kang
Original assignee: Samsung Electro Mechanics Co Ltd
Current assignee: Samsung Electro Mechanics Co Ltd
Priority date: 2008-12-17
Filing date: 2009-03-13
Publication date: 2010-06-17
Also published as: JP2010147452A; KR101095211B1; US8677618B2; US20110318480A1; KR20100070051A

Abstract

The invention relates to a carrier used in the manufacture of a substrate and a method of manufacturing a substrate using the carrier, the method including (A) preparing a carrier comprising a releasing layer, and insulating layers and metal layers sequentially disposed on both sides of the releasing layer; (B) patterning the metal layers to form base circuit layers; (C) forming buildup layers on the base circuit layers; (D) executing a routing process to separate the insulating layers from the releasing layer; and (E) forming solder-resist layers on the buildup layers and forming openings in-the solder-resist layers and the insulating layers to expose pads.

Description

CROSS REFERENCE TO RELATED APPLICATION

This application claims the benefit of Korean Patent Application No. 10-2008-0128642, filed Dec. 17, 2008, entitled “A Carrier member for manufacturing a substrate and a fabricating method of substrate using the same”, which is hereby incorporated by reference in its entirety into this application.

BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to a carrier used in the manufacture of a substrate and a method of manufacturing a substrate using the carrier.
2. Description of the Related Art
Generally, a printed circuit board is constructed in a manner such that a board which is composed of various thermosetting synthetic resins is wired at one or both sides thereof with copper foils, IC or electronic devices are arranged and mounted on the board and electrically connected to each other and then the resulting board with the electronic devices mounted thereon is coated with an insulating material.
With an increase in demand for the miniaturization and increased functionality of electronic devices as a result of the development of the electronic industries, printed circuit boards on which the electronic devices are mounted are also required to accommodate high density wiring and to be slim.
Particularly, intensive research into a printed circuit board which is thin and a method of manufacturing the printed circuit board which are designed to reduce a total thickness thereof and thus reduce signal processing time are under vigorous progress.
In a process of manufacturing a thin substrate, a carrier which serves as a support for the thin substrate during the manufacturing process is used.
FIG. 1 shows a cross-sectional view of a conventional carrier which is adapted to be used in manufacture of a thin substrate.
As shown in FIG. 1, the conventional carrier 10 is configured such that a pair of metal bases 12 a and 12 b which includes respective metal barrier layers 14 a and 14 b thereon is attached to each other via an adhesive material 16 disposed therebetween.
In this regard, the pair of metal bases 12 a and 12 b may be made of metals such as copper (Cu), aluminum (Al) or iron (Fe), while the metal barrier layers 14 a and 14 b may be made of titanium (Ti). The metal barrier layers 14 a and 14 b are formed by a dry coating technique such as vacuum deposition, sputtering or ion plating. The adhesive material 16 is disposed on the other side of the metal bases 12 a and 12 b to connect them with each other.
FIGS. 2 to 10 are cross-sectional views sequentially showing a conventional process of manufacturing a thin substrate using the carrier shown in FIG. 1. Referring to the drawings, the process of manufacturing a thin substrate is described below.
First, first plating layers 18 a and 18 b are formed on the metal barrier layers 14 a and 14 b of the carrier 10 (FIG. 2). At this point, the first plating layers 18 a and 18 b may be composed of an electroless plating layer and an electrolytic plating layer.
Subsequently, the first plating layers 18 a and 18 b are patterned to form first circuit layers 20 a and 20 b (FIG. 3).
First insulating layers 22 a and 22 b are disposed thereon (FIG. 4).
Via- holes 24 a and 24 b are formed in the first insulating layers 22 a and 22 b so as to expose the first circuit layers 20 a and 20 b to the outside (FIG. 5).
Second plating layers 26 a and 26 b are formed on the first insulating layers 22 a and 22 b and inner surfaces of the via- holes 24 a and 24 b (FIG. 6). In this regard, each of the second plating layers 26 a and 26 b are composed of an electroless plating layer and an electrolytic plating layer.
The second plating layers 26 a and 26 b are patterned to form second circuit layers 28 a and 28 b (FIG. 7).
Thereafter, a routing process is conducted along routing lines RL, with the result that the pair of metal bases 12 a and 12 b separate from each other (FIG. 8).
The metal bases 12 a and 12 b and the metal barrier layers 14 a and 14 b are removed (FIG. 9). At this point, because the metal bases 12 a and 12 b and the metal barrier layers 14 a and 14 b are made of different materials, they are sequentially removed using different etching solutions.
Finally, solder resist layers 30 a and 30 b are formed on both sides of each of the first insulating layers 22 a and 22 b, and then openings 32 a and 32 b are formed in the solder resist layers 30 a and 30 b to allow the pads to be exposed (FIG. 10).
According to the conventional process, the carrier 10, which serves as a component being removed after completion of manufacturing, is composed of the metal bases 12 a and 12 b and the metal barrier layers 14 a and 14 b. Consequently, the conventional process is problematic in that removal of the metal bases 12 a and 12 b and the metal barrier layers 14 a and 14 b requires at least two kinds of different etching solutions and at least two etching processes.
Additionally, according to the conventional process, since the carrier which is removed after completion of manufacture of a substrate is made of expensive metal, manufacturing costs are increased.

SUMMARY OF THE INVENTION

Accordingly, the present invention has been made keeping in mind the above problems occurring in the related art, and the present invention provides a carrier used in the manufacture of a substrate, which can be easily and expensively produced, and a method of manufacturing a substrate using the carrier.
Furthermore, the present invention provides a carrier used in the manufacture of a substrate, which can be efficiently used by employing the carrier as a part of the substrate, and a method of manufacturing a substrate using the carrier.
In an aspect, the present invention provides a carrier used in the manufacture of a substrate, including: a releasing layer; insulating layers disposed on both sides of the releasing layer; and metal layers disposed on the insulating layers.
The releasing layer may have a smaller length than that of the insulating layers such that the insulating layers are in contact with each other at lateral regions thereof.
The releasing layer may include first and second releasing layers, and which further comprises a reinforcing layer disposed between the first and second releasing layers.
The reinforcing layer may include a double-sided copper clad laminate or a reinforcing and insulating material.
In another aspect, the present invention provides a method of manufacturing a substrate using a carrier, including: (A) preparing a carrier comprising a releasing layer, and insulating layers and metal layers sequentially disposed on both sides of the releasing layer; (B) patterning the metal layers to form base circuit layers; (C) forming buildup layers on the base circuit layers; (D) executing a routing process to separate the insulating layers from the releasing layer; and (E) forming solder resist layers on the buildup layers and forming openings in the solder resist layers and the insulating layers to expose pads.
In (A) preparing the carrier, the releasing layer may have a smaller length than that of the insulating layers such that the insulating layers are in contact with each other at lateral regions thereof.
In (A) preparing the carrier, the releasing layer may include first and second releasing layers, and the carrier may further include a reinforcing layer disposed between the first and second releasing layers.
The reinforcing layer may include a double-sided copper clad laminate or a reinforcing and insulating material.
In (D) executing the routing process, the routing process may be executed along routing lines positioned inside the lateral regions at which the insulating layers are in contact with each other so as to separate the insulating layers from the releasing layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a cross-sectional view of a conventional-carrier;

FIGS. 2 to 10 are cross-sectional views showing a conventional process of manufacturing a thin substrate using the carrier shown in FIG. 1;

FIG. 11 is a cross-sectional view of a carrier used in the manufacture of a substrate according to a first embodiment of the present invention;

FIG. 12 is a cross-sectional view showing a process of manufacturing the carrier shown in FIG. 11;

FIG. 13 is a cross-sectional view of a carrier used in the manufacture of a substrate according to a second embodiment of the present invention;

FIG. 14 is a cross-sectional view showing a process of manufacturing the carrier shown in FIG. 13; and

FIGS. 15 to 21 are cross-sectional views showing a process of manufacturing a substrate using the carrier according to an embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Various advantages and features of the invention will become apparent from the following description of embodiments with reference to the accompanying drawings.
The terms and words used in the present specification and claims should not be interpreted as being limited to typical meanings or dictionary definitions, but should be interpreted as having meanings and concepts relevant to the technical scope of the present invention based on the rule according to which an inventor can appropriately define the concept of the term to best describe the method he or she knows for carrying out the invention.
In the following detailed description, it should be noted that the terms “first”, “second” and the like are not intended to indicate a specific amount, sequence or significance but are intended to differentiate constituent elements. Furthermore, concerning the designations of reference numerals, it should be noted that the same reference numerals are used throughout the different drawings to designate the same or similar components. Also, in the description of the present invention, when it is considered that the detailed description of a related prior art may obscure the gist of the present invention, such a detailed description is omitted.
Hereinafter, embodiments of the present invention will be described in greater detail with reference to the accompanying drawings.
Carrier used in the Manufacture of a Substrate
FIG. 11 is a cross-sectional view of a carrier used in the manufacture of a substrate according to a first embodiment of the present invention, and FIG. 12 is a cross-sectional view showing a process of manufacturing the carrier used in the manufacture of a substrate as shown in FIG. 11. Referring to the drawings, the carrier 100 a for manufacture of a substrate and a method of manufacturing the carrier 100 a, according to this embodiment are described below.
As shown in FIG. 11, the carrier 100 a according to this embodiment includes a releasing layer 112 on both sides of which are formed insulating layers 114 a and 114 b and metal layers 116 a and 116 b.
In this regard, the insulating layers 114 a and 114 b function to offer rigidity to the carrier 110 a and to serve as solder resist layers in a subsequent process of manufacturing the substrate. For example, the insulating layers 114 a and 114 b may be made of ABF, prepreg or insulating material containing glass. More specifically, the present invention provides the carrier 100 a used in the manufacture of a substrate, which includes the insulating layers 114 a and 114 b functioning to offer rigidity and serving as solder resist layers of the substrate, without using expensive metal components which are removed after completion of the manufacturing process as in the related art. Consequently, the present invention provides the carrier 100 a used in the manufacture of a substrate, which enables substantial cost saving.
The releasing layer 112 is intended to allow the insulating layers 114 a and 114 b and the metal layers 116 a and 116 b to be separated from each other. The releasing layer 112 is sized to be of a shorter length than that of the insulating layers 114 a and 114 b, and is disposed between the insulating layers 114 a and 114 b excepting both lateral regions. More specifically, while the regions of the first and second insulating layers 114 a and 114 b at which the releasing layer 112 is formed are not adhered to each other, the remaining lateral regions of the first and second insulating layers 114 a and 114 b at which the releasing layer 112 is not formed are adhered to each other. Thanks to the adoption of this configuration, a subsequent routing process which is conducted along lines positioned inside the remaining lateral regions enables the first and second insulating layers 114 a and 114 b to be easily separated from each other. This process will be described later in greater detail with reference to FIG. 20.
In this regard, the releasing layer 112 may be made of a releasing material using a thin film coating or sputtering process.
As shown in FIG. 12, the carrier used in the manufacture of a substrate according to this embodiment is manufactured in a manner such that the insulating layers 114 a and 114 b and the metal layers 116 a and 116 b are sequentially disposed above both sides of the releasing layer 112 and are then laminated together with the releasing layer 112 using a laminator or a V-press. In other words, since the present invention applies a typical process of manufacturing a CCL to manufacture of the carrier 100 a, the present invention obviates the need for additional equipment for manufacturing the carrier.
FIG. 13 is a cross-sectional view of a carrier used in the manufacture of a substrate according to a second embodiment of the present invention, and FIG. 14 is a cross-sectional view showing a process of manufacturing the carrier used in the manufacture of a substrate as shown in FIG. 13. Referring to the drawings, the carrier 100 b used in the manufacture of a substrate and a method of manufacturing the carrier 100 b, according to this embodiment are described below.
As shown in FIG. 13, the carrier 100 b used in the manufacture of a substrate according to this embodiment includes two releasing layers, that is, a first releasing layer 112 a and a second releasing layer 112 b and a reinforcing layer S disposed between the first and second releasing layers 112 a and 112 b, unlike the carrier 100 a shown in FIG. 11. The remaining components other than these unique components are substantially identical to those of the carrier 100 a used in the manufacture of a substrate shown in FIG. 11, and thus the redundant description thereof is omitted herein.
More specifically, the carrier 100 b used in the manufacture a substrate according to this embodiment is configured such that the releasing layers 112 a and 112 b, insulating layers 114 a and 114 b and metal layers 116 a and 116 b are sequentially disposed on both sides of the reinforcing layer S.
In this embodiment, the reinforcing layer S may be made of any material as long as the material can offer a desired rigidity to the carrier 100 b for manufacture a substrate. Particularly, the reinforcing layer S may be made of any material which is easily cut in a subsequent routing process, has easy availability and lowered cost. For example, the reinforcing layer may be embodied as a double-sided copper clad laminate, as shown in FIG. 14. Although not shown in drawings, a general reinforcing and insulating material may also be used as the reinforcing layer S.
As shown in FIG. 14, the carrier 100 b used in the manufacture of a substrate according to this embodiment is manufactured in a manner such that the releasing layer 112, the insulating layers 114 a and 114 b and the metal layers 116 a and 116 b are sequentially disposed above both sides of the releasing layer 112 and are then laminated using a laminator or a V-press.
Process of Manufacturing a Substrate Using the Carrier
FIGS. 15 to 21 are cross-sectional views showing a process of manufacturing a substrate using the carrier according to an embodiment of the present invention. Referring to the drawings, the process of manufacturing a substrate using the carrier according to this embodiment is described below.
Hereinafter, a process of manufacturing a substrate using the carrier 100 a according to the first embodiment of the present invention as shown in FIGS. 11 and 12 will be described.
First, as shown in FIG. 15, is the preparation of the carrier 100 a, which is configured such that the insulating layers 114 a and 114 b and the metal layers 116 b and 116 b are sequentially laminated on both sides of the releasing layer 112 as shown in FIG. 11.
Subsequently, as shown in FIG. 16, photosensitive resist material is applied onto the metal layers 116 a and 116 b to provide photosensitive resist layers 118 a and 118 b.
At this point, the photosensitive resist layers 118 a and 118 b may be made of typical dry film or positive liquid photo resist (P-LPR) which is composed of a photosensitive (photoresist) film, a Mylar film disposed on a side of the photosensitive film to impart flexibility and a cover-film disposed on the other side of the photosensitive film.
As shown in FIG. 17, the photosensitive resist layers 118 a and 118 b are patterned to form openings A such that the photosensitive resist layers 118 a and 118 b have configurations corresponding to base circuit layers 116 a′ and 116 b′ to be formed later.
At this time, the openings A may be formed in a manner such that the photosensitive resist layers 118 a and 118 b are partially exposed to light through a mask having a predetermined pattern and regions of the photosensitive resist layers 118 a and 118 b which are not exposed to the light are removed using developing solution.
As shown in FIG. 18, regions of the metal layers 116 a and 116 b which are exposed through the openings A are removed through an etching process, and the photosensitive resist layers 118 a and 118 b are peeled off, thus forming the base circuit layers 116 a′ and 116 b′.
The exposed regions of the photosensitive resist layers 118 a and 118 b are peeled off using a peeling solution such as NaOH or KOH. In this context, the peeling off of the photosensitive resist layers occurs as a result of uplifting the photosensitive resist layers 118 a and 118 b which occurs because of the binding of OH⁻ of the peeling solution to the carboxyl group (COOH⁺) of the photosensitive resist layers 118 a and 118 b.
Thereafter, as shown in FIG. 19, buildup layers 122 a and 122 b which include buildup insulating layers 124 a and 124 b and buildup circuit layers 126 a and 126 b are formed.
At this point, the buildup layers 122 a and 122 b may be formed in a manner such that the buildup insulating layers 124 a and 124 b are formed, via-holes for interlayer connection are formed, and plating layers are formed on the buildup insulating layers 124 a and 124 b including inner surfaces of the via-holes and are patterned to provide the buildup circuit layers 126 a and 126 b.
Although each of the buildup layers 122 a and 122 b is shown in FIG. 19 as being composed of a single layered structure for the sake of illustration and explanation, each of the buildup layers 122 a and 122 b may be naturally composed of a multilayered buildup structure which must also be construed as falling within the scope of the present invention.
As shown in FIG. 20, a routing process is conducted along routing lines RL. In this embodiment, the routing process refers to a process of mechanically cutting a workpiece using a routing bit.
In this regard, the routing lines RL are positioned inside the lateral regions at which the first insulating layer 114 a and the second insulating layer 114 b adhere to each other. Therefore, the execution of the routing process along the routing lines RL allows the first and second insulating to be separated from each other by the releasing layer 112.
Finally, as shown in FIG. 21, a solder resist layer 128 is formed on each of the buildup layers 122 a and 122 b, and then openings 130 a and 130 b are formed in the solder resist layer 128 and each of the insulating layers 114 a and 114 b, respectively, to expose pads therethrough.
In this regard, since the base circuit layers 116 a′ and 116 b′ are provided with the insulating layers 114 a and 114 b, respectively, there is no need for formation of additional solder resist layers. In other words, since the insulating layer 114, which has served as a carrier up till this point in a typical process of manufacturing a substrate, serves as the solder resist layer 128 in the present invention, there is no need for a material and a process for formation of the solder resist layer 128, thus reducing manufacturing costs and time.
Meanwhile, the openings 130 a and 130 b may be formed using a machining process such as LDA (Laser Direct Ablation).
Although the process of manufacturing a substrate according to the present invention has been described as being implemented by adopting the carrier 100 a according to the first embodiment, the manufacturing process may also be implemented by adopting the carrier 110 b according to the second embodiment shown in FIGS. 13 and 14. The latter process of manufacturing a substrate will be apparent to the those skilled in the art from the process described with reference to FIGS. 16 to 21, and thus the detailed description thereof is omitted herein.
As described above, according to the present invention, a typical process of manufacturing a CCL is applied to a process of manufacturing a carrier used in the manufacture of a substrate, and thus there is no need for additional equipment for manufacturing the carrier. Additionally, since the carrier is manufactured using inexpensive material that is readily available, costs required to manufacture the carrier are decreased.
Furthermore, according to the present invention, since the releasing process is concurrently implemented by execution of the routing process in the manufacture of a substrate, stress caused by external force is eliminated, thus avoiding distortion of a substrate and obviating an additional releasing process.
In addition, since the insulating layers of the carrier, which are usually used to manufacture a substrate, also serve as solder resist layers of the substrate, portions of the carrier which are otherwise discarded are minimized, thus contributing to cost saving.
In addition, according to the present invention, there is no need for two kinds of etching solutions nor for conducting the etching process for removal of the carrier twice.
Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that the carrier used in the manufacture of a substrate and the method of manufacturing a substrate using the carrier are not limited thereto and various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. Accordingly, such modifications, additions and substitutions should also be understood to fall within the scope of the present invention.

Claims

1. A carrier used in the manufacture of a substrate, comprising:

a releasing layer;

insulating layers disposed on both sides of the releasing layer; and

metal layers disposed on the insulating layers.

2. The carrier according to claim 1, wherein the releasing layer has a smaller length than that of the insulating layers such that the insulating layers are in contact with each other at lateral regions thereof.

3. The carrier according to claim 1, wherein the releasing layer includes first and second releasing layers, and which further comprises a reinforcing layer disposed between the first and second releasing layers.

4. The carrier according to claim 3, wherein the reinforcing layer comprises a double-sided copper clad laminate or a reinforcing and insulating material.

5. A method of manufacturing a substrate using a carrier, comprising:

preparing a carrier comprising a releasing layer, and insulating layers and metal layers sequentially disposed on both sides of the releasing layer;

patterning the metal layers to form base circuit layers;

forming buildup layers on the base circuit layers;

executing a routing process to separate the insulating layers from the releasing layer; and

forming solder resist layers on the buildup layers and forming openings in the solder resist layers and the insulating layers to expose pads.

6. The method according to claim 5, wherein, in preparing the carrier, the releasing layer has a smaller length than that of the insulating layers such that the insulating layers are in contact with each other at lateral regions thereof.

7. The method according to claim 5, wherein, in preparing the carrier, the releasing layer includes first and second releasing layers, and the carrier further comprises a reinforcing layer disposed between the first and second releasing layers.

8. The method according to claim 7, wherein the reinforcing layer comprises a double-sided copper clad laminate or a reinforcing and insulating material.

9. The method according to claim 6, wherein, in executing the routing process, the routing process is executed along routing lines positioned inside the lateral regions at which the insulating layers are in contact with each other so as to separate the insulating layers from the releasing layer.