JP2006237402A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique capable of fabricating a semiconductor device with requested characteristics in high yield at low cost without making processes and devices complex. <P>SOLUTION: The semiconductor has a thin film circuit provided on a substrate, and a conductive layer which is electrically connected to the thin film circuit and provided continuously on the substrate and thin film circuit. As an embodiment of a method for manufacturing the semiconductor device, the thin film circuit is installed on the substrate, and a composition containing a conductive material having flowability is stuck on the substrate and thin film circuit to form the conductive layer electrically connected to the thin film circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  2. Description of the Related Art In recent years, attention has been focused on an individual recognition technique in which an ID (individual identification number) is given to an individual object to clarify information such as a history of the object and to be useful for production and management. Among them, development of semiconductor devices capable of transmitting and receiving data without contact is underway. As such a semiconductor device, RFID (Radio Frequency Identification) (also referred to as an ID tag, IC tag, IC chip, RF tag (Radio Frequency), wireless tag, electronic tag, or wireless chip) is particularly used in the company, on the market, etc. Has begun to be introduced.

Many of these semiconductor devices have a circuit using a semiconductor substrate such as silicon (Si) (hereinafter also referred to as an IC (Integrated Circuit) chip) and an antenna, and the IC chip is a memory circuit (hereinafter also referred to as a memory). And a control circuit. Further, various functions are required depending on the use of the semiconductor device. Development of a semiconductor device that can stably provide a service suitable for a purpose has been actively performed (for example, Patent Document 1).
JP 2002-151947 A

    An object of the present invention is to provide a semiconductor device having required characteristics without complicating processes and devices. It is another object of the present invention to provide a technique capable of manufacturing a semiconductor device with low cost and high yield.

    The semiconductor device of the present invention includes a thin film circuit (also referred to as an IC chip) mainly including a transistor and an antenna, and the thin film circuit includes a memory circuit (hereinafter also referred to as a memory), a control circuit, and the like. Yes. In this specification, a thin film circuit is a circuit in which an active element such as a thin film transistor and a diode and a passive element such as a resistor are formed of a semiconductor film having a thickness of 1 μm or less. Are collectively referred to as a thin film circuit portion. A conductive layer electrically connected to the thin film circuit portion is also referred to as an antenna or an antenna portion. The thin film circuit portion and the conductive layer that is the antenna are electrically connected by being formed in contact with the wiring layer of the thin film circuit portion.

    In the present invention, a plurality of thin film circuit portions are formed on a substrate, and the thin film circuit portions are selectively peeled off and attached to a substrate which is also a film to be sealed. The position where the thin film circuit portion is installed on the substrate is controlled in accordance with the structure and size of the antenna of the thin film circuit portion. For control, a marker for alignment control is formed on the substrate, and mass production using a machine is also possible.

    A conductive layer functioning as an antenna is formed by adhering a composition containing a fluid conductive material to the thin film circuit portion and the substrate so as to be in contact with the wiring layer of the thin film circuit portion placed on the substrate. . Therefore, a semiconductor device including a thin film circuit portion provided over a substrate and an antenna electrically connected to the thin film circuit portion can be formed. Since the antenna is directly formed on the thin film circuit portion, heat or pressure is not applied to the thin film circuit portion, so that damage to the thin film circuit portion can be prevented and reliability is improved. In addition, since the process is simplified, productivity is improved at low cost.

  Note that in this specification, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. A semiconductor device such as a multilayer wiring layer or a processor chip can be manufactured by using the present invention.

    One embodiment of the semiconductor device of the present invention includes a thin film circuit portion provided over a substrate and a conductive layer electrically connected to the thin film circuit portion and continuously provided over the substrate and the thin film circuit portion.

    In the above structure, the conductive layer may be provided over a layer containing a substance having a fluorocarbon group on the substrate and the thin film circuit portion and a layer containing the substance having the fluorocarbon group.

    According to one embodiment of the semiconductor device of the present invention, a thin film circuit portion provided over a first flexible substrate, the thin film circuit portion electrically connected to the thin film circuit portion, and the first flexible substrate and thin film A conductive layer provided continuously over the circuit portion; and a second flexible substrate covering the thin film circuit portion and the conductive layer.

    In the above structure, the conductive layer is provided over a layer containing a substance having a fluorocarbon group on the first flexible substrate and the thin film circuit portion, and over the layer containing the substance having a fluorocarbon group. May be.

    According to one method for manufacturing a semiconductor device of the present invention, a thin film circuit portion is provided over a substrate, a composition containing a fluid conductive material is attached to the substrate and the thin film circuit portion, and the thin film circuit portion A conductive layer to be electrically connected is formed.

    According to one method for manufacturing a semiconductor device of the present invention, a thin film circuit portion is provided over a substrate, a composition containing a conductive material is printed over the substrate and the thin film circuit portion, and the thin film circuit portion is electrically connected. A conductive layer is formed.

    According to one method for manufacturing a semiconductor device of the present invention, a plurality of thin film circuit portions are formed over a substrate, the thin film circuit portions are selectively peeled off from the substrate, and bonded to a flexible substrate. A composition containing a fluid conductive material is attached to the substrate and the thin film circuit portion, and a conductive layer electrically connected to the thin film circuit portion is formed.

    According to one method for manufacturing a semiconductor device of the present invention, a plurality of thin film circuit portions are formed over a substrate, the thin film circuit portions are selectively peeled off from the substrate, and bonded to a flexible substrate. A composition containing a conductive material is printed on the substrate and the thin film circuit portion, and a conductive layer electrically connected to the thin film circuit portion is formed.

  According to the present invention, a semiconductor device with higher performance and higher reliability can be manufactured at low cost with high yield.

  Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

(Embodiment 1)
In this embodiment mode, a method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS.

    The semiconductor device of the present invention includes a thin film circuit (also referred to as a thin film circuit) mainly including a transistor and an antenna, and the thin film circuit includes a memory circuit (hereinafter also referred to as a memory), a control circuit, and the like. Yes. In this specification, a thin film circuit is a circuit in which an active element such as a thin film transistor and a diode and a passive element such as a resistor are formed of a semiconductor film having a thickness of 1 μm or less. Are collectively referred to as a thin film integrated circuit portion. A substrate having a thin film circuit is also referred to as a substrate with a thin film circuit.

    In this embodiment mode, a plurality of thin film circuit portions are formed over a substrate, the thin film circuits are selectively peeled off, and attached to a substrate which is also a film to be sealed. The position where the thin film circuit is installed on the substrate is controlled by the structure and size of the antenna of the thin film circuit. Control can be performed by forming a marker on the substrate for alignment, and mass production using a machine is also possible. For peeling and bonding, a peeling layer, an adhesive layer, or the like is used.

    A conductive layer functioning as an antenna is formed by adhering a composition containing a fluid conductive material to the thin film circuit portion and the substrate so as to be in contact with the wiring layer of the thin film circuit portion placed on the substrate. . Therefore, a semiconductor device including a thin film circuit portion provided over a substrate and an antenna electrically connected to the thin film circuit portion can be formed. A mounting method in which an antenna is formed on another substrate, and is bonded by heat and pressure through an anisotropic conductive paste (ACP) or an anisotropic conductive film (ACF), thereby establishing electrical continuity and connection; In comparison, since the antenna is directly formed in the thin film circuit portion in this embodiment, heat or pressure is not applied to the thin film circuit portion, so that damage to the thin film circuit portion can be prevented and reliability is improved. In addition, since the process is simplified, productivity is improved at low cost.

    Further, the required function differs depending on the application of the semiconductor device, and the structure and size of the antenna also change. This is because the antenna characteristics depend on the form of the antenna. The electromotive force generated when the antenna resonates with the reader / writer depends on the frequency, number of turns, area, etc. of the coil of the antenna, and the resonance frequency, which is the frequency when the electromotive force is high, depends on the inductance and capacitance of the coil. . This is because the coil inductance depends on the coil configuration such as the coil size, shape, number of turns, and distance between adjacent coils. Therefore, depending on the frequency to be received, the antenna may be larger than the size of the thin film circuit portion. In this case, after the thin film circuit portion and the antenna are formed on the substrate and then attached to a flexible substrate such as a film, the number of semiconductor devices that can be formed on the substrate is determined by the size of the antenna. And productivity is bad.

    When this embodiment mode is used, the antenna is formed after the thin film circuit portion is selectively attached to the substrate. Therefore, the number of semiconductor devices that can be formed over the substrate can be determined by the size of the thin film circuit portion. it can. Various antennas can be freely formed by controlling the position where the thin film circuit portion is placed on the substrate. In addition, since the antenna uses a printing method that can be formed using a composition containing a conductive material having fluidity, the thickness of the antenna can be increased, and the size of the film thickness can be set. High degree of freedom.

    The thin film circuit portion 51a and the thin film circuit portion 51b are placed and fixed on the substrate 50 while performing alignment using the alignment markers 80a and 80b provided on the substrate 50. For fixing, an adhesive layer can be used. Further, if the thin film circuit portion is mechanically arranged using a flip chip bonder or the like, productivity is improved. Although not shown, the thin film circuit portion 51a and the thin film circuit portion 51b are bonded to the substrate 50 with an adhesive layer (see FIGS. 1A1 and 1A2). 1A1, 1 </ b> B <b> 1, and 1 </ b> C <b> 1 are top views of the semiconductor device, and FIGS. 1A <b> 2, 2 </ b> B <b> 2, and 2 </ b> C2 correspond to a line YZ in each top view. It is sectional drawing.

    A conductive layer 52a and a conductive layer 52b functioning as an antenna are formed by a printing method on the thin film circuit portion 51a and the thin film circuit portion 51b provided over the substrate 50 (see FIGS. 1B1 and 1B2). The thin film circuit portion 51a and the thin film circuit portion 51b have a wiring layer exposed on the surface, and the thin film circuit portion 51a and the conductive layer 52b are formed so that the wiring layer is in contact with the conductive layer 52a and the conductive layer 52b. The layer 52a, the thin film circuit portion 51b, and the conductive layer 52b are electrically connected to each other. In this embodiment mode, the conductive layer 52a and the conductive layer 52b functioning as an antenna are larger in size than the thin film circuit portion 51a and the thin film circuit portion 51b. 51a and the thin film circuit portion 51b are formed so as to be in contact with the substrate 50 as well. At this time, the conductive layer 52a and the conductive layer 52b may be formed in contact with the side end portions of the thin film circuit portion 51a and the thin film circuit portion 51b as in this embodiment. Depending on the shape of the side edge of the thin film circuit portion 51a and the thin film circuit portion 51b and the thickness of the conductive layer 52a and the conductive layer 52b, the conductive layer 52a and the conductive layer 52b are the side edges of the thin film circuit portion 51a and the thin film circuit portion 51b. There are cases where it does not touch the part or only part of it.

    An insulating layer 53 is formed so as to cover the substrate 50, the thin film circuit portion 51a, the thin film circuit portion 51b, the conductive layer 52a, and the conductive layer 52b. In this embodiment mode, the insulating layer 53 is also formed using a printing method. The insulating layer 53 may be formed by a coating method such as a spin coating method, a droplet discharge method, or the like (see FIGS. 1C1 and 1C2). Although it is sufficient that the insulating layer 53 can be sufficiently sealed, it is preferable to seal the insulating layer 53 so as to be covered with a flexible substrate such as a film. Individual semiconductor devices can be obtained by cutting along a dotted line shown in FIG. Through the above steps, a semiconductor device including a thin film circuit and an antenna can be manufactured.

    A more specific example will be described in detail with reference to FIG. A plurality of thin film circuit portions are formed on the substrate 60. The thin film circuit portion is in contact with the substrate 60 via a release layer. In FIG. 2, in order to clearly show the region of the thin film circuit portion formed by exposing the wiring layer, the region having the thin film circuit portion and the wiring layer is divided into two upper and lower regions. The thin film circuit portion is formed over the substrate 60 with the wiring layer exposed to the surface. In the top view in FIG. 2A1, the wiring layer 62a, the wiring layer 62b, the wiring layer 62c, the wiring layer 62d, and the wiring The thin film circuit portion 61a, the thin film circuit portion 61b, the thin film circuit portion 61c, the thin film circuit portion 61d, and the thin film circuit portion 61e that can confirm the layer 62e and face the substrate 60 side are connected to each other as shown in FIG. It is formed by laminating below the layer. FIG. 2 is a schematic diagram only, and shows where the exposed region of the wiring layer has in the thin film circuit portion. The shape is not limited to FIG. 2, and the wiring layer is formed on the entire surface of the thin film circuit portion. It does not need to be formed. The same applies to the schematic diagram of FIG.

    On the substrate 60, a marker 81 for alignment control is formed. 2A1, 2 </ b> B <b> 1, 1 </ b> C <b> 1, and 2 </ b> D <b> 1 are top views of the semiconductor device, and FIGS. 2A <b> 2, 2 </ b> B 2, 2 </ b> C 2, and 2 </ b> D 2 are lines in the top views. It is sectional drawing corresponding to VX. An adhesive layer 85a and an adhesive layer 85b are formed in the region of the thin film circuit portion to be peeled of the transfer substrate 63 having flexibility. The thin film circuit portion 61a, the thin film circuit portion 61b, the thin film circuit portion 61c, the thin film circuit portion 61d, the peeling layer provided between the thin film circuit portion 61e and the substrate 60 is partially or completely removed, and then selectively removed. The transfer substrate 63 having an adhesive layer is bonded and peeled so that the adhesive layer faces the wiring layer. 2B2, the wiring layer 62a included in the thin film circuit portion 61a formed on the substrate 60 is bonded to the adhesive layer 85a, and the wiring layer 62e included in the thin film circuit portion 61e is bonded to the adhesive layer 85b. The film is further peeled off and bonded to the transfer substrate 63 (see FIG. 2B1).

    This peeling process can also be position controlled using the markers 82a and 82b for alignment control. FIG. 2 shows an example in which the markers are formed at the four corners of the transfer substrate 63 and in each region where the thin film circuit is bonded. However, a single marker may be formed or a plurality of markers may be formed at more locations. Good. The marker may be set as appropriate depending on the accuracy required for the position control, the size of the substrate to be aligned, and the like. The same applies to FIG. The marker can be formed by etching the substrate using a photolithography method. In addition, it can also be formed by laser light irradiation or a printing method. Alternatively, a marker can be formed from a composition containing a conductive material by a printing method, and then a conductive layer functioning as an antenna can be formed over the marker, and the marker can be part of the conductive layer. The marker may have any shape, and may have a cross shape, a round shape, a square shape, a linear shape, or the like.

    In FIG. 2B1, the thin film circuit portion 61a and the thin film circuit portion 61e are exposed on the upper surface, and the wiring layer 62a and the wiring layer 62b are in contact with the transfer substrate 63 side. Since the wiring layer and the conductive layer functioning as an antenna must be formed in contact with each other and electrically connected to each other, a separation and transfer process using a flexible substrate is performed again to expose the wiring layer on the surface. The flexible substrate 64 provided with the adhesive layer 86a and the adhesive layer 86b selectively is adhered to the thin film circuit portion 61a and the thin film circuit portion 61e and peeled off from the transfer substrate 63 (see FIG. 2C2). .) After the peeling step, the wiring layer 62a, the adhesive layer 85a and the adhesive layer 85b remaining on the wiring layer 62b are removed, and the thin film circuit portion 61a and the thin film circuit are formed on the substrate 64 as shown in the top view of FIG. The part 61b is installed with the wiring layer 62a and the wiring layer 62b exposed on the surface. The adhesive layer 86a and the adhesive layer 86b may have a stronger adhesive force than the adhesive layer 85a and the adhesive layer 85b, and the adhesive layer 85a and the adhesive layer 85b may be an ultraviolet peelable adhesive layer or adhesive layer. The adhesive force may be controlled by irradiating with ultraviolet rays by using an ultraviolet curable adhesive layer for 86a and adhesive layer 86b. This also applies to the peeling and bonding steps performed using the adhesive force of the adhesive layer in this specification. The adhesive layer corresponds to a layer containing an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, or a resin additive.

    An insulating layer covering the conductive layer 67a and the conductive layer 67b by forming a conductive layer 67a and a conductive layer 67b functioning as an antenna so as to be in contact with the exposed wiring layer 62a, the wiring layer 62b, and the substrate 64; or A substrate is provided (not shown), and the semiconductor device 68a and the semiconductor device 68b are manufactured (see FIGS. 2D1 and 2D2). The semiconductor device 68a and the semiconductor device 68b are separated by a dotted line shown in FIG.

  Note that the example shown in this embodiment mode is just an example, and the shape of the antenna is not limited. The present invention can be implemented with any shape of antenna. Although a linear antenna shape is shown in FIG. 1, for example, an antenna wound in a rectangular shape or a circular antenna may be used. Another example of the antenna shape is shown in FIG. The semiconductor devices in FIGS. 20A and 20B are two semiconductor devices formed over the substrate 40 or the substrate 45, and can be made into individual semiconductor devices by being divided at a dotted line portion. 20A includes a thin film circuit portion 41a, a conductive layer 42a functioning as an antenna, a thin film circuit portion 41b, and a conductive layer 42b functioning as an antenna. The substrate 40 is used for alignment control. A marker 43a and a marker 43b are provided. The conductive layer 42a and the conductive layer 42b are wound in a coil shape. 20B includes a thin film circuit portion 46a, a conductive layer 47a that functions as an antenna, a thin film circuit portion 46b, and a conductive layer 47b that functions as an antenna. A marker 48a and a marker 48b are provided. The conductive layer 47a and the conductive layer 47b are connected to the thin film circuit portion 46a and the thin film circuit portion 46b at two positions so that the two T-shaped conductive layers face each other. As shown in FIG. 20B, a plurality of antennas may be provided, and a plurality of connection points with the thin film circuit portion may be provided.

    A manufacturing process of the semiconductor device in FIG. 2 will be described with reference to FIGS. 5 and 6 which are cross-sectional views corresponding to the line QR in FIG.

    FIG. 5A corresponds to the process of FIG. 2A1, and the thin film circuit portion is formed on the substrate 60 with the wiring layer 205b exposed. A p-channel thin film transistor 210a and an n-type impurity region 206b having a separation layer 222, an insulating layer 201a, an insulating layer 201b, a gate insulating layer 208, a semiconductor layer 204a including a p-type impurity region 206a, and a gate electrode layer 202a over the substrate 60. An n-channel thin film transistor 210b including a semiconductor layer 204b including a gate electrode layer 202b, an insulating layer 209, and an insulating layer 211 are formed. A wiring layer 205a, a wiring layer 205b, and a wiring layer 205c connected to the semiconductor layer 204a and the semiconductor layer 204b of the p-channel thin film transistor 210a and the n-channel thin film transistor 210b, respectively, are formed over the insulating layer 211. An insulating layer 207a and an insulating layer 207b are formed so as to expose the portion. The p-channel thin film transistor 210a and the n-channel thin film transistor 210b are electrically connected and have a CMOS structure.

    After that, the peeling layer 222 is removed as shown in FIG. 2, and a peeling process is performed. As shown in FIG. 5B corresponding to the process shown in FIG. 2D1, a conductive layer 212 functioning as an antenna is formed by a printing method. Is done. Various printing methods (screen (stencil) printing, offset (lithographic) printing, relief printing, gravure (intaglio printing), etc. can be used.The screen printing method is used in FIG. A screen printing plate having (mesh) 214 and a mask emulsion 213 provided on a frame is provided on the wiring layer 205b, and then a composition (paste) 215 is provided on the screen printing plate, and a squeegee 216, a roller, etc. The composition (paste) 215 is then used to extrude the composition (paste) 215. As a result, the composition (paste) can be applied and printed on the wiring layer 205b, before the paste is pushed out by a squeegee or roller. The conductive layer 212 may be formed by drying and baking the composition (paste) applied by printing. Doo can (see FIG. 5 (B) reference.).

    An insulating layer 220 is formed so as to cover the conductive layer 212 and the thin film circuit portion, and sealed with a flexible substrate 221, so that a semiconductor device is manufactured (see FIGS. 6A and 6B). In FIG. 6A, the insulating layer 220 is formed by a screen printing method in the same manner as the conductive layer 212.

    Another example will be described in detail with reference to FIG. 2 shows an example in which the wiring layer is exposed on the upper surface on the substrate on which the thin film circuit portion is formed, but FIG. 3 shows an example in which the wiring layer reaches the substrate side. Show. Also in FIG. 3, a plurality of thin film circuit portions are formed on the substrate 70 as in FIG. Further, the thin film circuit portion is in contact with the substrate 70 through a release layer. Also in FIG. 3, in order to clearly show the region of the thin film circuit portion where the wiring layer is exposed, the region having the thin film circuit portion and the wiring layer is shown by changing the hatching in the drawing. The thin film circuit portion is formed over the substrate 70 with the wiring layer partially exposed to the substrate 70 side. In the top view in FIG. 3A1, the wiring layer 72a, the wiring layer 72b, the wiring layer 72c, and the wiring The thin film circuit portion 71a, the thin film circuit portion 71b, the thin film circuit portion 71c, the thin film circuit portion 71d, and the thin film circuit portion 71e facing the substrate 70 can be confirmed as shown in FIG. 3A2. In this way, it is formed by laminating below each wiring layer.

    On the substrate 70, an alignment control marker 83 is formed. 3A1, 3 </ b> B1, and 3 </ b> C1 are top views of the semiconductor device, and FIGS. 3A2, 3 </ b> B <b> 2, and 2 </ b> C2 are cross-sectional views corresponding to a line U-W in each top view. It is. An adhesive layer 87a and an adhesive layer 87b are formed in the region of the thin film circuit portion to be peeled over the flexible substrate 74. The thin film circuit portion 71a, the thin film circuit portion 71b, the thin film circuit portion 71c, the thin film circuit portion 71d, the peeling layer provided between the thin film circuit portion 71e and the substrate 70 is partially or completely removed, and then selectively removed. The substrate 74 having an adhesive layer is bonded and peeled so that the adhesive layer faces the wiring layer. As shown in FIG. 3B2, the wiring layer 72a of the thin film circuit portion 71a formed on the substrate 70 is bonded to the adhesive layer 87a, and the wiring layer 72e of the thin film circuit portion 71e is bonded to the adhesive layer 87b. It is further peeled off and adheres to the substrate 74 (see FIG. 3B1). Also in this peeling step, position control can be performed using the alignment control markers 84a and 84b.

    As shown in the top view of FIG. 3C1, a thin film circuit portion 71a and a thin film circuit portion 71b are installed on a substrate 74 with a part of the wiring layer 72a and a part of the wiring layer 72b exposed on the surface. The A conductive layer 77a and a conductive layer 77b that function as an antenna so as to be in contact with the exposed wiring layer 72a, the wiring layer 72b, and the substrate 74 by a printing method, and an insulating layer that covers the conductive layer 77a and the conductive layer 77b, or A substrate is provided (not shown), and the semiconductor device 76a and the semiconductor device 76b are manufactured (see FIGS. 3C1 and 3C2). The semiconductor device 76a and the semiconductor device 76b are divided into individual semiconductor devices 76a and 76b by being separated by a dotted line illustrated in FIG.

    A manufacturing process of the semiconductor device in FIG. 3 will be described with reference to FIGS. 7 and 8, which are cross-sectional views corresponding to line ST in FIG.

    FIG. 7A corresponds to the process of FIG. 3A 1, and a thin film circuit portion is formed in the contact hole so that the wiring layer 235 b reaches the substrate 70 in the substrate 70. A separation layer 232, an insulating layer 231a, an insulating layer 231b, a gate insulating layer 238, and a p-channel thin film transistor 230a, an n-channel thin film transistor 230b, an insulating layer 239, and an insulating layer 245 having a structure similar to that illustrated in FIG. 5 are formed over the substrate 70. Has been. The p-channel thin film transistor 230a and the n-channel thin film transistor 230b are electrically connected and have a CMOS structure. The wiring layers 235a, 235b, and 235c connected to the semiconductor layers of the p-channel thin film transistor 230a and the n-channel thin film transistor 230b are formed over the insulating layer 211, and the wiring layer 235b includes the insulating layer 245 and the insulating layer. 239, a gate insulating layer 238, an insulating layer 231b, and a contact hole formed in the insulating layer 231a so as to be in contact with the substrate 70. An insulating layer 237 is formed so as to cover the thin film circuit portion.

    After that, as shown in FIG. 3, the peeling layer 232 is removed and a peeling process is performed. As shown in FIG. 7B corresponding to the process of FIG. 3C1, the conductive layer 241 functioning as an antenna is a droplet discharge device. It is formed by a droplet discharge method using 240. The droplet discharge method is a method in which a composition containing a composition forming material that is a fluid is discharged (jetted) as droplets to form a desired pattern shape. A droplet containing a component forming material is discharged onto a region where the component is to be formed, and fixed by firing, drying, or the like to form a component having a desired pattern.

    One mode of a droplet discharge apparatus used for the droplet discharge method is shown in FIG. The individual heads 1405 and 1412 of the droplet discharge means 1403 are connected to the control means 1407, which can be drawn in a pre-programmed pattern under the control of the computer 1410. The drawing timing may be performed with reference to a marker 1411 formed on the substrate 1400, for example. Alternatively, the reference point may be determined based on the edge of the substrate 1400. This is detected by the imaging means 1404, converted into a digital signal by the image processing means 1409, is recognized by the computer 1410, a control signal is generated, and sent to the control means 1407. As the imaging unit 1404, an image sensor using a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) can be used. Of course, the information on the pattern to be formed on the substrate 1400 is stored in the storage medium 1408. Based on this information, a control signal is sent to the control means 1407, and each head 1405 of the droplet discharge means 1403 is sent. The heads 1412 can be individually controlled. The material to be discharged is supplied from the material supply source 1413 and the material supply source 1414 to the head 1405 and the head 1412 through piping.

    The inside of the head 1405 has a structure having a space filled with a liquid material as indicated by a dotted line 1406 and a nozzle that is a discharge port. Although not shown, the head 1412 has the same internal structure as the head 1405. When the nozzles of the head 1405 and the head 1412 are provided in different sizes, different materials can be drawn simultaneously with different widths. With one head, conductive material, organic material, inorganic material, etc. can be discharged and drawn respectively. When drawing in a wide area like an interlayer film, the same material is used from multiple nozzles to improve throughput. It is possible to discharge and draw at the same time. In the case of using a large substrate, the head 1405 and the head 1412 can freely scan on the substrate in the direction of the arrow to freely set a drawing area, and a plurality of the same pattern can be drawn on a single substrate. it can.

    In the case of forming a conductive layer by using a droplet discharge method, a conductive layer is formed by discharging a composition containing a conductive material processed into a particulate form and fusing or fusion-bonding and solidifying by firing. In such a conductive layer (or insulating layer) formed by discharging and baking a composition containing a conductive material, the conductive layer (or insulating layer) formed by sputtering or the like is mostly a columnar structure. In many cases, a polycrystalline state having many grain boundaries is exhibited.

    An insulating layer 243 is formed so as to cover the conductive layer 241 and the thin film circuit portion, and sealed with a flexible substrate 244 to manufacture a semiconductor device (see FIGS. 7A and 7B). In FIG. 7A, the insulating layer 220 is formed by a spin coating method.

    As the composition having fluidity, a composition obtained by dissolving or dispersing a conductive material in a solvent is used. Conductive materials include metals such as Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, and Al, metal sulfides of Cd and Zn, Fe, Ti, Si, Ge, Si, Zr, and Ba It corresponds to oxides such as silver halide fine particles or dispersible nanoparticles. Further, it corresponds to indium tin oxide (ITO) used as a transparent conductive film, ITSO composed of indium tin oxide and silicon oxide, organic indium, organic tin, zinc oxide, titanium nitride, and the like. However, it is preferable to use a composition in which any of gold, silver and copper is dissolved or dispersed in a solvent in consideration of the specific resistance value, more preferably the composition discharged from the discharge port. It is preferable to use low resistance silver or copper. However, when silver or copper is used, a barrier film may be provided as a countermeasure against impurities. As the barrier film, a silicon nitride film or nickel boron (NiB) can be used. As the solvent, esters such as butyl acetate and ethyl acetate, alcohols such as isopropyl alcohol and ethyl alcohol, organic solvents such as methyl ethyl ketone and acetone, and water are used.

    The composition to be discharged is obtained by dissolving or dispersing a conductive material in a solvent, but additionally contains a dispersant and a thermosetting resin called a binder. In particular, the binder has a function of preventing occurrence of cracks and uneven baking during firing. Thus, the formed conductive layer may contain an organic material. The organic material contained varies depending on the heating temperature, atmosphere, and time. This organic material is a metal particle binder, a solvent, a dispersant, an organic resin that functions as a coating agent, etc., and typically, polyimide, acrylic, novolac resin, melamine resin, phenol resin, epoxy resin, silicon resin , Furan resin, diallyl phthalate resin and the like, and known organic resins.

    2 and 3 show examples in which a semiconductor device is manufactured by selectively peeling and bonding a thin film circuit portion formed over a substrate to a substrate serving as a sealing film. An installation example of another thin film circuit portion is shown in FIG.

    4, as in FIG. 2, a plurality of thin film circuit portions are formed on the substrate 30 via a release layer. The thin film circuit unit 31a, the thin film circuit unit 31b, the thin film circuit unit 31c, the thin film circuit unit 31d, and the thin film circuit unit 31e have a wiring layer 32a, a wiring layer 32b, a wiring layer 32c, a wiring layer 32d, and a wiring layer 32e, respectively. (See FIGS. 4A1 and 4A2.) A part or all of the peeling layer under the thin film circuit part 31a, the thin film circuit part 31b, the thin film circuit part 31c, the thin film circuit part 31d, and the thin film circuit part 31e is removed to make it easy to peel from the substrate 30. A flexible substrate 33 having an adhesive surface is formed on a thin film circuit portion 31a, a thin film circuit portion 31b, a thin film circuit portion 31c, a thin film circuit portion 31d, a wiring layer 32a of the thin film circuit portion 31e, a wiring layer 32b, a wiring layer 32c, and a wiring layer. 32d is bonded to the wiring layer 32e side and peeled off (see FIGS. 4B2 and 4B2). As in FIG. 2, a flexible substrate 34 having an adhesive surface is formed as a thin film circuit portion 31a, a thin film circuit portion 31b, a thin film circuit portion 31c, a thin film circuit portion 31d, and a thin film circuit portion so that the wiring layer is exposed to the upper surface again. The wiring layer 32a, the wiring layer 32b, the wiring layer 32c, the wiring layer 32d, and the wiring layer 32e are exposed (see FIGS. 4C1 and 4C2). Then, the board | substrate 34 is parted by the dotted line part of FIG.4 (C1), and it is set as each thin film circuit part. The thin film circuit portions 38a and 38b having individually divided substrates are selectively installed on a flexible substrate 35 that serves as a sealing material together with the substrate 34. A conductive layer 37a and a conductive layer 37b functioning as an antenna are formed on the wiring layer and the substrate 35 by a printing method. After that, an insulating layer or a substrate covering the conductive layer 37a and the conductive layer 37b is provided and sealed, and cut by a dotted line in FIG. 4D1 with a laser beam or the like to manufacture a semiconductor device. In the case of FIG. 4, since the conductive layer 37a is formed so as to cover the thin film circuit portion 38a having the substrate, the film thickness of the conductive layer 37a is preferably equal to or greater than the film thickness of the thin film circuit portion 38a having the substrate. The film thickness of the conductive layer 37a can be adjusted by controlling the wettability of the formation region of the conductive layer 37a with respect to the composition containing a conductive material having fluidity. As will be described in detail in Embodiment 2, if the formation region is controlled so that the contact angle with respect to the composition containing a conductive material having fluidity is increased, the composition does not wet and spread, so the film thickness is increased. can do. When the conductive layer 37a is thin and does not have continuity as a film, the conductive layer can be stacked again by a printing method.

    As a substrate for forming the thin film circuit portion, a glass substrate, a flexible substrate, a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate, or the like can be used. The flexible substrate is a substrate that can be bent (flexible), and examples thereof include a plastic substrate made of polycarbonate, polyarylate, polyethersulfone, or the like. Also, use laminate film (made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, etc.), paper made of fibrous material, base film (polyester, polyamide, inorganic vapor deposition film, paper, etc.), etc. You can also. In this specification, the substrate is a support material capable of sealing the thin film circuit portion and the antenna, and includes the base materials made of the various materials described above.

    A thin film circuit portion and an antenna are attached to a flexible substrate and installed, whereby a flexible semiconductor device can be obtained. The film is subjected to heat treatment and pressure treatment by thermocompression bonding. When the heat treatment and pressure treatment are performed, the film is either an adhesive layer provided on the outermost surface of the film or the A layer (not an adhesive layer) provided in the outer layer is melted by heat treatment and bonded by pressure. In addition, the substrate may be provided with an adhesive layer or may not be provided with an adhesive layer. The adhesive layer corresponds to a layer containing an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, or a resin additive.

    As described above, according to the present invention, a high-performance and highly reliable semiconductor device can be manufactured at low cost with high yield.

(Embodiment 2)
In this embodiment, a method for manufacturing a semiconductor device of the present invention including a thin film transistor, a memory element, and an antenna will be described with reference to drawings. The semiconductor device described in this embodiment is characterized in that data can be read and written in a non-contact manner. A data transmission format is an electromagnetic which performs communication by mutual induction with a pair of coils arranged opposite to each other. There are roughly divided into a coupling system, an electromagnetic induction system that communicates using an induction electromagnetic field, and a radio system that communicates using radio waves, but any system may be used.

  First, the peeling layer 401 is formed on one surface of the substrate 400. As the substrate 400, a glass substrate, a quartz substrate, a metal substrate, a stainless steel substrate with an insulating layer formed on one surface, a heat-resistant plastic substrate that can withstand the processing temperature in this step, or the like may be used. With such a substrate 400, the area and shape of the substrate 400 are not greatly limited. For example, if the substrate 400 has a side of 1 meter or more and a rectangular shape, the productivity is remarkably improved. Can be made. Such an advantage is a great advantage compared to the case of using a circular silicon substrate. Note that in this step, the separation layer 401 is provided over the entire surface of the substrate 400; however, if necessary, the separation layer 401 is provided over the entire surface of the substrate 400 and then selectively provided by patterning using a photolithography method. May be. In addition, the peeling layer 401 is formed so as to be in contact with the substrate 400, but if necessary, an insulating layer serving as a base is formed so as to be in contact with the substrate 400, and the peeling layer 401 is formed so as to be in contact with the insulating layer. May be.

  The peeling layer 401 is formed by a known means (sputtering method, plasma CVD method, etc.) tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nd), nickel (Ni), cobalt An element selected from (Co), zirconium (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), lead (Pd), osmium (Os), iridium (Ir), silicon (Si) A layer formed of an alloy material or a compound material containing an element as a main component is formed as a single layer or a stacked layer. The crystal structure of the layer containing silicon may be any of amorphous, microcrystalline, and polycrystalline.

  In the case where the separation layer 401 has a single-layer structure, for example, a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum is formed. Alternatively, a layer containing tungsten oxide or oxynitride, a layer containing molybdenum oxide or oxynitride, or a layer containing oxide or oxynitride of a mixture of tungsten and molybdenum is formed. Note that the mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum. The oxide of tungsten may be expressed as tungsten oxide.

  In the case where the separation layer 401 has a stacked structure, a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum is formed as a first layer, and an oxide or nitride of tungsten, molybdenum, or a mixture of tungsten and molybdenum is formed as a second layer Forming an oxide, oxynitride or nitride oxide.

Note that in the case where a layered structure of a layer containing tungsten and a layer containing an oxide of tungsten is formed as the separation layer 401, a layer containing tungsten is formed, and a layer containing silicon oxide is formed thereover. The fact that a layer containing an oxide of tungsten is formed at the interface between the layer and the silicon oxide layer may be utilized. The same applies to the case where a layer containing tungsten nitride, oxynitride, and nitride oxide is formed. After a layer containing tungsten is formed, a silicon nitride layer, a silicon oxynitride layer, and a silicon nitride oxide layer are formed thereon. A layer may be formed. The oxide of tungsten is represented by WOx, X is 2 to 3, and when X is 2 (WO ₂ ), when X is 2.5 (W ₂ O ₅ ), X is 2.75. (W ₄ O ₁₁ ) and X is 3 (WO ₃ ). In forming the tungsten oxide, there is no particular limitation on the value of X mentioned above, and it is preferable to determine which oxide is formed based on the etching rate or the like. Note that the best etching rate is a layer containing tungsten oxide (WOx, 0 <X <3) formed by a sputtering method in an oxygen atmosphere. Therefore, in order to shorten the manufacturing time, a layer containing a tungsten oxide is preferably formed as the separation layer by a sputtering method in an oxygen atmosphere.

    A silicon nitride oxide film (SiNO) is formed on the release layer 401 by a sputtering method, a PVD method (Physical Vapor Deposition), a low pressure CVD method (LPCVD method), or a CVD method (Chemical Vapor Deposition) such as a plasma CVD method. Is used to form a base film 101a of 10 to 200 nm (preferably 50 to 100 nm), and a silicon oxynitride film (SiON) is used to stack a base film 101b of 50 to 200 nm (preferably 100 to 150 nm). Further, the insulating layer may be formed by a coating method, a printing method, or the like. In this embodiment, the insulating layer 402a and the insulating layer 402b are formed by a plasma CVD method.

As the insulating layer 402a and the insulating layer 402b, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like can be used, and a single layer or a stacked structure of two layers or three layers may be used. Note that in this specification, silicon oxynitride is a substance in which the oxygen composition ratio is higher than the nitrogen composition ratio, and can also be referred to as silicon oxide containing nitrogen. Similarly, silicon nitride oxide is a substance in which the composition ratio of nitrogen is higher than the composition ratio of oxygen, and can be said to be silicon nitride containing oxygen. In this embodiment, a silicon nitride oxide film having a thickness of 50 nm is formed on a substrate using SiH ₄ , NH ₃ , N ₂ O, N _2, and H ₂ as reactive gases, and oxidized using SiH ₄ and N ₂ O as reactive gases. A silicon nitride film is formed with a thickness of 100 nm. The thickness of the silicon nitride oxide film may be 140 nm, and the thickness of the stacked silicon oxynitride film may be 100 nm.

    Next, a semiconductor film is formed over the base film. The semiconductor film may be formed by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like) with a thickness of 25 to 200 nm (preferably 30 to 150 nm). In this embodiment mode, it is preferable to use a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film by laser crystallization.

    As a material for forming the semiconductor film, an amorphous semiconductor (hereinafter also referred to as “amorphous semiconductor: AS”) manufactured by a vapor deposition method or a sputtering method using a semiconductor material gas typified by silane or germane is used. A polycrystalline semiconductor obtained by crystallizing a crystalline semiconductor using light energy or thermal energy, or a semi-amorphous (also referred to as microcrystal or microcrystal; hereinafter, also referred to as “SAS”) semiconductor can be used.

SAS is a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal) and having a third state that is stable in terms of free energy and has a short-range order and a lattice. It includes a crystalline region with strain. A crystal region of 0.5 to 20 nm can be observed in at least a part of the film, and when silicon is the main component, the Raman spectrum shifts to a lower wave number side than 520 cm ^−1. Yes. In X-ray diffraction, diffraction peaks of (111) and (220) that are derived from the silicon crystal lattice are observed. At least 1 atomic% or more of hydrogen or halogen is contained as a neutralizing agent for dangling bonds. The SAS is formed by glow discharge decomposition (plasma CVD) of a silicide gas. As the silicide gas, SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _{4, and the} like can be used. Further, F ₂ and GeF ₄ may be mixed. This silicide gas may be diluted with H ₂ , or H ₂ and one or more kinds of rare gas elements selected from He, Ar, Kr, and Ne. The dilution rate is in the range of 2 to 1000 times, the pressure is in the range of approximately 0.1 Pa to 133 Pa, and the power supply frequency is 1 MHz to 120 MHz, preferably 13 MHz to 60 MHz. The substrate heating temperature is preferably 300 ° C. or lower, and can be formed even at a substrate heating temperature of 100 to 200 ° C. Here, as an impurity element mainly taken in during film formation, impurities derived from atmospheric components such as oxygen, nitrogen, and carbon are preferably 1 × 10 ²⁰ atoms / cm ³ or less, and in particular, the oxygen concentration is 5 ×. It is preferable to set it to 10 ¹⁹ atoms / cm ³ or less, preferably 1 × 10 ¹⁹ atoms / cm ³ or less. Further, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, stability is improved and a favorable SAS can be obtained. In addition, a SAS layer formed of a hydrogen-based gas may be stacked on a SAS layer formed of a fluorine-based gas as a semiconductor film.

    A typical example of an amorphous semiconductor is hydrogenated amorphous silicon, and a typical example of a crystalline semiconductor is polysilicon. Polysilicon (polycrystalline silicon) is mainly made of so-called high-temperature polysilicon using polysilicon formed through a process temperature of 800 ° C. or higher as a main material, or polysilicon formed at a process temperature of 600 ° C. or lower. And so-called low-temperature polysilicon, and polysilicon crystallized by adding an element that promotes crystallization. Needless to say, as described above, a semi-amorphous semiconductor or a semiconductor containing a crystal phase in part of a semiconductor film can also be used.

  Alternatively, an organic semiconductor material can be used as a semiconductor and can be formed by a printing method, a spray method, a spin coating method, a droplet discharge method, or the like. In this case, the number of processes can be reduced because the etching process is not necessary. As the organic semiconductor, a low molecular material, a polymer material, or the like is used, and materials such as an organic dye or a conductive polymer material can also be used. The organic semiconductor material used in the present invention is preferably a π-electron conjugated polymer material whose skeleton is composed of conjugated double bonds. Typically, a soluble polymer material such as polythiophene, polyfluorene, poly (3-alkylthiophene), a polythiophene derivative, or pentacene can be used.

  In addition, as an organic semiconductor material that can be used in the present invention, there is a material that can form a semiconductor layer by processing after forming a soluble precursor. Examples of the organic semiconductor material that passes through such a precursor include polythienylene vinylene, poly (2,5-thienylene vinylene), polyacetylene, a polyacetylene derivative, and polyarylene vinylene.

  When converting the precursor into an organic semiconductor, a reaction catalyst such as hydrogen chloride gas is added as well as heat treatment. Typical solvents for dissolving these soluble organic semiconductor materials include toluene, xylene, chlorobenzene, dichlorobenzene, anisole, chloroform, dichloromethane, γ-butyllactone, butyl cellosolve, cyclohexane, NMP (N-methyl-2 -Pyrrolidone), cyclohexanone, 2-butanone, dioxane, dimethylformamide (DMF), THF (tetrahydrofuran), or the like can be applied.

In the case where a crystalline semiconductor film is used as the semiconductor film, a method for manufacturing the crystalline semiconductor film can be a known method (laser crystallization method, thermal crystallization method, or heat using an element that promotes crystallization such as nickel. A crystallization method or the like may be used. In addition, a microcrystalline semiconductor that is a SAS can be crystallized by laser irradiation to improve crystallinity. In the case where an element for promoting crystallization is not introduced, the concentration of hydrogen contained in the amorphous semiconductor film is set to 1 × by heating at 500 ° C. for 1 hour in a nitrogen atmosphere before irradiating the amorphous semiconductor film with laser light. Release to 10 ²⁰ atoms / cm ³ or less. This is because the film is destroyed when an amorphous semiconductor film containing a large amount of hydrogen is irradiated with laser light. As the heat treatment for crystallization, a heating furnace, laser irradiation, irradiation with light emitted from a lamp (also referred to as lamp annealing), or the like can be used. As a heating method, there are RTA methods such as a GRTA (Gas Rapid Thermal Anneal) method and an LRTA (Lamp Rapid Thermal Anneal) method.

    The method of introducing the metal element into the amorphous semiconductor film is not particularly limited as long as the metal element can be present on the surface of the amorphous semiconductor film or inside the amorphous semiconductor film. For example, sputtering, CVD, A plasma treatment method (including a plasma CVD method), an adsorption method, or a method of applying a metal salt solution can be used. Among these, the method using a solution is simple and useful in that the concentration of the metal element can be easily adjusted. At this time, in order to improve the wettability of the surface of the amorphous semiconductor film and to spread the aqueous solution over the entire surface of the amorphous semiconductor film, irradiation with UV light in an oxygen atmosphere, thermal oxidation method, hydroxy radical It is desirable to form an oxide film by treatment with ozone water or hydrogen peroxide.

By using a solid-state laser capable of continuous oscillation and irradiating laser light of the second to fourth harmonics of the fundamental wave, a crystal having a large grain size can be obtained. For example, typically, it is desirable to use the second harmonic (532 nm) or the third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm). Specifically, laser light emitted from a continuous wave YVO ₄ laser is converted into a harmonic by a non-linear optical element to obtain laser light having an output number of W or more. Then, it is preferably formed into a rectangular or elliptical laser beam on the irradiation surface by an optical system and irradiated onto the semiconductor film. At this time, the energy density of about 0.001~100MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 0.5 to 2000 cm / sec (preferably 10 to 200 cm / sec).

    The laser beam shape is preferably linear. As a result, throughput can be improved. Further, the laser may be irradiated with an incident angle θ (0 <θ <90 degrees) with respect to the semiconductor film. This is because laser interference can be prevented.

    Laser irradiation can be performed by relatively scanning such a laser and the semiconductor film. In laser irradiation, a marker can be formed in order to superimpose beams with high accuracy and to control a laser irradiation start position and a laser irradiation end position. The marker may be formed on the substrate simultaneously with the amorphous semiconductor film.

As the laser, a continuous wave or pulsed gas laser, solid state laser, copper vapor laser, gold vapor laser, or the like can be used. Examples of gas lasers include excimer lasers, Ar lasers, Kr lasers, and He-Cd lasers. Solid state lasers include YAG lasers, YVO ₄ lasers, YLF lasers, YAlO ₃ lasers, Y ₂ O ₃ lasers, glass lasers, and ruby lasers. Alexandride laser, Ti: sapphire laser, and the like.

    Further, the laser crystallization may be performed using a frequency band significantly higher than a frequency band of several tens to several hundreds Hz that is usually used with an oscillation frequency of pulsed laser light of 0.5 MHz or more. It is said that the time from irradiating a semiconductor film with laser light by pulse oscillation until the semiconductor film is completely solidified is several tens to several hundreds nsec. Therefore, by using the above frequency band, it is possible to irradiate the next pulse of laser light from when the semiconductor film is melted by the laser light to solidification. Accordingly, since the solid-liquid interface can be continuously moved in the semiconductor film, a semiconductor film having crystal grains continuously grown in the scanning direction is formed. Specifically, a set of crystal grains having a width of 10 to 30 μm in the scanning direction and a width of about 1 to 5 μm in a direction perpendicular to the scanning direction can be formed. By forming single crystal grains extending long along the scanning direction, a semiconductor film having almost no crystal grain boundary at least in the channel direction of the thin film transistor can be formed.

    Further, laser light may be irradiated in an inert gas atmosphere such as a rare gas or nitrogen. Accordingly, the surface roughness of the semiconductor can be suppressed by laser light irradiation, and variations in threshold values caused by variations in interface state density can be suppressed.

    Crystallization of the amorphous semiconductor film may be a combination of heat treatment and crystallization by laser light irradiation, or may be performed multiple times by heat treatment or laser light irradiation alone.

In this embodiment, an amorphous semiconductor film is formed over the insulating layer 402b, and the crystalline semiconductor film is formed by crystallizing the amorphous semiconductor film. As the amorphous semiconductor film, amorphous silicon formed using a reaction gas of SiH ₄ and H ₂ is used. In this embodiment, the insulating layer 402a, the insulating layer 402b, and the amorphous semiconductor film are continuously formed in the same chamber without breaking the vacuum at the same temperature of 330 ° C. while switching the reaction gas.

    After removing the oxide film formed on the amorphous semiconductor film, the oxide film is made 10 by irradiation with UV light in an oxygen atmosphere, a thermal oxidation method, treatment with ozone water containing hydrogen radicals or hydrogen peroxide, and the like. Form ~ 50cm. In this embodiment mode, Ni is used as an element for promoting crystallization. An aqueous solution containing 10 ppm of Ni acetate is applied by spin coating.

    In this embodiment mode, heat treatment is performed at 750 ° C. for 3 minutes by an RTA method, and then an oxide film formed over the semiconductor film is removed and laser light is irradiated. The amorphous semiconductor film is crystallized by the above crystallization treatment and formed as a crystalline semiconductor film.

    When crystallization using a metal element is performed, a gettering step is performed in order to reduce or remove the metal element. In this embodiment mode, a metal element is captured using an amorphous semiconductor film as a gettering sink. First, an oxide film is formed over the crystalline semiconductor film by irradiation with UV light in an oxygen atmosphere, a thermal oxidation method, treatment with ozone water containing hydroxyl radicals or hydrogen peroxide, and the like. The oxide film is preferably thickened by heat treatment. Next, an amorphous semiconductor film is formed to a thickness of 50 nm by a plasma CVD method (conditions 350 W and 35 Pa in this embodiment).

  Thereafter, heat treatment is performed at 744 ° C. for 3 minutes by the RTA method to reduce or remove the metal element. The heat treatment may be performed in a nitrogen atmosphere. Then, the amorphous semiconductor film that has been a gettering sink and the oxide film formed on the amorphous semiconductor film are removed with hydrofluoric acid or the like, and the crystalline semiconductor film in which the metal element is reduced or removed is obtained. Obtainable. In this embodiment mode, the amorphous semiconductor film serving as a gettering sink is removed using TMAH (Tetramethyl ammonium hydroxide).

    In order to control the threshold voltage of the thin film transistor, the semiconductor film thus obtained may be doped with a trace amount of impurity element (boron or phosphorus). This doping of the impurity element may be performed on the amorphous semiconductor film before the crystallization step. When the impurity element is doped in the state of the amorphous semiconductor film, the impurity can be activated by heat treatment for subsequent crystallization. In addition, defects and the like generated during doping can be improved.

    Next, the crystalline semiconductor film is patterned using a mask. In this embodiment mode, after removing the oxide film formed over the crystalline semiconductor film, a new oxide film is formed. Then, a photomask is manufactured, and a semiconductor layer 403a, a semiconductor layer 403b, a semiconductor layer 403c, and a semiconductor layer 403d are formed by patterning treatment using a photolithography method.

As the etching process at the time of patterning, either plasma etching (dry etching) or wet etching may be employed, but plasma etching is suitable for processing a large area substrate. As an etching gas, a fluorine-based or chlorine-based gas such as CF ₄ , NF ₃ , Cl ₂ , or BCl ₃ may be used, and an inert gas such as He or Ar may be appropriately added. Further, if an atmospheric pressure discharge etching process is applied, a local electric discharge process is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

    In the present invention, a conductive layer for forming a wiring layer or an electrode layer, a mask layer for forming a predetermined pattern, or the like may be formed by a method capable of selectively forming a pattern such as a droplet discharge method. . A droplet discharge (ejection) method (also called an ink-jet method depending on the method) is a method in which a droplet of a composition prepared for a specific purpose is selectively ejected (ejection) to form a predetermined pattern (such as a conductive layer or a conductive layer). An insulating layer or the like can be formed. At this time, a process for controlling wettability and adhesion may be performed on the formation region. In addition, a method by which a pattern can be transferred or drawn, for example, a printing method (a method for forming a pattern such as screen printing or offset printing) can be used.

  In this embodiment mode, a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, a melamine resin, or a urethane resin is used as a mask to be used. Also, organic materials such as benzocyclobutene, parylene, flare, permeable polyimide, compound materials made by polymerization of siloxane polymers, composition materials containing water-soluble homopolymers and water-soluble copolymers, etc. are used. You can also Alternatively, a commercially available resist material containing a photosensitizer may be used. For example, a novolak resin that is a typical positive resist and a naphthoquinonediazide compound that is a photosensitizer, a base resin that is a negative resist, diphenylsilanediol, and An acid generator or the like may be used. When using the droplet discharge method, regardless of which material is used, the surface tension and viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant or the like.

    The oxide film over the semiconductor layer is removed, and a gate insulating layer is formed to cover the semiconductor layer 403a, the semiconductor layer 403b, the semiconductor layer 403c, and the semiconductor layer 403d. The gate insulating layer is formed of an insulating film containing silicon with a thickness of 10 to 150 nm using a plasma CVD method or a sputtering method. The gate insulating layer may be formed of a known material such as silicon nitride, silicon oxide, silicon oxynitride, or silicon oxide or nitride material typified by silicon nitride oxide, and may be a stacked layer or a single layer. Further, the insulating layer may be a three-layer stack of a silicon nitride film, a silicon oxide film, and a silicon nitride film, or a stack of a single layer and two layers of a silicon oxynitride film. A silicon nitride film having a dense film quality is preferably used. Further, a thin silicon oxide film with a thickness of 1 to 100 nm, preferably 1 to 10 nm, more preferably 2 to 5 nm may be formed between the semiconductor layer and the gate insulating layer. As a method for forming a thin silicon oxide film, a thin silicon oxide film can be formed by oxidizing the surface of the semiconductor region using a GRTA method, an LRTA method, or the like to form a thermal oxide film. Note that in order to form a dense insulating film with low gate leakage current at a low deposition temperature, a rare gas element such as argon is preferably contained in the reaction gas and mixed into the formed insulating film. In this embodiment, a silicon oxynitride film is formed to a thickness of 115 nm as the gate insulating layer 107.

    Next, a first conductive film with a thickness of 20 to 100 nm and a second conductive film with a thickness of 100 to 400 nm used as a gate electrode layer are stacked over the gate insulating layer. The first conductive film and the second conductive film can be formed by a known method such as sputtering, vapor deposition, or CVD. The first conductive film and the second conductive film are tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), neodymium (Nd ), Or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used as the first conductive film and the second conductive film. The structure is not limited to a two-layer structure. For example, a tungsten film with a thickness of 50 nm is used as the first conductive film, an aluminum-silicon alloy (Al-Si) film with a thickness of 500 nm is used as the second conductive film, The conductive film may have a three-layer structure in which titanium nitride films with a thickness of 30 nm are sequentially stacked. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten of the first conductive film, or aluminum instead of the aluminum and silicon alloy (Al-Si) film of the second conductive film. A titanium alloy film (Al—Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film. Moreover, a single layer structure may be sufficient. In this embodiment mode, tantalum nitride (TaN) is formed with a thickness of 30 nm as the first conductive film, and tungsten (W) is formed with a thickness of 370 nm as the second conductive film.

Next, a resist mask is formed using a photolithography method, the first conductive film and the second conductive film are patterned, and the first gate electrode layer 405a, the first gate electrode layer 405b, and the first The first gate electrode layer 405c, the first gate electrode layer 405d, the second gate electrode layer 406a, the second gate electrode layer 406b, the second gate electrode layer 406c, and the second gate electrode layer 406d are formed. Using ICP (Inductively Coupled Plasma) etching method, etching conditions (amount of power applied to coil-type electrode layer, amount of power applied to electrode layer on substrate side, electrode temperature on substrate side, etc.) By appropriately adjusting the first gate electrode layer 405a, the first gate electrode layer 405b, the first gate electrode layer 405c, the first gate electrode layer 405d, the second gate electrode layer 406a, the second The gate electrode layer 406b, the second gate electrode layer 406c, and the second gate electrode layer 405d can be etched to have a desired tapered shape. Further, the taper shape can control the angle and the like depending on the shape of the mask. As the etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ or CCl ₄ , a fluorine-based gas typified by CF ₄ , CF ₅ , SF ₆ or NF _3, or O ₂ Can be used as appropriate. In the present embodiment, CF _5, Cl etched second conductive film by using the _2, an etching gas consisting of O _2, first using an etching gas comprising a continuously CF _5, Cl ₂ The conductive film is etched.

  Next, a resist mask is formed by photolithography, and an impurity element imparting n-type conductivity is reduced in concentration to the semiconductor layers 403a, 403b, and 403c by ion doping or ion implantation. In addition, an n-type impurity region 443a, an n-type impurity region 443b, and an n-type impurity region 443c are formed. As the impurity element imparting n-type conductivity, an element belonging to Group 15 may be used. For example, phosphorus (P) or arsenic (As) is used.

  Next, a resist mask is formed by a photolithography method, and an impurity element imparting p-type conductivity is added to the semiconductor layer 403d, so that a p-type impurity region 410 and a channel formation region are formed. For example, boron (B) is used as the impurity element imparting P-type.

  Next, the gate insulating layer, the first gate electrode layer 405a, the first gate electrode layer 405b, the first gate electrode layer 405c, the first gate electrode layer 405d, the second gate electrode layer 406a, and the second An insulating layer is formed so as to cover the gate electrode layer 406b, the second gate electrode layer 406c, and the second gate electrode layer 405d. The insulating layer may be a single layer or a layer containing an inorganic material such as silicon, silicon oxide or silicon nitride, or an organic material such as an organic resin by a known means (plasma CVD method or sputtering method). It is formed by stacking. Next, the insulating layer is selectively etched by anisotropic etching mainly in the vertical direction, so that the first gate electrode layer 405a, the first gate electrode layer 405b, the first gate electrode layer 405c, and The first gate electrode layer 405d, the second gate electrode layer 406a, the second gate electrode layer 406b, the second gate electrode layer 406c, and an insulating layer in contact with the side surface of the second gate electrode layer 405d (also referred to as a sidewall) ) 407a, insulating layer 407b, insulating layer 407c, and insulating layer 407d are formed. At the same time as the formation of the insulating layers 407a, 407b, 407c, and 407d, the gate insulating layer is also etched, so that the insulating layers 404a, 404b, 404c, and 404d are formed. The insulating layer 404a, the insulating layer 404b, and the insulating layer 404c are used as doping masks when an LDD (Lightly Doped Drain) region is formed later.

  Next, an impurity imparting n-type conductivity to the semiconductor layer 403a, the semiconductor layer 403b, and the semiconductor layer 403c by using a resist mask formed by a photolithography method and the insulating layer 404a, the insulating layer 404b, and the insulating layer 404c as a mask. By adding an element, a low concentration n-type impurity region (also referred to as an LDD region) 408a, a low concentration n-type impurity region 408b, a low concentration n-type impurity region 408c, a high concentration impurity region 409a, a high concentration impurity region 409b, a high concentration An impurity region 409c is formed (see FIG. 9C). The concentrations of the impurity elements contained in the low-concentration n-type impurity region 408a, the low-concentration n-type impurity region 408b, and the low-concentration n-type impurity region 408c are the impurities in the high-concentration impurity region 409a, the high-concentration impurity region 409b, and the high-concentration impurity region 409c. Lower than elemental concentration.

  In order to form the LDD region, the gate electrode has a stacked structure of two or more layers, and the gate electrode is subjected to taper etching or anisotropic etching, and the lower conductive layer constituting the gate electrode is used as a mask. There are a technique to use and a technique to use the insulating layer of the sidewall as a mask. A thin film transistor formed by using the former method has a structure in which an LDD region is disposed so as to overlap a gate electrode with a gate insulating film interposed therebetween. Since the etching is used, it is difficult to control the width of the LDD region, and the LDD region may not be formed unless the etching process is performed well. On the other hand, the latter method using the sidewall insulating layer as a mask is easier to control the width of the LDD region than the former method, and the LDD region can be formed reliably.

    In order to activate the impurity element, heat treatment, intense light irradiation, or laser light irradiation may be performed. Simultaneously with activation, plasma damage to the gate insulating layer and plasma damage to the interface between the gate insulating layer and the semiconductor layer can be recovered.

    Next, an insulating layer 411 containing hydrogen is formed as a passivation film. The insulating layer 411 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm using a plasma CVD method or a sputtering method. The insulating layer 411 is not limited to a silicon nitride film, and may be a silicon nitride oxide (SiNO) film using plasma CVD, or an insulating film containing other silicon may be used as a single layer or a stacked structure.

    Further, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in a nitrogen atmosphere to perform a step of hydrogenating the semiconductor layer. Preferably, it carries out at 400-500 degreeC. This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the insulating layer 411.

    The insulating layer 411 includes silicon nitride, silicon oxide, silicon oxynitride (SiON), silicon nitride oxide (SiNO), aluminum nitride (AlN), aluminum oxynitride (AlON), and aluminum nitride oxide having a nitrogen content higher than the oxygen content. (AlNO) or aluminum oxide, diamond-like carbon (DLC), and a material selected from substances including a nitrogen-containing carbon film (CN). In addition, a skeleton structure is formed by a bond of silicon (Si) and oxygen (O), and at least one of a material containing at least hydrogen as a substituent, or fluorine, an alkyl group, or an aromatic hydrocarbon as a substituent. You may use the material which has.

  Next, an insulating layer 412 which serves as an interlayer insulating layer is formed (see FIG. 9D). In the present invention, an interlayer insulating film provided for planarization is required to have high heat resistance and insulation and a high planarization rate. As a method for forming such an insulating layer, a coating method typified by a spin coating method is preferably used.

  In this embodiment mode, a siloxane resin is used as a material for the insulating layer 412. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  The insulating layer 412 can employ dip, spray coating, doctor knife, roll coater, curtain coater, knife coater, CVD method, vapor deposition method, and the like. The insulating layer 109 may be formed by a droplet discharge method. When the droplet discharge method is used, the material liquid can be saved. Further, a method capable of transferring or drawing a pattern, such as a droplet discharge method, for example, a printing method (a method for forming a pattern such as screen printing or offset printing) or the like can be used. Spin coating or an inorganic material may be used. In that case, silicon oxide, silicon nitride, or silicon oxynitride may be used.

  The insulating layer 412 can be formed using an inorganic material (silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide PSG (phosphorus glass), BPSG (phosphorus glass)) as long as it has high heat resistance and good planarity in addition to the siloxane resin. Phosphorus glass, alumina film, etc.), photosensitive or non-photosensitive organic materials (organic resin materials) (polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, etc.), low-k materials with low dielectric constant A film made of one kind or a plurality of kinds of the above, or a laminate of these films can be used.

    Next, contact holes (openings) reaching the semiconductor layers are formed in the insulating layers 412 and 411 using a mask made of a resist.

    A wiring layer 413a, a wiring layer 413b functioning as a source electrode layer or a drain electrode layer which are electrically connected to a part of the impurity region which is each source region or drain region by forming a conductive film and etching the conductive film; A wiring layer 414a, a wiring layer 414b, a wiring layer 415a, a wiring layer 415b, and a wiring layer 415c are formed. The wiring layer 413a, the wiring layer 413b, the wiring layer 414a, the wiring layer 414b, the wiring layer 415a, the wiring layer 415b, and the wiring layer 415c are formed in a desired shape after a conductive film is formed by a PVD method, a CVD method, an evaporation method, or the like. It can be formed by etching. Further, the conductive layer can be selectively formed at a predetermined place by a droplet discharge method, a printing method, an electroplating method, or the like. Furthermore, a reflow method or a damascene method may be used. The material of the wiring layer 413a, the wiring layer 413b, the wiring layer 414a, the wiring layer 414b, the wiring layer 415a, the wiring layer 415b, and the wiring layer 415c is Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al , Ta, Mo, Cd, Zn, Fe, Ti, Si, Ge, Zr, Ba or the like, or an alloy thereof, or a metal nitride thereof. Moreover, it is good also as these laminated structures. In this embodiment, after Ti, Al, and Ti are stacked, patterning is performed in a desired shape to form a wiring layer 413a, a wiring layer 413b, a wiring layer 414a, a wiring layer 414b, a wiring layer 415a, a wiring layer 415b, and a wiring layer. 415c is formed. Further, the wiring layer 414a and the wiring layer 414b also function as a first conductive layer included in the memory element.

  Through the above steps, an n-type thin film transistor 416a and an n-type thin film transistor 416b to be connected to a memory element later, and an n-type thin film transistor 417a and a p-type thin film transistor 417b to be connected to a conductive layer that later functions as an antenna are completed. (See FIG. 10A).

    Without being limited to this embodiment mode, the thin film transistor may have a single gate structure in which one channel formation region is formed, a double gate structure in which two channel formation regions are formed, or a triple gate structure in which three channel formation regions are formed. The thin film transistor in the peripheral driver circuit region may have a single gate structure, a double gate structure, or a triple gate structure. A silicide layer may be formed in one or both of the source and drain regions. As a material for the silicide layer, nickel, tungsten, molybdenum, cobalt, platinum, or the like can be used.

    Note that not only the method for manufacturing the thin film transistor described in this embodiment mode, but also a top gate type (planar type, forward stagger type), a bottom gate type (reverse stagger type), or a gate insulating film above and below the channel region. The present invention can also be applied to a dual gate type or other structure having two gate electrode layers arranged.

    An insulating layer (also referred to as a partition wall or a bank) 420 is formed with openings in part of the wiring layers 414a, 414b, and 415a. As the insulating layer 420, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, other inorganic insulating materials, acrylic acid, methacrylic acid and derivatives thereof, polyimide, aromatic, Heat-resistant polymers such as polyamidopolyamides, polybenzimidazole, or inorganic siloxanes containing Si-O-Si bonds among silicon, oxygen, and hydrogen compounds, and hydrogen bonded to silicon is methyl or phenyl. An insulating material of organosiloxane substituted with such an organic group can be used. Further, a resin material such as a vinyl resin such as polyvinyl alcohol or polyvinyl butyral, an epoxy resin, a phenol resin, a novolac resin, an acrylic resin, a melamine resin, or a urethane resin is used. Alternatively, an organic material such as benzocyclobutene, parylene, flare, polyimide, a compound material made by polymerization of a siloxane polymer, a composition material containing a water-soluble homopolymer and a water-soluble copolymer, or the like may be used. As a manufacturing method, a vapor deposition method such as a plasma CVD method or a thermal CVD method, or a sputtering method can be used. Alternatively, a droplet discharge method or a printing method (a method for forming a pattern such as screen printing or offset printing) can be used. A TOF film or an SOG film obtained by a coating method can also be used.

    Further, after a conductive layer, an insulating layer, or the like is formed by discharging a composition by a droplet discharge method, the surface may be flattened by pressing with a pressure in order to improve the flatness. As a pressing method, the surface of the roller-like object may be scanned to reduce unevenness, or the surface may be pressed vertically with a flat plate-like object. A heating step may be performed when pressing. Alternatively, the surface may be softened or melted with a solvent or the like, and the surface irregularities may be removed with an air knife. Further, polishing may be performed using a CMP method. This step can be applied when the surface is flattened when unevenness is generated by the droplet discharge method.

    An insulating layer 421 and a conductive layer 422 are stacked over the wiring layer 414a and the wiring layer 414b. In addition, a wiring layer 425 is formed over the wiring layer 415a in the same process as the conductive layer 422.

    The insulating layer 421 is formed of an organic insulator, an organic compound whose conductivity is changed by an electric action or an optical action, an inorganic insulator, or a layer formed by mixing an organic compound and an inorganic compound. The insulating layer 421 may be a single layer or a stack of a plurality of layers. Alternatively, a mixed layer of an organic compound and an inorganic compound and a layer formed of an organic compound whose conductivity is changed by another electric action or optical action may be provided.

    As the inorganic insulator that can form the insulating layer 421, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like can be used.

    As an organic insulator that can form the insulating layer 421, an organic resin typified by polyimide, acrylic, polyamide, benzocyclobutene, epoxy, or the like can be used.

As the organic compound that can form the insulating layer 421 and whose conductivity is changed by an electric action or an optical action, an organic compound material having a high hole-transport property or an organic compound material having a high electron-transport property can be used. Can be used.

As an organic compound material having a high hole-transport property, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD), 4,4′-bis [ N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD) or 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: TDATA) ), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) and 4,4′-bis (N- (4- (N, N-di-m-tolylamino) phenyl) -N-phenylamino) biphenyl (abbreviation: DNTPD) and other aromatic amine-based compounds (that is, having a benzene ring-nitrogen bond) and phthalocyanines (abbreviation: H ₂ Pc), copper phthalonitrile Cyanine (abbreviation: CuPc), or vanadyl phthalocyanine (abbreviation: VOPc), and the phthalocyanine compound and the like can be used. The substances mentioned here are mainly substances having a hole mobility of 10 ⁻⁶ cm ² / Vs or higher. Note that other than the above substances, any substance that has a property of transporting more holes than electrons may be used.

Note that in the case where a mixed layer of an organic compound and an inorganic compound is provided, it is preferable to mix an organic compound material having a high hole-transport property and an inorganic compound material that easily receives electrons. By adopting such a configuration, many hole carriers are generated in an organic compound which has essentially no inherent carrier, and exhibits extremely excellent hole injection / transport properties. As a result, the organic compound layer can obtain excellent conductivity.

  As an inorganic compound material that easily receives electrons, a metal oxide, metal nitride, or metal oxynitride of a transition metal in any of Groups 4 to 12 of the periodic table can be used. Specifically, titanium oxide (TiOx), zirconium oxide (ZrOx), vanadium oxide (VOx), molybdenum oxide (MoOx), tungsten oxide (WOx), tantalum oxide (TaOx), hafnium oxide (HfOx), niobium oxide (NbOx), cobalt oxide (Cox), rhenium oxide (ReOx), ruthenium oxide (RuOx), zinc oxide (ZnO), nickel oxide (NiOx), copper oxide ( CuOx) or the like can be used. Further, although oxides are given as specific examples here, these nitrides and oxynitrides may of course be used.

As an organic compound material having a high electron transporting property, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [ h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), etc., and a metal complex having a quinoline skeleton or a benzoquinoline skeleton Materials can be used. In addition, bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) ₂ ) and other materials such as metal complexes having an oxazole-based or thiazole-based ligand can also be used. In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (P-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5- ( 4-biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2, 4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), and the like can be used. The substances mentioned here are mainly substances having an electron mobility of 10 ⁻⁶ cm ² / Vs or higher. Note that other than the above substances, any substance that has a property of transporting more electrons than holes may be used.

Note that in the case of providing a mixed layer of an organic compound and an inorganic compound, it is preferable to mix an organic compound material having a high electron-transport property and an inorganic compound material that easily gives electrons. By adopting such a structure, many electron carriers are generated in an organic compound that has essentially no intrinsic carrier, and exhibits extremely excellent electron injecting and transporting properties. As a result, the organic compound layer can obtain excellent conductivity.

  As the inorganic compound material that easily gives electrons, alkali metal oxides, alkaline earth metal oxides, rare earth metal oxides, alkali metal nitrides, alkaline earth metal nitrides, and rare earth metal nitrides can be used. Specifically, lithium oxide (LiOx), strontium oxide (SrOx), barium oxide (BaOx), erbium oxide (ErOx), sodium oxide (NaOx), lithium nitride (LiNx), magnesium nitride (MgNx), calcium nitride (CaNx), yttrium nitride (YNx), lanthanum nitride (LaNx), or the like can be used.

  Furthermore, as the inorganic compound material, any inorganic compound material that easily receives electrons from an organic compound or inorganic compound material that easily gives electrons to an organic compound may be used. Aluminum oxide (AlOx), gallium oxide (GaOx), silicon In addition to oxide (SiOx), germanium oxide (GeOx), indium tin oxide (ITO), and the like, various metal oxides, metal nitrides, or metal oxynitrides can be used.

  In addition, when the insulating layer 421 is formed of a compound selected from metal oxides or metal nitrides and a compound having a high hole-transport property, the steric hindrance is further large (in contrast to the planar structure, the spatial spread is increased. It is also possible to add a compound having a structure having As the compound having a large steric hindrance, 5,6,11,12-tetraphenyltetracene (abbreviation: rubrene) is preferable. However, besides this, hexaphenylbenzene, t-butylperylene, 9,10-di (phenyl) anthracene, coumarin 545T, and the like can also be used. In addition, dendrimers and the like are also effective.

Furthermore, 4-dicyanomethylene-2-methyl-6- (1,1,7) is formed between a layer formed of an organic compound material having a high electron-transport property and an organic compound material layer having a high hole-transport property. , 7-tetramethyljulolidyl-9-enyl) -4H-pyran (abbreviation: DCJT), 4-dicyanomethylene-2-t-butyl-6- (1,1,7,7-tetramethyljulolidyl) -9-enyl) -4H-pyran, periflanthene, 2,5-dicyano-1,4-bis (10-methoxy-1,1,7,7-tetramethyljulolidyl-9-enyl) benzene, N, N'- dimethyl quinacridone (abbreviation: DMQd), coumarin 6, coumarin 545T, tris (8-quinolinolato) aluminum (abbreviation: Alq _3), 9,9'-bianthryl, 9,10-diphenyl anthracene (abbreviation : DPA) and 9,10-bis (2-naphthyl) anthracene (abbreviation: DNA), 2,5,8,11-tetra -t- butyl perylene (abbreviation: TBP) a light-emitting substance may be provided, such as.

For the insulating layer 421, a material whose electrical resistance changes by an optical action can be used. For example, a conjugated polymer doped with a compound that generates an acid by absorbing light (a photoacid generator) can be used. As the conjugated polymer, polyacetylenes, polyphenylene vinylenes, polythiophenes, polyanilines, polyphenylene ethynylenes, and the like can be used. As the photoacid generator, arylsulfonium salts, aryliodonium salts, o-nitrobenzyl tosylate, arylsulfonic acid p-nitrobenzyl esters, sulfonylacetophenones, Fe-allene complex PF ₆ salts, and the like can be used. .

  The insulating layer 421 can be formed by an evaporation method, an electron beam evaporation method, a sputtering method, a CVD method, or the like. Moreover, the mixed layer containing an organic compound and an inorganic compound can be formed by simultaneously forming the respective materials. The co-evaporation method using resistance heating evaporation, the co-evaporation method using electron beam evaporation, and resistance heating. It can be formed by a combination of the same or different methods such as co-evaporation by vapor deposition and electron beam vapor deposition, film formation by resistance heating vapor deposition and sputtering, and film formation by electron beam vapor deposition and sputtering. As another formation method, a spin coating method, a sol-gel method, a printing method, a droplet discharge method, or the like may be used, or the insulating layer 421 may be formed by combining these methods.

Note that the insulating layer 421 is formed to a thickness at which the conductivity of the memory element is changed by an electric action or an optical action.

  The conductive layer 422 and the wiring layer 425 can be formed using the same material as the wiring layer 414a and the wiring layer 414b and can be formed in a similar process. In this embodiment mode, data is written to the memory element by applying an electrical action or an optical action. When data is written by an optical action, the wiring layer 414a and the wiring layer 414b or the conductive layer is written. One or both of the 422 are provided so as to have a light-transmitting property. The light-transmitting conductive layer is formed using a transparent conductive material, or is formed with a thickness that allows light to pass even if it is not a transparent conductive material. As the transparent conductive material, other light-transmitting oxide conductive materials such as indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), gallium-doped zinc oxide (GZO), and the like are used. Is possible. Indium tin oxide containing ITO and silicon oxide (hereinafter referred to as ITSO) or indium oxide containing silicon oxide may be mixed with 2 to 20% zinc oxide (ZnO).

  The memory element 424a is formed by stacking an insulating layer 421 and a conductive layer 422 over a wiring layer 414a, and the memory element 424b is formed by stacking an insulating layer 421 and a conductive layer 422 over the wiring layer 414b. . In addition, an insulating layer 423 which covers the conductive layer 422 and functions as a protective film is formed (see FIG. 10B). In addition, the wiring layer 414a and the wiring layer 414b in which the memory element 424a and the memory element 424b are formed are connected to a source region or a drain region of each of the thin film transistors 416a and 416b. That is, each memory element is connected to one thin film transistor. In addition, although the insulating layer 421 is formed over the entire surface so as to cover the wiring layer 414a, the wiring layer 414b, and the insulating layer 420, it may be selectively formed in each memory element.

    As a material for the wiring layer 414a, the wiring layer 414b, and the conductive layer 422, an element or a compound having high conductivity is used. In this embodiment, a material whose crystal state, conductivity, or shape is changed by an electric action or an optical action is used for the material of the insulating layer 421. Since the conductivity of the memory element having the above configuration changes before and after voltage application, two values corresponding to “initial state” and “after conductivity change” can be stored.

The insulating layer 423 is formed using silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, or other inorganic insulating materials, acrylic acid, methacrylic acid, and derivatives thereof, polyimide, aromatic, Heat-resistant polymers such as polyamide and polybenzimidazole, or inorganic siloxanes containing Si-O-Si bonds among compounds consisting of silicon, oxygen, and hydrogen, and hydrogen bonded to silicon is like methyl or phenyl An insulating material of organosiloxane substituted with an organic group can be used. Further, a resin material such as a vinyl resin such as polyvinyl alcohol or polyvinyl butyral, an epoxy resin, a phenol resin, a novolac resin, an acrylic resin, a melamine resin, or a urethane resin is used. Alternatively, an organic material such as benzocyclobutene, parylene, flare, polyimide, a compound material made by polymerization of a siloxane polymer, a composition material containing a water-soluble homopolymer and a water-soluble copolymer, or the like may be used. As a manufacturing method, a vapor deposition method such as a plasma CVD method or a thermal CVD method, or a sputtering method can be used. Alternatively, a droplet discharge method or a printing method (a method for forming a pattern such as screen printing or offset printing) can be used. A TOF film or an SOG film obtained by a coating method can also be used. Further, a carbon film or a DLC film may be used. Since the DLC film can be formed in a temperature range from room temperature to 100 ° C., even if the insulating layer 421 is a material having low heat resistance, it can be easily formed upward. The DLC film is formed by a plasma CVD method (typically, an RF plasma CVD method, a microwave CVD method, an electron cyclotron resonance (ECR) CVD method, a hot filament CVD method, etc.), a combustion flame method, a sputtering method, or an ion beam evaporation method. It can be formed by laser vapor deposition. The reaction gas used for film formation was hydrogen gas and a hydrocarbon-based gas (for example, CH ₄ , C ₂ H ₂ , C ₆ H _6, etc.), ionized by glow discharge, and negative self-bias was applied. Films are formed by accelerated collision of ions with the cathode. The CN film may be formed using C ₂ H ₄ gas and N ₂ gas as the reaction gas. The DLC film has a high blocking effect against oxygen.

  In this embodiment, in the above structure, a rectifying element may be provided between the wiring layer 414a, the wiring layer 414b, and the insulating layer 421. The element having a rectifying property is a transistor or a diode in which a gate electrode and a drain electrode are connected. Thus, by providing a diode having a rectifying property, current flows only in one direction, so that an error is reduced and a read margin is improved. Note that the element having a rectifying property may be provided between the insulating layer 421 and the conductive layer 422.

    Through the above steps, the thin film circuit portion 430 is formed on the substrate 400.

  Next, the insulating layer is etched by a photolithography method so that the separation layer 401 is exposed, so that an opening 426a and an opening 426b are formed (FIG. 11A).

Next, an etchant is introduced into the opening 426a and the opening 426b, and the separation layer 401 is removed (FIG. 11B). As the etchant, a gas or liquid containing halogen fluoride or an interhalogen compound is used. For example, chlorine trifluoride (ClF ₃ ) is used as a gas containing halogen fluoride. Then, the thin film circuit portion 430 is peeled from the substrate 400. Note that a part of the peeling layer 401 may be left without being removed. By doing so, the processing time can be shortened.

  The substrate 400 from which the thin film circuit portion 430 has been peeled is preferably reused for cost reduction. As shown in Embodiment Mode 1, one surface of the thin film circuit portion 430 is adhered to the transfer substrate 445 and completely peeled from the substrate 400, and the wiring layer 425 of the thin film circuit portion 430 is not exposed. A first substrate 427 is bonded to the surface of the insulating layer 402a. (See FIGS. 11B and 12A.)

    Next, the insulating layer 428 is formed by a printing method. Various printing methods (screen (stencil) printing, offset (lithographic printing) printing, letterpress printing, gravure printing (intaglio printing), etc. Screen printing is used in this embodiment. Wire mesh (mesh) 431 and mask A screen printing plate having an emulsion 442 provided on the frame is provided on the insulating layer 423. Next, a composition (paste) 432 is provided on the screen printing plate, and the composition (paste) is formed using a squeegee 433, a roller, or the like. As a result, the composition (paste) can be applied and printed on the insulating layer 423. Note that the paste may be spread on the screen printing plate with a scraper before the paste is extruded with a squeegee or a roller. The insulating layer 428 having the opening 429 is formed by drying and baking the composition (paste) applied by printing. Doo can (see FIG. 12 (B).).

    Next, a conductive layer 435 functioning as an antenna is formed by a printing method. In this embodiment, before the conductive layer 435 is formed, pretreatment for controlling wettability of the conductive layer 435 with respect to the composition in the formation region is performed. The degree of wettability may be set as appropriate depending on the line width, pattern shape, and film thickness of the conductive layer to be formed, and the wettability can be controlled by the following process.

    The wettability of the solid surface is affected by the surface condition. When a substance having low wettability is formed with respect to the liquid composition, the surface thereof becomes a region with low wettability with respect to the liquid composition (hereinafter also referred to as a low wettability region). On the other hand, when a highly wettable substance is formed, the surface thereof becomes a highly wettable region (hereinafter also referred to as a highly wettable region) with respect to the liquid composition. In the present invention, the treatment of controlling the wettability of the surface is to make the adhesion region of the liquid composition suitable for forming a desired shape of the liquid composition.

    The degree of wettability also affects the value of the contact angle. A region where the contact angle of the liquid composition is large is a region with lower wettability (hereinafter also referred to as a low wettability region), and a region with a small contact angle is a region with high wettability (hereinafter also referred to as a high wettability region). It becomes. When the contact angle is large, the liquid composition having fluidity does not spread on the surface of the region and repels the composition, so that the surface is not wetted. However, when the contact angle is small, the composition has fluidity on the surface. Because it spreads out and wets the surface well. Therefore, regions having different wettability also have different surface energies. The surface energy of the surface in the region with low wettability is small, and the surface energy at the surface of the region with high wettability is large.

First, a method of forming a wettability control substance and controlling so as to reduce the wettability of the surface of the formation region will be described. As such a wettability control substance, a substance containing a fluorocarbon group (fluorocarbon chain) or a substance containing a silane coupling agent can be used. The silane coupling agent is represented by a chemical formula of Rn—Si—X _(4-n) (n = 1, 2, 3). Here, R is a substance containing a relatively inert group such as an alkyl group. X is a hydrolyzable group such as halogen, methoxy group, ethoxy group or acetoxy group, which can be bonded by condensation with a hydroxyl group on the substrate surface or adsorbed water.

Further, as a representative example of the silane coupling agent, wettability can be further reduced by using a fluorine-based silane coupling agent (fluoroalkylsilane (FAS)) having a fluoroalkyl group in R. R of FAS has a structure represented by (CF ₃ ) (CF ₂ ) _x (CH ₂ ) _y (x: an integer of 0 or more and 10 or less, y: an integer of 0 or more and 4 or less), and a plurality of R Alternatively, when X is bonded to Si, R and X may all be the same or different. As typical FAS, fluoroalkylsilanes (hereinafter also referred to as FAS) such as heptadecafluorotetrahydrodecyltriethoxysilane, heptadecafluorotetrahydrodecyltrichlorosilane, tridecafluorotetrahydrooctyltrichlorosilane, and trifluoropropyltrimethoxysilane. ).

    As the wettability control substance, a substance having an alkyl group and not having a fluorocarbon chain in R of the silane coupling agent can be used. For example, octadecyltrimethoxysilane or the like can be used as the organic silane.

  Solvents of the solution containing the wettability control substance include n-pentane, n-hexane, n-heptane, n-octane, n-decane, dicyclopentane, benzene, toluene, xylene, durene, indene, tetrahydronaphthalene, deca Hydrocarbon solvents such as hydronaphthalene and squalane or tetrahydrofuran are used.

  In addition, as an example of a wettability control substance that forms a low wettability region, a material having a fluorocarbon chain (fluorine-based resin) can be used. Examples of fluorine resins include polytetrafluoroethylene (PTFE; tetrafluoroethylene resin), perfluoroalkoxyalkane (PFA; tetrafluoroethylene perfluoroalkyl vinyl ether copolymer resin), and perfluoroethylene propene copolymer (PFEP; four fluoropolymer). Ethylene-hexafluoropropylene copolymer resin), ethylene-tetrafluoroethylene copolymer (ETFE; tetrafluoroethylene-ethylene copolymer resin), polyvinylidene fluoride (PVDF; vinylidene fluoride resin), polychlorotrifluoroethylene (PCTFE; trifluoroethylene chloride resin), ethylene-chlorotrifluoroethylene copolymer (ECTFE; trifluoroethylene chloride-ethylene copolymer resin), polytetrafluoroethylene-perfluorodioxide Rukoporima (TFE / PDD), polyvinyl fluoride (PVF; a vinyl fluoride resin), or the like can be used.

In addition, when an inorganic material or an organic material is treated with CF ₄ plasma or the like, wettability can be reduced. For example, a material obtained by mixing a water-soluble resin such as polyvinyl alcohol (PVA) in a solvent such as H ₂ O as an organic material can be used. Moreover, you may use combining PVA and another water-soluble resin. Organic material (organic resin material) (polyimide, acrylic) or skeleton structure is composed of a bond of silicon (Si) and oxygen (O), a material containing at least hydrogen as a substituent, or fluorine, alkyl group as a substituent, Alternatively, a material having at least one of aromatic hydrocarbons may be used.

    In this embodiment mode, FAS is formed as the wettability control substance 434 over the insulating layer 428 and the wiring layer 425 by a spin coating method, and the wettability of the conductive layer formation region is adjusted. This wettability is with respect to a composition containing a liquid conductive material constituting a conductive layer formed in a later step. Further, as a wettability control substance 434, a substrate is sealed in a sealed container containing a FAS reagent, and heated at 50 to 200 degrees, preferably 100 to 200 degrees for 5 minutes or more, so that the FAS is insulated layers 428 and wiring layers 425. It can also be formed by adsorbing to the surface. The wettability controlling substance 434 may not be continuously formed as a film depending on the forming method. Further, the wettability control substance 434 may be selectively formed in a region where the conductive layer 435 is formed and in the vicinity thereof. After the conductive layer 435 is formed into a desired pattern, the remaining wettability control substance may be left, or unnecessary portions may be removed. The removal may be performed by ashing or etching with oxygen or the like.

    A conductive layer 435 is formed by a printing method in a region in which wettability is controlled by the wettability control substance 434. Various printing methods (screen (stencil) printing, offset (lithographic printing) printing, relief printing, gravure printing (intaglio printing), or a droplet discharge method can be used. In this embodiment, a screen printing method is used. Similarly to 428, a screen printing plate having a metal mesh (mesh) 437 and a mask emulsion 436 provided on a frame is provided on the insulating layer 428 and the wiring layer 425. Next, a composition (paste) 438 is provided on the screen printing plate. And the composition (paste) 438 is extruded to the opening 429 using a squeegee 439, a roller, etc. As a result, the composition (paste) can be applied and printed on the wiring layer 425. The paste may be spread on a screen printing plate with a scraper before extruding the paste with a composition applied by printing (paste). By drying and baking, the conductive layer 435 can be formed (see FIG. 13). The above control of wettability is performed on the conductive layer and the insulating layer by a printing method or a droplet discharge method in this specification. If formed, it can be used.

    An insulating layer 440 is formed so as to cover the conductive layer 435 and the thin film circuit portion 330, and sealed with a flexible substrate 441 to manufacture a semiconductor device (see FIG. 14). In this embodiment, the insulating layer 440 is formed by a screen printing method as in the case of the conductive layer 435.

    As described above, according to the present invention, a high-performance and highly reliable semiconductor device can be manufactured at low cost with high yield.

(Embodiment 3)
In this embodiment, another example of a semiconductor device including the memory device described in Embodiment 2 will be described with reference to drawings.

  The semiconductor device described in this embodiment is characterized in that data can be read and written in a non-contact manner. A data transmission format is an electromagnetic which performs communication by mutual induction with a pair of coils arranged opposite to each other. There are roughly divided into a coupling system, an electromagnetic induction system that communicates using an induction electromagnetic field, and a radio system that communicates using radio waves, but any system may be used.

  Next, a structural example of a semiconductor device having a passive matrix memory device will be described with reference to FIGS.

  FIG. 15 illustrates a semiconductor device having a passive matrix memory device, in which a transistor 466a, a transistor 466b, a transistor 467a, and a transistor 467b are provided over a substrate 450, and an insulating layer 481 and an insulating layer 482 are provided above the transistor. A memory element 474a and a memory element 474b are provided, and a wiring layer 473 connected to the transistor 467a and the transistor 467b and a conductive layer 485 functioning as an antenna are provided over the wiring layer 480.

  The memory element 474a is formed by stacking an insulating layer 461a and a second conductive layer 472a over the first conductive layer 464 connected to the transistor 466b. The memory element 474b is insulated over the first conductive layer 464. A layer 461b and a second conductive layer 472b are stacked. In addition, an insulating layer 483 functioning as a protective film is formed so as to cover the second conductive layers 472a and 472b and the conductive layer 485, and an insulating layer 490 is provided over the insulating layer 483 and sealed with the substrate 491. In addition, the first conductive layer 464 in which the plurality of memory elements 474a and 474b are formed is connected to one source or drain electrode layer of the transistor 466b. That is, the memory element is connected to the same single transistor. In addition, the insulating layer 461a and the insulating layer 461b are provided with an insulating layer serving as a partition wall for separating the insulating layer for each memory element. When there is no concern about the influence of the electric field in the lateral direction in the adjacent memory element, It may be formed on the entire surface. Note that the memory elements 474a and 474b can be formed using any of the materials and manufacturing methods described in the above embodiment modes.

  Next, a structure example of a semiconductor device including an active matrix memory device in which a conductive layer functioning as an antenna is provided below a thin film circuit portion will be described with reference to FIGS.

  FIG. 16 illustrates a semiconductor device having an active matrix memory device. A transistor 516a, a transistor 516b, a transistor 517a, and a transistor 517b are provided over a substrate 541, and a memory element 524a and a memory element 524b are provided above the transistor. It has been. The wiring layer 523 connected to the transistors 517a and 517b is formed in a contact hole provided in the insulating layer and is electrically connected to a conductive layer 485 functioning as an antenna provided below the transistors 517a and 517b. The conductive layer 535b also functions as an antenna. One is an insulating layer 513 that functions as a protective film so as to cover the memory element 524a and the memory element 524b. The insulating layer 532 is provided over the insulating layer 513 and sealed with the substrate 500, and the other is sealed with the conductive layer 535a and the conductive layer. An insulating layer 540 is formed to cover the layer 535 b and is sealed with the substrate 541.

  Since it is an active matrix type, each memory element is connected to one transistor as in the semiconductor device described in Embodiment 2. Note that the memory elements 524a and 524b can be formed using any of the materials and manufacturing methods described in the above embodiment modes.

  In this manner, a semiconductor device including a memory device and an antenna can be formed. In this embodiment mode, an element formation layer can be provided by forming a thin film transistor over a substrate, or by forming a field effect transistor over a substrate using a semiconductor substrate such as Si as the substrate. A layer may be provided. Alternatively, an SOI substrate may be used as a substrate, and an element formation layer may be provided thereover. In this case, the SOI substrate may be formed by using a method of bonding wafers or a method called SIMOX in which an insulating layer is formed inside by implanting oxygen ions into the Si substrate. A sensor connected to the transistor may be provided.

  The thin film circuit portion can be formed by vapor deposition, sputtering, CVD, printing, droplet discharge, or the like. Note that a different method may be used depending on each place. For example, a transistor that requires high-speed operation is provided by forming a semiconductor layer made of Si or the like on a substrate and then crystallizing it by heat treatment, and then forming a transistor that functions as a switching element above the element formation layer by a printing method or An organic transistor can be provided by a droplet discharge method.

  Note that a sensor connected to the transistor may be provided. Examples of the sensor include an element that detects temperature, humidity, illuminance, gas (gas), gravity, pressure, sound (vibration), acceleration, and other characteristics by physical or chemical means. The sensor is typically formed of a semiconductor element such as a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectric element, a transistor, a thermistor, or a diode.

Note that this embodiment can be freely combined with the above embodiment. In addition, the substrate 450, the substrate 491, the substrate 500, and the substrate 541 described in this embodiment mode are flexible substrates, which can be attached to the flexible substrate and installed. A semiconductor device having flexibility can be obtained. A flexible substrate is a film made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, paper made of a fibrous material, base film (polyester, polyamide, inorganic vapor deposition film, paper, etc.) And an adhesive synthetic resin film (acrylic synthetic resin, epoxy synthetic resin, etc.). The film is subjected to heat treatment and pressure treatment by thermocompression bonding. When the heat treatment and pressure treatment are performed, the film is either an adhesive layer provided on the outermost surface of the film or the A layer (not an adhesive layer) provided in the outer layer is melted by heat treatment and bonded by pressure. In addition, the substrate may be provided with an adhesive layer or may not be provided with an adhesive layer. The adhesive layer corresponds to a layer containing an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, or a resin additive.

    As described above, according to the present invention, a high-performance and highly reliable semiconductor device can be manufactured at low cost with high yield.

(Embodiment 4)
The configuration of the semiconductor device of this embodiment will be described with reference to FIG. As shown in FIG. 17, the semiconductor device 20 of the present invention has a function of communicating data without contact, and controls the power supply circuit 11, the clock generation circuit 12, the data demodulation / modulation circuit 13, and other circuits. A circuit 14, an interface circuit 15, a memory circuit 16, a data bus 17, an antenna (antenna coil) 18, a sensor 21, and a sensor circuit 22 are included.

  The power supply circuit 11 is a circuit that generates various power supplies to be supplied to each circuit inside the semiconductor device 20 based on the AC signal input from the antenna 18. The clock generation circuit 12 is a circuit that generates various clock signals to be supplied to each circuit inside the semiconductor device 20 based on the AC signal input from the antenna 18. The data demodulation / modulation circuit 13 has a function of demodulating / modulating data communicated with the reader / writer 19. The control circuit 14 has a function of controlling the memory circuit 16. The antenna 18 has a function of transmitting and receiving an electromagnetic field or a radio wave. The reader / writer 19 controls communication and control with the semiconductor device and processing related to the data. The semiconductor device is not limited to the above-described configuration, and may be a configuration in which other elements such as a power supply voltage limiter circuit and hardware dedicated to cryptographic processing are added.

  The memory circuit 16 includes a memory element in which an insulating layer or a phase change layer is sandwiched between a pair of conductive layers. Note that the memory circuit 16 may include only a memory element in which an insulating layer or a phase change layer is interposed between a pair of conductive layers, or may include a memory circuit having another structure. The memory circuit having another configuration corresponds to, for example, one or more selected from DRAM, SRAM, FRAM, mask ROM, PROM, EPROM, EEPROM, and flash memory.

  The sensor 21 is formed of a semiconductor element such as a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectric element, a transistor, a thermistor, or a diode. The sensor circuit 22 detects a change in impedance, reactance, inductance, voltage or current, performs analog / digital conversion (A / D conversion), and outputs a signal to the control circuit 14.

(Embodiment 5)
According to the present invention, a semiconductor device that functions as a processor chip (also referred to as a wireless chip, a wireless processor, a wireless memory, or a wireless tag) can be formed. The semiconductor device of the present invention has a wide range of uses. For example, banknotes, coins, securities, certificates, bearer bonds, packaging containers, books, recording media, personal items, vehicles, foods, clothing It can be used in health supplies, daily necessities, medicines and electronic devices.

  Banknotes and coins are money that circulates in the market, and include those that are used in the same way as money in a specific area (cash vouchers), commemorative coins, and the like. Securities refers to checks, securities, promissory notes, and the like, and can be provided with a processor chip 90 (see FIG. 18A). The certificate refers to a driver's license, a resident's card, and the like, and can be provided with a processor chip 91 (see FIG. 18B). The vehicles refer to vehicles such as bicycles, ships, and the like, and can be provided with a processor chip 97 (see FIG. 18C). Bearer bonds refer to stamps, gift cards, and various gift certificates. Packaging containers refer to wrapping paper such as lunch boxes, plastic bottles, and the like, and can be provided with a processor chip 93 (see FIG. 18D). Books refer to books, books, and the like, and can be provided with a processor chip 94 (see FIG. 18E). A recording medium refers to DVD software, a video tape, or the like, and can be provided with a processor chip 95 (see FIG. 18F). Personal belongings refer to bags, glasses, and the like, and can be provided with a processor chip 96 (see FIG. 18G). Foods refer to food products, beverages, and the like. Clothing refers to clothing, footwear, and the like. Health supplies refer to medical equipment, health equipment, and the like. Livingware refers to furniture, lighting equipment, and the like. Chemicals refer to pharmaceuticals, agricultural chemicals, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (TV receivers, flat-screen TV receivers), mobile phones, and the like.

  The semiconductor device of the present invention is fixed to an article by being mounted on a printed board, pasted on a surface, or embedded. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin, and is fixed to each article. Since the semiconductor device of the present invention realizes a small size, a thin shape, and a light weight, the design of the article itself is not impaired even after being fixed to the article. In addition, by providing the semiconductor device of the present invention in bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and if this authentication function is utilized, counterfeiting can be prevented. it can. In addition, by providing the semiconductor device of the present invention in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved.

  An example that can be applied to an object management or distribution system will be described with reference to FIG. Here, an example in which a processor chip is mounted on a product will be described. As shown in FIG. 21A, a processor chip 3402 is mounted on a beer bottle 3400 using a label 3401.

  The processor chip 3402 records basic items such as the date of manufacture, the place of manufacture, and the materials used. Such basic matters do not need to be rewritten, and therefore may be recorded using a non-rewritable memory element (memory) such as a mask ROM or the memory element of the present invention. The basic items such as the date of manufacture, the place of manufacture, and the materials used are information that consumers want to obtain accurately when purchasing a product. By recording such information in a non-rewritable storage element, it is possible to prevent tampering of information and the like, so that reliable and accurate information can be transmitted to consumers. In addition, the processor chip 3402 records individual items such as the delivery destination and delivery date and time of each beer bottle. For example, as shown in FIG. 21B, when the beer bottle 3400 flows by the belt conveyor 3412 and passes through the writer device 3413, each delivery destination and delivery date and time can be recorded. Such individual items may be recorded using a rewritable and erasable memory such as EEROM.

  When product information purchased from a delivery destination is transmitted to the distribution management center via the network, the writer device or a personal computer that controls the writer device calculates the delivery destination and delivery date based on the product information, and the processor A system that records on a chip should be constructed.

  Since delivery is performed for each case, a processor chip can be mounted for each case or for each of a plurality of cases, and individual items can be recorded.

  By installing a processor chip in such a product that can record a plurality of delivery destinations, it is possible to reduce the time required for manual input and to reduce input errors caused by the time. In addition, labor costs that are the most expensive in the field of logistics management can be reduced. Therefore, by implementing the processor, it is possible to carry out low-cost logistics management with few mistakes.

  Furthermore, application items such as foods suitable for beer and cooking methods using beer may be recorded at the delivery destination. As a result, it can serve as an advertisement for foods and the like, and the consumer's willingness to purchase can be enhanced. Such application items may be recorded using a rewritable and erasable memory such as EEROM. By mounting the processor chip in this manner, information that can be provided to the consumer can be increased, so that the consumer can purchase the product with peace of mind.

  Next, one mode of an electronic device in which the semiconductor device of the present invention is mounted will be described with reference to the drawings. An electronic device illustrated here is a mobile phone, which includes housings 2700 and 2706, a panel 2701, a housing 2702, a printed wiring board 2703, operation buttons 2704, and a battery 2705 (see FIG. 17B). The panel 2701 is detachably incorporated in the housing 2702, and the housing 2702 is fitted on the printed wiring board 2703. The shape and dimensions of the housing 2702 are changed as appropriate in accordance with the electronic device in which the panel 2701 is incorporated. A plurality of packaged semiconductor devices are mounted on the printed wiring board 2703, and the semiconductor device of the present invention can be used as one of them. The plurality of semiconductor devices mounted on the printed wiring board 2703 have any one function of a controller, a central processing unit (CPU), a memory, a power supply circuit, a sound processing circuit, a transmission / reception circuit, and the like.

  The panel 2701 is integrated with the printed wiring board 2703 through the connection film 2708. The panel 2701, the housing 2702, and the printed wiring board 2703 are housed in the housings 2700 and 2706 together with the operation buttons 2704 and the battery 2705. A pixel region 2709 included in the panel 2701 is arranged so as to be visible from an opening window provided in the housing 2700.

  As described above, the semiconductor device of the present invention is characterized in that it is small, thin, and lightweight, and the limited space inside the housings 2700 and 2706 of the electronic device can be effectively used due to the above characteristics. .

  In addition, since the semiconductor device of the present invention includes a memory element having a simple structure in which an insulating layer is sandwiched between a pair of conductive layers, an electronic device using an inexpensive semiconductor device can be provided. In addition, since the semiconductor device of the present invention can be easily integrated, an electronic device using the semiconductor device including a large-capacity memory circuit can be provided.

  In addition, a memory device included in the semiconductor device of the present invention writes data by an optical action or an electrical action, is nonvolatile, and can additionally write data. With the above feature, forgery due to rewriting can be prevented, and new data can be added and written. Therefore, an electronic device using a semiconductor device that achieves high functionality and high added value can be provided.

  Note that the housings 2700 and 2706 are examples of the appearance of a mobile phone, and the electronic device according to this embodiment can be changed into various modes depending on functions and uses.

The conceptual diagram explaining this invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 8A and 8B illustrate an application example of a semiconductor device of the invention. 8A and 8B illustrate an application example of a semiconductor device of the invention. 2A and 2B illustrate a structure of a droplet discharge device that can be applied to the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 8A and 8B illustrate an application example of a semiconductor device of the invention.

Claims (15)

    A semiconductor device comprising: a thin film circuit portion provided on a substrate; and a conductive layer electrically connected to the thin film circuit portion and continuously provided on the substrate and the thin film circuit portion. .     2. The method according to claim 1, further comprising: a layer containing a substance having a fluorocarbon group on the substrate and the thin film circuit portion; and the conductive layer on a layer containing the substance having the fluorocarbon group. Semiconductor device.     A thin film circuit portion provided on a first flexible substrate, electrically connected to the thin film circuit portion, and continuously on the first flexible substrate and the thin film circuit portion And a second flexible substrate which covers the thin film circuit portion and the conductive layer.     4. The conductive layer according to claim 3, wherein a layer containing a substance having a fluorocarbon group is formed on the first flexible substrate and the thin film circuit portion, and the layer containing the substance having the fluorocarbon group is formed on the conductive layer. A semiconductor device comprising a layer.     5. The semiconductor device according to claim 1, wherein the thin film circuit portion includes a memory device.     6. The semiconductor device according to claim 5, wherein the memory device includes an insulating layer containing an organic material. Install the thin film circuit on the substrate,
A semiconductor device is manufactured by attaching a composition containing a conductive material having fluidity to the substrate and the thin film circuit portion to form a conductive layer electrically connected to the thin film circuit portion. Method. Install the thin film circuit on the substrate,
A method for manufacturing a semiconductor device, comprising: printing a composition containing a conductive material on the substrate and the thin film circuit portion; and forming a conductive layer electrically connected to the thin film circuit portion.     9. The layer according to claim 7 or 8, wherein a layer containing a substance having a fluorocarbon group is formed on the substrate and the thin film circuit portion, and the conductive layer is formed on the layer containing the substance having a fluorocarbon group. A method for manufacturing a semiconductor device, comprising: forming a semiconductor device. A plurality of thin film circuit portions are formed on the substrate,
The thin film circuit portion is selectively peeled from the substrate and bonded onto a flexible substrate,
A conductive layer electrically connected to the thin film circuit portion is formed by attaching a composition containing a conductive material having fluidity on the flexible substrate and the thin film circuit portion. A method for manufacturing a semiconductor device. A plurality of thin film circuit portions are formed on the substrate,
The thin film circuit portion is selectively peeled from the substrate and bonded onto a flexible substrate,
Fabrication of a semiconductor device, wherein a composition containing a conductive material is printed on the flexible substrate and the thin film circuit portion, and a conductive layer electrically connected to the thin film circuit portion is formed. Method.     12. The method according to claim 10, wherein a layer containing a substance having a fluorocarbon group is formed on the flexible substrate and the thin film circuit portion, and the substance containing the substance having a fluorocarbon group is formed. A method for manufacturing a semiconductor device, wherein the conductive layer is formed on the substrate.     13. The thin film circuit portion is selectively peeled off from a flexible substrate using a marker formed on the flexible substrate according to claim 10. A method for manufacturing a semiconductor device.     14. The method for manufacturing a semiconductor device according to claim 13, wherein the marker is formed by irradiation with laser light. 14. The method for manufacturing a semiconductor device according to claim 13, wherein the marker is formed by a printing method.

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