JP2006237586A - Semiconductor device, electronic apparatus, and process for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is manufactured by simplifying the manufacturing process while enhancing utilization efficiency of material, and also to provide a display, its manufacturing technology, and a technique for forming the wiring pattern constituting these semiconductor devices and the display with desired profile and high controllability. <P>SOLUTION: Conductor layers having nodes are formed adjacently at a uniform interval. In the adjacent conductive layers, a liquid drop is ejected while shifting the central position in the length direction of wiring not to be aligned in the line width direction. Since the center of a liquid drop is shifted, maximum line width parts (maximum node) of the conductive layers do not adjoin and the conductive layers can be provided adjacently at a narrower interval. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to a semiconductor device, an electronic device, and a method for manufacturing the semiconductor device using a printing method.

A thin film transistor (hereinafter also referred to as “TFT”) and an electronic circuit using the thin film transistor are obtained by laminating various thin films such as a semiconductor, an insulator, and a conductor on a substrate and appropriately forming a predetermined pattern by a photolithography technique. It is manufactured. Photolithographic technology is a technology that uses a light to transfer a circuit pattern or other pattern formed on a transparent flat plate called a photomask onto a target substrate. It is widely used in the manufacturing process.

In the manufacturing process using the conventional photolithography technology, a multi-step process such as exposure, development, baking, and peeling is required only for handling a mask pattern formed using a photosensitive organic resin material called a photoresist. Become. Therefore, the manufacturing cost inevitably increases as the number of photolithography processes increases. In order to improve such problems, attempts have been made to manufacture TFTs by reducing the photolithography process (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 11-251259

The present invention reduces the number of photolithography processes in the manufacturing process of a TFT, an electronic circuit using the TFT, a semiconductor device formed by the TFT, and a display device, simplifies the manufacturing process, and has a large side exceeding 1 meter. An object of the present invention is to provide a technology capable of manufacturing a substrate with a large area at a low cost with high yield.

Another object of the present invention is to provide a technique that can stably form components such as wirings constituting the semiconductor device and the display device in a desired shape.

    In the present invention, an adjacent conductive layer, a wiring, or an insulating layer used as a mask layer for forming an adjacent conductive layer is divided into a liquid composition and a wettability controlled formation region several times. Then, it is solidified by firing, drying or the like to form a conductive layer or an insulating layer. When the composition is ejected in several times, droplets are not aggregated and a stable pattern shape without disconnection is obtained. The shapes of the conductive layer and the insulating layer formed in this way are stable because the droplets discharged later do not stay at the landing position due to the difference in wettability of the formation region, but move to a region with high wettability. Therefore, the obtained conductive layer, wiring, and mask layer have a shape having a node, and the line width has a plurality of line widths. Further, the line width changes continuously, and the maximum line width and the minimum line width are periodically repeated. Here, the maximum line width does not necessarily have to be constant throughout the wiring, and strictly speaking, each maximum line width indicates a local maximum value of the line width. Similarly, the minimum line width does not necessarily have to be constant for the entire wiring, and strictly speaking, each minimum line width indicates a local minimum value of the line width.

  In the present invention, conductive layers having a shape having nodes are formed adjacent to each other with a uniform interval. In the adjacent conductive layer, the discharge is performed while shifting in the length direction of the wiring so that the position of the center of the discharged droplet does not coincide with the line width direction. Since the centers of the droplets are shifted, the maximum portions (maximum values of the nodes) of the line widths of the conductive layers are not adjacent to each other, and can be provided adjacent to each other at a narrower interval.

  In addition, the conductive layer (wiring) or the insulating layer formed in the present invention has a portion where the film thickness differs not only in the side end portion but also in the film thickness direction, and has a concavo-convex shape reflecting droplets on the surface. This is because a liquid composition containing a conductive material or an insulating material is discharged and then solidified by drying or baking to form a conductive layer or an insulating layer. The same applies to the mask layer formed by using the present invention, and the mask layer has portions with different film thicknesses and has a concavo-convex shape on the surface. Therefore, a conductive layer or an insulating layer processed using such a mask layer also reflects the shape of the mask layer. The shape and size of the irregular shape on the surface varies depending on the viscosity of the liquid composition, the drying process when the solvent is removed and solidified.

    The wettability of the solid surface is affected by the surface condition. When a substance having low wettability is formed with respect to the liquid composition, the surface of the liquid composition becomes a region with low wettability with respect to the liquid composition (hereinafter also referred to as a low wettability region). When a highly wettable substance is formed, the surface thereof becomes a highly wettable region (hereinafter also referred to as a highly wettable region) with respect to the liquid composition. In the present invention, the treatment of controlling the wettability of the surface is to form regions having different wettability with respect to the liquid composition in the adhesion region of the liquid composition.

    A region having different wettability is a region having a difference in wettability with respect to a liquid composition, and a contact angle of the liquid composition is different. A region where the contact angle of the liquid composition is large is a region with lower wettability (hereinafter also referred to as a low wettability region), and a region with a small contact angle is a region with high wettability (hereinafter also referred to as a high wettability region). It becomes. When the contact angle is large, the liquid composition having fluidity does not spread on the surface of the region and repels the composition, so that the surface is not wetted. However, when the contact angle is small, the composition has fluidity on the surface. Because it spreads out and wets the surface well. Therefore, regions having different wettability also have different surface energies. The surface energy of the surface in the region with low wettability is small, and the surface energy at the surface of the region with high wettability is large.

  Note that in this specification, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. By using the present invention, a semiconductor device such as a multilayer wiring layer or a chip having a processor circuit (hereinafter also referred to as a processor chip) can be manufactured.

    The present invention can also be used for a display device that has a display function. The display device using the present invention includes an organic substance that emits light called electroluminescence (hereinafter also referred to as “EL”), or an organic substance. And a liquid crystal display device using a liquid crystal element having a liquid crystal material as a display element, and the like.

    One of the semiconductor devices of the present invention includes a first wiring having a plurality of line widths and a second wiring having a plurality of line widths, and side end portions of the first wiring and the second wiring are The first wiring and the second wiring are symmetric with respect to the central axis, and the distance between the first wiring and the second wiring is constant. Therefore, at least a part of the first wiring and the second wiring is bent when viewed from above, and the side end portions appear to have a wavy shape.

    One of the semiconductor devices of the present invention includes a first wiring whose line width is continuously changed and a second wiring whose line width is continuously changed. The side ends of the second wiring have a continuous wavy shape, the first wiring and the second wiring are axisymmetric with respect to the central axis, and the distance between the first wiring and the second wiring is It is constant.

    One of the semiconductor devices of the present invention includes a first wiring whose line width is periodically changed and a second wiring whose line width is periodically changed. The side ends of the second wiring have a wavy shape, the first wiring and the second wiring are symmetrical with respect to the central axis, and the distance between the first wiring and the second wiring is constant. is there.

    One embodiment of the semiconductor device of the present invention includes a gate electrode layer, a gate insulating layer, a semiconductor layer, a source electrode layer, and a drain electrode layer, and the source electrode layer and the drain electrode layer have a plurality of line widths. The side ends of the first wiring and the second wiring have a wavy shape, the source electrode layer and the drain electrode layer are axisymmetric with respect to the central axis, and the source electrode layer and the drain electrode layer The interval is constant.

    One embodiment of the semiconductor device of the present invention includes a gate electrode layer, a gate insulating layer, a semiconductor layer, a source electrode layer, and a drain electrode layer. The source electrode layer and the drain electrode layer have continuous line widths. The side edges of the source electrode layer and the drain electrode layer have a continuous wave shape, the source electrode layer and the drain electrode layer are axisymmetric with respect to the central axis, and the source electrode layer and the drain electrode The distance between the layers is constant.

    One embodiment of a semiconductor device of the present invention includes a gate electrode layer, a gate insulating layer, a semiconductor layer, a source electrode layer, and a drain electrode layer. The source electrode layer and the drain electrode layer have a line width periodically. The source electrode layer and the drain electrode layer have wavy shapes, the source electrode layer and the drain electrode layer are axisymmetric with respect to the central axis, and the source electrode layer, the drain electrode layer, The interval of is constant.

    According to one aspect of the semiconductor device of the present invention, a plurality of droplets having a center on a first line in a substrate surface ejected by a first ejection step of a plurality of droplets made of a composition containing a conductive material on a substrate. A first droplet and a plurality of third droplets having a center on a first line ejected between the first droplets by the second ejection step of the plurality of droplets; A first wiring line symmetrical with respect to one line, a plurality of second droplets having a center on a second line parallel to the first line ejected in the first ejection step, and A second line symmetric with respect to the second line, formed by a plurality of fourth liquid droplets having a center on the second line discharged between the second liquid droplets in the second discharge step; Wiring, and the distance between the first wiring and the second wiring is constant.

    In one embodiment of the method for manufacturing a semiconductor device of the present invention, a plurality of droplets having a center on a first line in a substrate plane are formed on a substrate by a first discharge step of a plurality of droplets made of a composition containing a conductive material. And a plurality of second droplets having a center on a second line parallel to the first line, respectively, and the first discharge step of the plurality of droplets results in the first By ejecting a plurality of third droplets having a center on the first line between the droplets, the first line having line symmetry with respect to the first line and having a plurality of line widths A plurality of fourth liquid droplets having a center on the second line are ejected between the conductive layer and the second liquid droplet, thereby being line symmetric with respect to the second line and the plurality of lines. A second conductive layer having a width is formed with a certain interval.

    In one embodiment of the method for manufacturing a semiconductor device of the present invention, a plurality of droplets having a center on a first line in a substrate plane are formed on a substrate by a first discharge step of a plurality of droplets made of a composition containing a conductive material. And a plurality of second droplets having a center on a second line parallel to the first line, respectively, and the first discharge step of the plurality of droplets results in the first By ejecting a plurality of third droplets having a center on the first line between the droplets, the first line is symmetrical with respect to the first line and the line width continuously changes. By ejecting a plurality of fourth droplets having a center on the second line between the one conductive layer and the second droplet, the line is symmetrical with respect to the second line, and the line The second conductive layer whose width is continuously changed is formed with a certain interval.

    In one embodiment of the method for manufacturing a semiconductor device of the present invention, a plurality of droplets having a center on a first line in a substrate plane are formed on a substrate by a first discharge step of a plurality of droplets made of a composition containing a conductive material. And a plurality of second droplets having a center on a second line parallel to the first line, respectively, and the first discharge step of the plurality of droplets results in the first By ejecting a plurality of third droplets having a center on the first line between the droplets, the first line is symmetrical with respect to the first line and the line width changes periodically. By ejecting a plurality of fourth droplets having a center on the second line between one conductive layer and the second droplet, the first layer is symmetrical with respect to the first line, and the line The second conductive layer whose width periodically changes is formed with a certain interval.

    In one embodiment of the method for manufacturing a semiconductor device of the present invention, a conductive film is formed over a substrate, and a plurality of droplets made of a composition containing a mask layer material are formed over the conductive film. A plurality of first droplets having a center on the first line and a plurality of second droplets having a center on a second line parallel to the first line, respectively, In the second ejection step, a plurality of third droplets having a center on the first line are ejected between the first droplets, thereby being line symmetric with respect to the first line, And by ejecting a plurality of fourth droplets having a center on the second line between the first mask layer having a plurality of line widths and the second droplet, And a second mask layer having a plurality of line widths, respectively, and using the first mask layer and the second mask layer, a conductive film is formed. Processed to form the first conductive layer and a second conductive layer having a predetermined interval.

    In one embodiment of the method for manufacturing a semiconductor device of the present invention, a conductive film is formed over a substrate, and a plurality of droplets made of a composition containing a mask layer material are formed over the conductive film. A plurality of first droplets having a center on the first line and a plurality of second droplets having a center on a second line parallel to the first line, respectively, In the second ejection step, a plurality of third droplets having a center on the first line are ejected between the first droplets, thereby being line symmetric with respect to the first line, In addition, a plurality of fourth droplets having a center on the second line are ejected between the first mask layer whose line width is continuously changed and the second droplet, whereby the second line And a second mask layer whose line width is continuously changed, respectively, are formed using the first mask layer and the second mask layer. Conductive film is processed to form the first conductive layer and a second conductive layer having a predetermined interval.

    In one embodiment of the method for manufacturing a semiconductor device of the present invention, a conductive film is formed over a substrate, and a plurality of droplets made of a composition containing a mask layer material are formed over the conductive film. A plurality of first droplets having a center on the first line and a plurality of second droplets having a center on a second line parallel to the first line, respectively, In the second ejection step, a plurality of third droplets having a center on the first line are ejected between the first droplets, thereby being line symmetric with respect to the first line, In addition, a plurality of fourth droplets having a center on the second line are ejected between the first mask layer whose line width is periodically changed and the second droplet, whereby the second line And a second mask layer whose line width is periodically changed, and using the first mask layer and the second mask layer, respectively. Conductive film is processed to form the first conductive layer and a second conductive layer having a predetermined interval.

  The mask layer and the conductive layer formed by using the present invention have a wavy and wavy shape such as a wavy shape continuous to the side end portion when viewed from above.

According to the present invention, components such as wirings constituting a semiconductor device, a display device and the like can be stably formed in a desired shape. Also. There is little loss of material, and cost reduction can be achieved. Therefore, a high-performance and highly reliable semiconductor device and display device can be manufactured with high yield.

  Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

(Embodiment 1)
An embodiment of the present invention will be described with reference to FIG.

    The present invention provides at least one or more of components necessary for manufacturing a semiconductor device, a display device, and the like, such as a conductive layer for forming a wiring layer or an electrode, and a mask layer for forming a predetermined pattern. Are formed by a method that can be selectively formed into a desired shape, and a semiconductor device and a display device are manufactured. In the present invention, a component (also referred to as a pattern) refers to a conductive layer such as a wiring layer, a gate electrode layer, a source electrode layer, and a drain electrode layer, a semiconductor layer, a mask layer, an insulating layer, etc. that constitute a thin film transistor or a display device. Including all components formed with a predetermined shape. As a method that can selectively form a desired pattern with a desired pattern, droplets of a composition formulated for a specific purpose are selectively ejected (ejected) to form a conductive layer, insulating layer, etc. in a predetermined pattern A droplet discharge (ejection) method (also called an ink jet method depending on the method) can be used. In addition, a method in which the composition can be transferred or drawn in a desired pattern, for example, various printing methods (screen (stencil) printing, offset (flat plate) printing, letterpress printing, gravure (intaglio printing), etc.) ), A dispenser method, a selective coating method, and the like can also be used.

    In this embodiment, a method is used in which a composition containing a constituent forming material that is a fluid is ejected (ejected) as droplets to form a desired pattern. A droplet containing a component forming material is discharged onto a region where the component is to be formed, and fixed by firing, drying, or the like to form a component having a desired pattern.

    One mode of a droplet discharge apparatus used for the droplet discharge method is shown in FIG. The individual heads 1405 and 1412 of the droplet discharge means 1403 are connected to the control means 1407, which can be drawn in a pre-programmed pattern under the control of the computer 1410. The drawing timing may be performed with reference to a marker 1411 formed on the substrate 1400, for example. Alternatively, the reference point may be determined based on the edge of the substrate 1400. This is detected by the imaging means 1404, converted into a digital signal by the image processing means 1409, is recognized by the computer 1410, a control signal is generated, and sent to the control means 1407. As the imaging unit 1404, a charge coupled device (CCD), an image sensor using a complementary metal oxide semiconductor, or the like can be used. Of course, the information on the pattern to be formed on the substrate 1400 is stored in the storage medium 1408. Based on this information, a control signal is sent to the control means 1407, and each head 1405 of the droplet discharge means 1403 is sent. The heads 1412 can be individually controlled. The material to be discharged is supplied from the material supply source 1413 and the material supply source 1414 to the head 1405 and the head 1412 through piping.

    The inside of the head 1405 has a structure having a space filled with a liquid material as indicated by a dotted line 1406 and a nozzle that is a discharge port. Although not shown, the head 1412 has the same internal structure as the head 1405. When the nozzles of the head 1405 and the head 1412 are provided in different sizes, different materials can be drawn simultaneously with different widths. With one head, conductive material, organic material, inorganic material, etc. can be discharged and drawn respectively. When drawing in a wide area like an interlayer film, the same material is used from multiple nozzles to improve throughput. It is possible to discharge and draw at the same time. In the case of using a large substrate, the head 1405 and the head 1412 can freely scan on the substrate in the direction of the arrow to freely set a drawing area, and a plurality of the same pattern can be drawn on a single substrate. it can.

    In the case of forming a conductive layer by using a droplet discharge method, a conductive layer is formed by discharging a composition containing a conductive material processed into a particulate form and fusing or fusion-bonding and solidifying by firing. In such a conductive layer (or insulating layer) formed by discharging and baking a composition containing a conductive material, the conductive layer (or insulating layer) formed by sputtering or the like is mostly a columnar structure. In many cases, a polycrystalline state having many grain boundaries is exhibited.

    The concept of the embodiment of the present invention will be described with reference to FIG. 1 using a method for forming a conductive layer. FIG. 1 is a top view of the conductive layer.

    As shown in FIG. 1, the conductive layer is formed on the substrate 50. Therefore, it is necessary to control the wettability of the surface of the substrate 50, which is a region where the conductive layer is formed, with respect to a liquid composition containing a conductive material forming the conductive layer. The degree of wettability may be set as appropriate depending on the line width and pattern shape of the conductive layer to be formed, and the wettability can be controlled by the following process. In this embodiment, when the conductive layer is formed, the contact angle of the formation region with respect to the composition containing a conductive material is preferably 20 degrees or more, more preferably 20 degrees or more and 40 degrees or less.

First, a method of forming a substance with low wettability and controlling so as to reduce the wettability of the surface of the formation region will be described. As such a low wettability substance, a substance containing a fluorocarbon group (fluorocarbon chain) or a substance containing a silane coupling agent can be used. The silane coupling agent is represented by a chemical formula of Rn—Si—X _(4-n) (n = 1, 2, 3). Here, R is a substance containing a relatively inert group such as an alkyl group. X is a hydrolyzable group such as halogen, methoxy group, ethoxy group or acetoxy group, which can be bonded by condensation with a hydroxyl group on the substrate surface or adsorbed water.

Further, as a representative example of the silane coupling agent, wettability can be further reduced by using a fluorine-based silane coupling agent (fluoroalkylsilane (FAS)) having a fluoroalkyl group in R. R of FAS has a structure represented by (CF ₃ ) (CF ₂ ) _x (CH ₂ ) _y (x: an integer of 0 or more and 10 or less, y: an integer of 0 or more and 4 or less), and a plurality of R Alternatively, when X is bonded to Si, R and X may all be the same or different. As typical FAS, fluoroalkylsilanes (hereinafter also referred to as FAS) such as heptadecafluorotetrahydrodecyltriethoxysilane, hepadecafluorotetrahydrodecyltrichlorosilane, tridecafluorotetrahydrooctyltrichlorosilane, and trifluoropropyltrimethoxysilane. ).

    As the substance having low wettability, a substance having no fluorocarbon chain and having an alkyl group in R of the silane coupling agent can be used. For example, octadecyltrimethoxysilane or the like can be used as the organic silane.

As a solvent of a solution containing a substance having low wettability, n-pentane, n-hexane, n-heptane, n-octane, n-decane, dicyclopentane, benzene, toluene, xylene, durene, indene, tetrahydronaphthalene, Hydrocarbon solvents such as decahydronaphthalene and squalane or tetrahydrofuran are used.

In addition, as an example of a composition that controls wettability to be low and forms a low wettability region, a substance having a fluorocarbon chain (fluorine resin) can be used. Examples of fluorine resins include polytetrafluoroethylene (PTFE; tetrafluoroethylene resin), perfluoroalkoxyalkane (PFA; tetrafluoroethylene perfluoroalkyl vinyl ether copolymer resin), and perfluoroethylene propene copolymer (PFEP; four fluoropolymer). Ethylene-hexafluoropropylene copolymer resin), ethylene-tetrafluoroethylene copolymer (ETFE; tetrafluoroethylene-ethylene copolymer resin), polyvinylidene fluoride (PVDF; vinylidene fluoride resin), polychlorotrifluoroethylene (PCTFE; trifluoroethylene chloride resin), ethylene-chlorotrifluoroethylene copolymer (ECTFE; trifluoroethylene chloride-ethylene copolymer resin), polytetrafluoroethylene-perfluorodioxide Rukoporima (TFE / PDD), polyvinyl fluoride (PVF; a vinyl fluoride resin), or the like can be used.

In addition, when an inorganic material or an organic material is treated with CF ₄ plasma or the like, wettability can be reduced. For example, a material obtained by mixing a water-soluble resin such as polyvinyl alcohol (PVA) in a solvent such as H ₂ O as an organic material can be used. Moreover, you may use combining PVA and another water-soluble resin. An organic material (organic resin material) (polyimide, acrylic) or a siloxane material may be used. Note that the siloxane material corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

    In the present embodiment, FAS is formed on the surface of the substrate 50 by spin coating, and the wettability of the surface of the substrate 50 is adjusted. This wettability is for a liquid composition containing a conductive material constituting a conductive layer formed in a later step.

    If the conductive layer is formed continuously by one discharge, the liquid droplets aggregate and a liquid pool called a bulge is generated, and the conductive layer may be disconnected. Therefore, in the present invention, the conductive layer is formed by a plurality of ejections. That is, in the first discharge step, a liquid composition containing a conductive material is attached so as to be scattered in a region where the droplets are not in contact with each other. Next, the conductive material droplets discharged in the first discharge step are filled with the composition containing the conductive material in the second discharge step, thereby forming a continuous conductive layer. Since the composition containing the conductive material discharged in the first discharge step has elapsed, it is solidified by drying, and thus does not aggregate with the conductive material in the second discharge step. When a conductive layer is manufactured in this way, a stable conductive layer can be formed regardless of whether it is a thin line.

    However, the conductive layer formed by a plurality of ejections as described above has a line width that is not uniform and has a shape having nodes. The surface of the conductive layer solidified with the composition containing the conductive material discharged in the first discharge step and the surface of the substrate 50 with controlled wettability are wettability with respect to the liquid composition containing the conductive material. Is different. The liquid composition containing the conductive material discharged in the second discharge step is discharged to both the conductive layer in the first discharge step and the substrate 50 surface. The liquid composition containing a conductive material that is greatly affected by the wettability of the surface moves so as to flow onto the conductive layer formed by the first discharge process with higher wettability. As a result, the line width of the conductive layer in the region formed by the first discharge process is increased, and the line width of the conductive layer in the region formed by the second discharge process is decreased. Thus, a conductive layer having a non-uniform line width and a periodic node is formed. Therefore, at least a part of the conductive layer in this embodiment is bent when viewed from the upper surface, and the side end portion appears to have a wavy shape that undulates from side to side.

  When conductive layers having nodes are formed adjacent to each other, if the portions having a wide line width are adjacent to each other, the interval between the conductive layers is narrowed. If the portions having a narrow line width are adjacent to each other, the interval between the conductive layers is increased. As described above, the gap between the conductive layers varies and becomes non-uniform. In addition, there is a problem of shape failure that the conductive layers come into contact with each other, and it is difficult to form finely designed conductive layers and insulating layers at stable intervals.

    In the present embodiment, as shown in FIG. 1, first, the conductive layers 51a to 51e and the conductive layers 51f to 51j are formed by the first discharge process. At this time, the centers of the droplets of the conductive layers 51a to 51e that are part of the first conductive layer and the centers of the conductive layers 51f to 51j that are part of the adjacent second conductive layer are lined up. Do not overlap in the width direction. The center of the conductive layer 51f is positioned between the center of the conductive layer 51a and the center of the conductive layer 51b, preferably in the line width direction of the central region obtained by dividing the center of the conductive layer 51a and the center of the conductive layer 51b into three. To do. Since the maximum widths of the conductive layers 51a to 51e and the conductive layers 51f to 51j formed by the first discharge process are the maximum widths of the first conductive layer and the second conductive layer later, If the conductive layer 51a to the conductive layer 51e and the conductive layer 51f to the conductive layer 51j are not in contact with each other at the stage of FIG. 1A, the first conductive layer and the second conductive layer are in contact with each other. There is no cause.

    Next, as shown in FIG. 1B, a conductive layer is formed by a second discharge step of a composition containing a conductive material so as to fill between the conductive layers 51a to 51e formed in the first discharge step. 52a to 52d are formed, and the first conductive layer 53a is formed. Similarly, the conductive layer 52e to the conductive layer 52h are formed by the second discharge step of the composition containing the conductive material so as to fill the space between the conductive layer 51f and the conductive layer 51j, and the second conductive layer 53b is formed. To do.

  As described above, the composition containing the liquid conductive material having fluidity attached in the second ejection step is changed to the conductive layers 51a to 51j having higher wettability due to the difference in wettability of the attached region. Move partly and stabilize. Then, it solidifies by drying, baking, etc., and the 1st conductive layer 53a and the 2nd conductive layer 53b which have a node periodically are formed like FIG.1 (C). The side end portion 54a of the first conductive layer 53a and the side end portion 54b of the second conductive layer 53b exhibit a continuous wavy shape. The first conductive layer 53a and the second conductive layer 53b are formed so that the maximum line width regions are not adjacent to each other and are shifted by the discharge method of the present invention. The distance between the first conductive layer 53a and the second conductive layer 53b can be made smaller than the sum of the difference between the maximum line width and the minimum line width halved. Therefore, the first conductive layer 53a and the second conductive layer 53b can be stably formed even at a narrow interval. An insulating layer can also be formed by discharging an insulating material in the same manner. Since it can be formed at a uniform interval, fine and accurate processing can be performed by using the mask layer formed in this way. Since the distance between the conductive layers can be reduced, the channel width can be reduced by using the conductive layers as a source electrode layer and a drain electrode layer. Therefore, a high-performance and highly reliable semiconductor device capable of high-speed operation can be manufactured. Since defects due to shape defects are reduced at the time of manufacturing, the yield is improved and the productivity is increased.

    In this embodiment mode, the first conductive layer 53a and the second conductive layer 53b are formed using a droplet discharge unit. The droplet discharge means is a general term for a device having means for discharging droplets such as a nozzle having a composition discharge port and a head having one or a plurality of nozzles. The diameter of the nozzle provided in the droplet discharge means is set to 0.02 to 100 μm (preferably 30 μm or less), and the discharge amount of the composition discharged from the nozzle is 0.001 pl to 100 pl (preferably 0). .1pl or more and 40pl or less, more preferably 10pl or less). The discharge amount increases in proportion to the size of the nozzle diameter. In addition, the distance between the object to be processed and the nozzle outlet is preferably as close as possible in order to drop it at a desired location, preferably about 0.1 to 3 mm (preferably about 1 mm or less). Set.

    A composition in which a conductive material is dissolved or dispersed in a solvent is used as the composition discharged from the discharge port. The conductive material corresponds to fine particles or dispersible nanoparticles of one or more kinds of metals such as Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, and Al. Further, the conductive material is mixed with metal sulfides of Cd and Zn, oxides such as Fe, Ti, Ge, Si, Zr, and Ba, one or more kinds of fine particles of silver halide, or dispersible nanoparticles. May be. As the conductive material, indium tin oxide (ITO) used as a transparent conductive film, indium tin oxide containing silicon oxide (ITSO), organic indium, organic tin, zinc oxide, titanium nitride, or the like may be used. . As the conductive material, particles of a single element or a plurality of kinds of elements can be mixed and used. However, it is preferable to use a composition in which any of gold, silver and copper is dissolved or dispersed in a solvent in consideration of the specific resistance value, more preferably the composition discharged from the discharge port. It is preferable to use low resistance silver or copper. However, when silver or copper is used, a barrier film may be provided as a countermeasure against impurities. As the barrier film, a silicon nitride film or nickel boron (NiB) can be used.

  The composition to be discharged is obtained by dissolving or dispersing a conductive material in a solvent, but additionally contains a dispersant and a thermosetting resin called a binder. In particular, the binder has a function of preventing the occurrence of cracks and unevenness in the fused state during firing. Thus, the formed conductive layer may contain an organic material. The organic material contained varies depending on the heating temperature, atmosphere, and time. This organic material is an organic resin that functions as a binder of metal particles, a solvent, a dispersant, and a coating agent. Typically, a polyimide resin, an acrylic resin, a novolac resin, a melamine resin, a phenol resin, an epoxy resin, Organic resins such as silicon resin, furan resin and diallyl phthalate resin can be used.

    Alternatively, particles in which a conductive material is coated with another conductive material to form a plurality of layers may be used. For example, particles having a three-layer structure in which nickel boron (NiB) is coated around copper and silver is coated around it may be used. As the solvent, esters such as butyl acetate and ethyl acetate, alcohols such as isopropyl alcohol and ethyl alcohol, organic solvents such as methyl ethyl ketone and acetone, and water are used. The viscosity of the composition is preferably 20 mPa · s or less, in order to prevent drying during discharge or to allow the composition to be smoothly discharged from the discharge port. The surface tension of the composition is preferably 40 mN / m or less. However, the viscosity and the like of the composition may be appropriately adjusted according to the solvent to be used and the application. As an example, the viscosity of a composition in which ITO, organic indium, or organic tin is dissolved or dispersed in a solvent is 5 to 20 mPa · s, the viscosity of a composition in which silver is dissolved or dispersed in a solvent is 5 to 20 mPa · s, The viscosity of the composition in which gold is dissolved or dispersed in a solvent is preferably set to 5 to 20 mPa · s.

    The conductive layer may be a stack of a plurality of conductive materials. Alternatively, first, silver may be used as a conductive material, and a conductive layer may be formed by a droplet discharge method, followed by plating with copper or the like. Plating may be performed by electroplating or chemical (electroless) plating. For plating, the substrate surface may be immersed in a container filled with a solution having a plating material, but the substrate is placed at an angle (or vertically) so that the solution having the material to be plated flows on the substrate surface. It may be applied. When plating is performed such that the solution is applied while standing the substrate, there is an advantage that the apparatus used in the process can be downsized even if the substrate is a large area.

    Although depending on the diameter of each nozzle and the desired pattern shape, the diameter of the conductor particles is preferably as small as possible for preventing nozzle clogging and producing a high-definition pattern. 1 μm or less is preferable. The composition is formed by a method such as an electrolytic method, an atomizing method, or a wet reduction method, and its particle size is generally about 0.01 to 10 μm. However, when formed by a gas evaporation method, the nanoparticles protected by the dispersant are as fine as about 7 nm, and these nanoparticles are aggregated in the solvent when the surface of each particle is covered with a coating agent. And stably disperse at room temperature and shows almost the same behavior as liquid. Therefore, it is preferable to use a coating agent.

    In the present invention, since the wettability difference between the composition of the fluid and the vicinity of the region to be formed is processed into a desired pattern shape, the composition has fluidity even when it is landed on the object to be processed. However, as long as the fluidity is not lost, the step of discharging the composition may be performed under reduced pressure. Further, it is preferable to perform under reduced pressure because an oxide film or the like is not formed on the surface of the conductor. After discharging the composition, one or both steps of drying and baking are performed. The drying and firing steps are both heat treatment steps. For example, drying is performed at 100 degrees (C) for 3 minutes, and firing is performed at 200 to 550 degrees (C) for 15 minutes to 60 minutes. Depending on the purpose, temperature and time are different. The drying process and the firing process are performed under normal pressure or reduced pressure by laser light irradiation, rapid thermal annealing, a heating furnace, or the like. Note that the timing of performing this heat treatment and the number of heat treatments are not particularly limited. In order to carry out the drying and firing steps satisfactorily, the substrate may be heated, and the temperature at that time depends on the material such as the substrate, but is generally 100 to 800 ° C. (° C.) ( Preferably, it is set to 200 to 550 degrees (° C.). By this step, the solvent in the composition is volatilized or the dispersant is chemically removed, and the surrounding resin is cured and contracted to bring the nanoparticles into contact with each other, thereby accelerating fusion and fusion.

For the laser light irradiation, a continuous wave or pulsed gas laser or solid-state laser may be used. Examples of the former gas laser include an excimer laser and a YAG laser, and examples of the latter solid-state laser include a laser using a crystal such as YAG, YVO ₄ , and GdVO ₄ doped with Cr, Nd, or the like. . Note that it is preferable to use a continuous wave laser because of the absorption rate of the laser light. Further, a laser irradiation method combining pulse oscillation and continuous oscillation may be used. However, depending on the heat resistance of the substrate, the heat treatment by laser light irradiation may be performed instantaneously within a few microseconds to several tens of seconds so as not to destroy the substrate. Instantaneous thermal annealing (RTA) uses an infrared lamp or a halogen lamp that irradiates ultraviolet light or infrared light in an inert gas atmosphere, and rapidly raises the temperature for several minutes to several microseconds. This is done by applying heat instantaneously. Since this treatment is performed instantaneously, only the outermost thin film can be heated substantially without affecting the lower layer film. That is, it does not affect a substrate having low heat resistance such as a plastic substrate.

    Alternatively, after the composition is discharged by a droplet discharge method to form a conductive layer, an insulating layer, or the like, the surface may be pressed and flattened by pressure in order to improve the flatness. As a pressing method, unevenness may be reduced by scanning a roller-shaped object on the surface, or the surface may be pressed vertically with a flat plate-like object. A heating step may be performed when pressing. Alternatively, the surface may be softened or dissolved with a solvent or the like, and the surface irregularities may be removed with an air knife. Further, polishing may be performed using a CMP method. This step can be applied when the surface is flattened when unevenness is generated by the droplet discharge method.

    According to the present invention, even if the wiring and the like are densely and complicatedly arranged by downsizing and thinning, they can be stably formed in a desired pattern with a good shape, and reliability and productivity can be improved. Can be improved. In addition, there is little material loss, and cost reduction can be achieved. Therefore, a high-performance and highly reliable semiconductor device and display device can be manufactured with high yield.

(Embodiment 2)
FIG. 26A is a top view illustrating a structure of a display panel according to the present invention. A pixel portion 2701 in which pixels 2702 are arranged in a matrix over a substrate 2700 having an insulating surface, a scan line side input terminal 2703, a signal A line side input terminal 2704 is formed. The number of pixels may be provided in accordance with various standards. For full color display using XGA and RGB, 1024 × 768 × 3 (RGB), and for full color display using UXGA and RGB, 1600 × 1200. If it corresponds to x3 (RGB) and full spec high vision and is full color display using RGB, it may be 1920 x 1080 x 3 (RGB).

The pixels 2702 are arranged in a matrix by a scan line extending from the scan line side input terminal 2703 and a signal line extending from the signal line side input terminal 2704 intersecting. Each of the pixels 2702 includes a switching element and a pixel electrode connected to the switching element. A typical example of the switching element is a TFT. By connecting the gate electrode side of the TFT to a scanning line and the source or drain side to a signal line, each pixel can be controlled independently by a signal input from the outside. Yes.

A TFT includes a semiconductor layer, a gate insulating layer, and a gate electrode layer as main components, and a wiring layer connected to a source region and a drain region formed in the semiconductor layer is attached to the TFT. Structurally, the top gate type in which the semiconductor layer, the gate insulating layer and the gate electrode layer are arranged from the substrate side, and the bottom gate type in which the gate electrode layer, the gate insulating layer and the semiconductor layer are arranged from the substrate side are representative. In the present invention, any of those structures may be used.

    FIG. 26A illustrates a structure of a display panel in which signals input to the scan lines and the signal lines are controlled by an external driver circuit. As illustrated in FIG. 27A, COG (Chip on The driver IC 2751 may be mounted on the substrate 2700 by a glass method. As another mounting mode, a TAB (Tape Automated Bonding) method as shown in FIG. 27B may be used. The driver IC may be formed on a single crystal semiconductor substrate or may be a circuit in which a TFT is formed on a glass substrate. In FIG. 27, the driver IC 2751 is connected to the FPC 2750.

    In the case where the TFT provided for the pixel is formed using a polycrystalline (microcrystalline) semiconductor with high crystallinity, the scan line driver circuit 3702 may be formed over the substrate 3700 as illustrated in FIG. it can. In FIG. 26B, reference numeral 3701 denotes a pixel portion, and the signal line driver circuit is controlled by an external driver circuit as in FIG. Reference numeral 3704 denotes a signal line side input terminal. In the case where a TFT provided in a pixel is formed using a polycrystalline (microcrystalline) semiconductor, a single crystal semiconductor, or the like with high mobility like the TFT formed in the present invention, as shown in FIG. 4701, the scan line driver circuit 4702, and the signal line driver circuit 4704 can be formed over the glass substrate 4700 integrally.

    An embodiment of the present invention will be described with reference to FIGS. More specifically, a method for manufacturing a display device having an inverted staggered thin film transistor to which the present invention is applied will be described. 2A to 6A are top views of the display device pixel portion, and FIG. 2B to FIG. 6B are cross-sectional views taken along line A-C in FIG. 2A to FIG. C) is a sectional view taken along line BD. 7 is a cross-sectional view of the display device, and FIG. 8A is a top view. FIG. 8B is a cross-sectional view taken along line LK (including IJ) in FIG.

As the substrate 100, a glass substrate made of barium borosilicate glass, alumino borosilicate glass, or the like, a quartz substrate, a metal substrate, or a plastic substrate having heat resistance that can withstand the processing temperature in this manufacturing process is used. Further, polishing may be performed by a CMP method or the like so that the surface of the substrate 100 is planarized. Note that an insulating layer may be formed over the substrate 100. The insulating layer is formed as a single layer or a stacked layer using an oxide material or a nitride material containing silicon by a method such as a CVD method, a plasma CVD method, a sputtering method, or a spin coating method. This insulating layer may not be formed, but has an effect of blocking contaminants from the substrate 100.

    A gate electrode layer 103 and a gate electrode layer 104 are formed over the substrate 100. The gate electrode layer 103 and the gate electrode layer 104 can be formed by a CVD method, a sputtering method, a droplet discharge method, or the like. The gate electrode layer 103 and the gate electrode layer 104 are composed mainly of an element selected from Ag, Au, Ni, Pt, Pd, Ir, Rh, Ta, W, Ti, Mo, Al, and Cu, or the above elements. What is necessary is just to form with an alloy material or a compound material. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used. Alternatively, a single-layer structure or a multi-layer structure may be used, for example, a two-layer structure of a tungsten nitride (WN) film and a molybdenum (Mo) film, a tungsten film with a thickness of 50 nm, aluminum with a thickness of 500 nm, and A three-layer structure in which a silicon alloy (Al—Si) film and a titanium nitride film with a thickness of 30 nm are sequentially stacked may be employed. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten of the first conductive film, or aluminum instead of the aluminum and silicon alloy (Al-Si) film of the second conductive film. A titanium alloy film (Al—Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film.

When the gate electrode layer 103 and the gate electrode layer 104 need to be processed, a mask may be formed and processed by dry etching or wet etching. Using an ICP (Inductively Coupled Plasma) etching method, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the electrode temperature on the substrate side, etc.) are appropriately set. By adjusting, the electrode layer can be etched into a tapered shape. As an etching _gas, using Cl _2, BCl 3, SiCl ₄ or a chlorine-based gas typified by CCl _4, fluorine-based gas or _{O 2} and typified by CF 4, SF ₆ or NF ₃ as appropriate be able to.

A mask for processing can be formed by selectively discharging a composition. When the mask is selectively formed in this way, there is an effect that the processing step is simplified. For the mask, a resin material such as an epoxy resin, a phenol resin, a novolac resin, an acrylic resin, a melamine resin, or a urethane resin is used. In addition, a composition comprising an organic material such as benzocyclobutene, parylene, fluorinated arylene ether, permeable polyimide, a compound material obtained by polymerization of a siloxane polymer, a water-soluble homopolymer and a water-soluble copolymer It is formed by a droplet discharge method using a material or the like. Alternatively, a commercially available resist material containing a photosensitizer may be used. For example, a novolak resin that is a typical positive resist and a naphthoquinonediazide compound that is a photosensitizer, a base resin that is a negative resist, diphenylsilanediol, and An acid generator or the like may be used. Whichever material is used, the surface tension and viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant or the like.

    In this embodiment, the gate electrode layer 103 and the gate electrode layer 104 are formed by forming a conductive film and then processing into a desired shape with a mask layer. The wettability is controlled by forming FAS on the surface of the conductive film, and a mask layer is formed using a droplet discharge means. Since the mask layer is formed by a method using a droplet discharge method as described in Embodiment Mode 1, it has a shape having a node, and the gate electrode layer 103 and the gate electrode layer 104 obtained by processing using the mask layer are also included. Reflects its shape. (See FIG. 2).

Next, the gate insulating layer 105 is formed over the gate electrode layer 103 and the gate electrode layer 104. The gate insulating layer 105 may be formed of a material such as a silicon oxide material or a nitride material, and may be a stacked layer or a single layer. In this embodiment, a two-layer stack of a silicon nitride film and a silicon oxide film is used. Alternatively, a single layer of silicon oxynitride film or a stack of three or more layers may be used. A silicon nitride film having a dense film quality is preferably used. In addition, when silver or copper is used for a conductive layer formed by a droplet discharge method, if a silicon nitride film or a NiB film is formed thereon as a barrier film, diffusion of impurities can be prevented and the surface can be planarized. is there. Note that in order to form a dense insulating film with low gate leakage current at a low deposition temperature, a rare gas element such as argon is preferably contained in a reaction gas and mixed into the formed insulating film.

Next, a semiconductor layer is formed. A semiconductor layer having one conductivity type may be formed as necessary. In addition, an n-type semiconductor layer is formed, an n-channel TFT NMOS structure, a p-channel TFT PMOS structure having a p-type semiconductor layer, and an n-channel TFT and p-channel TFT CMOS structure. Can be produced. Further, in order to impart conductivity, an n-channel TFT or a p-channel TFT can be formed by adding an element imparting conductivity by doping and forming an impurity region in the semiconductor layer. Instead of forming an n-type semiconductor layer, conductivity may be imparted to the semiconductor layer by performing plasma treatment with a PH ₃ gas.

As a material for forming the semiconductor layer, an amorphous semiconductor (hereinafter also referred to as “AS”) manufactured by a vapor deposition method or a sputtering method using a semiconductor material gas typified by silane or germane is used. A polycrystalline semiconductor crystallized using energy or thermal energy, a semi-amorphous (also referred to as microcrystal or microcrystal, hereinafter, also referred to as “SAS”) semiconductor, or the like can be used. The semiconductor layer can be formed by various means (a sputtering method, an LPCVD method, a plasma CVD method, or the like).

SAS is a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal) and having a third state that is stable in terms of free energy and has a short-range order and a lattice. It includes a crystalline region with strain. A crystal region of 0.5 to 20 nm can be observed in at least a part of the film, and when silicon is a main component, the Raman spectrum is shifted to a lower wave number side than 520 cm ^−1. Yes. In X-ray diffraction, diffraction peaks of (111) and (220) that are derived from the silicon crystal lattice are observed. In order to terminate dangling bonds (dangling bonds), hydrogen or halogen is contained at least 1 atomic% or more. SAS is formed by glow discharge decomposition (plasma CVD) of a gas containing silicon. As a gas containing silicon, SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _4, or the like can be used. Further, F ₂ and GeF ₄ may be mixed. The gas containing silicon may be diluted with H ₂ , or H ₂ and one or more kinds of rare gas elements selected from He, Ar, Kr, and Ne. The dilution rate is in the range of 2 to 1000 times, the pressure is in the range of approximately 0.1 Pa to 133 Pa, and the power supply frequency is 1 MHz to 120 MHz, preferably 13 MHz to 60 MHz. The substrate heating temperature is preferably 300 ° C. or lower, and can be formed even at a substrate heating temperature of 100 to 200 ° C. Here, as an impurity element mainly taken in at the time of film formation, impurities derived from atmospheric components such as oxygen, nitrogen, and carbon are preferably 1 × 10 ²⁰ cm ⁻³ or less, and in particular, the oxygen concentration is 5 × 10 5. It is preferable to be ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ⁻³ or less. Further, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, stability is improved and a favorable SAS can be obtained. In addition, a SAS layer formed of a hydrogen-based gas may be stacked on a SAS layer formed of a fluorine-based gas as a semiconductor layer.

    A typical example of an amorphous semiconductor is hydrogenated amorphous silicon, and a typical example of a crystalline semiconductor is polysilicon. Polysilicon (polycrystalline silicon) is mainly made of so-called high-temperature polysilicon using polysilicon formed through a process temperature of 800 ° C. or higher as a main material, or polysilicon formed at a process temperature of 600 ° C. or lower. And so-called low-temperature polysilicon, and polysilicon crystallized by adding an element that promotes crystallization. Of course, as described above, a semi-amorphous semiconductor or a semiconductor including a crystal phase in a part of the semiconductor layer can also be used.

As a semiconductor material, a compound semiconductor such as GaAs, InP, SiC, ZnSe, GaN, or SiGe can be used in addition to a simple substance such as silicon (Si) or germanium (Ge). Zinc oxide (ZnO) can also be used. When ZnO is used for the semiconductor layer, the gate insulating layer may be Y ₂ O _x , Al ₂ O ₃ , TiO ₂ , a stacked layer thereof, or the like. ITO, Au, Ti, or the like is preferably used for the source electrode layer and the drain electrode layer. In addition, In, Ga, or the like can be added to ZnO.

In the case where a crystalline semiconductor layer is used as a semiconductor layer, a crystalline semiconductor layer can be formed by various methods (laser crystallization method, thermal crystallization method, or heat using an element that promotes crystallization such as nickel). A crystallization method or the like may be used. In addition, a microcrystalline semiconductor that is a SAS can be crystallized by laser irradiation to improve crystallinity. In the case where an element for promoting crystallization is not introduced, the amorphous semiconductor film (for example, an amorphous silicon film) is heated at 500 ° C. for 1 hour in a nitrogen atmosphere before irradiating the amorphous semiconductor film (for example, an amorphous silicon film) with laser light. The hydrogen concentration of the film is released to 1 × 10 ²⁰ atoms / cm ³ or less. This is because when an amorphous semiconductor film containing a large amount of hydrogen is irradiated with laser light, the amorphous semiconductor film is destroyed.

The method of introducing the metal element into the amorphous semiconductor layer is not particularly limited as long as the metal element can be present on the surface of the amorphous semiconductor layer or inside the amorphous semiconductor layer. For example, sputtering, CVD, A plasma treatment method (including a plasma CVD method), an adsorption method, or a method of applying a metal salt solution can be used. Among these, the method using a solution is simple and useful in that the concentration of the metal element can be easily adjusted. At this time, in order to improve the wettability of the surface of the amorphous semiconductor layer and to spread the aqueous solution over the entire surface of the amorphous semiconductor layer, irradiation with UV light in an oxygen atmosphere, thermal oxidation method, hydroxy radical It is desirable to form an oxide film by treatment with ozone water or hydrogen peroxide.

The crystallization of the amorphous semiconductor layer may be a combination of heat treatment and crystallization by laser light irradiation, or may be performed multiple times by heat treatment or laser light irradiation alone.

    Alternatively, the crystalline semiconductor layer may be directly formed over the substrate by a linear plasma method. Alternatively, the crystalline semiconductor layer may be selectively formed over the substrate by a linear plasma method.

As a semiconductor, an organic semiconductor material can be used and formed by a printing method, a dispenser method, a spray method, a spin coating method, a droplet discharge method, or the like. In this case, the number of processes can be reduced because the etching process is not necessary. As the organic semiconductor, a low molecular material, a polymer material, or the like is used, and materials such as an organic dye or a conductive polymer material can also be used. The organic semiconductor material used in the present invention is preferably a π-electron conjugated polymer material whose skeleton is composed of conjugated double bonds. Typically, a soluble polymer material such as polythiophene, polyfluorene, poly (3-alkylthiophene), a polythiophene derivative, or pentacene can be used.

In addition, as an organic semiconductor material that can be used in the present invention, there is a material that can form a semiconductor layer by processing after forming a soluble precursor. Examples of such an organic semiconductor material include polythienylene vinylene, poly (2,5-thienylene vinylene), polyacetylene, a polyacetylene derivative, and polyarylene vinylene.

When converting the precursor into an organic semiconductor, a reaction catalyst such as hydrogen chloride gas is added as well as heat treatment. Typical solvents for dissolving these soluble organic semiconductor materials include toluene, xylene, chlorobenzene, dichlorobenzene, anisole, chloroform, dichloromethane, γ-butyllactone, butyl cellosolve, cyclohexane, NMP (N-methyl-2 -Pyrrolidone), cyclohexanone, 2-butanone, dioxane, dimethylformamide (DMF), THF (tetrahydrofuran), or the like can be applied.

A semiconductor layer 107 and a semiconductor layer 108 are formed over the gate insulating layer 105. In this embodiment mode, an amorphous semiconductor layer is crystallized as the semiconductor layer 107 and the semiconductor layer 108 to form a crystalline semiconductor layer. In the crystallization step, an element (also referred to as a catalyst element or a metal element) that promotes crystallization is added to the amorphous semiconductor layer, and crystallization is performed by heat treatment (at 550 ° C. to 750 ° C. for 3 minutes to 24 hours). As elements for promoting crystallization, metal elements for promoting crystallization of silicon include iron (Fe), nickel (Ni), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd). One or plural types selected from osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), and gold (Au) can be used. In this embodiment, nickel is used.

In order to remove or reduce the element that promotes crystallization from the crystalline semiconductor layer, a semiconductor layer containing an impurity element is formed in contact with the crystalline semiconductor layer and functions as a gettering sink. As the impurity element, an impurity element imparting n-type conductivity, an impurity element imparting p-type conductivity, a rare gas element, or the like can be used. For example, phosphorus (P), nitrogen (N), arsenic (As), antimony (Sb ), Bismuth (Bi), boron (B), helium (He), neon (Ne), argon (Ar), Kr (krypton), and Xe (xenon) can be used. In this embodiment, a semiconductor layer containing argon is formed as the semiconductor layer containing an impurity element that functions as a gettering sink. A semiconductor layer containing argon is formed over the crystalline semiconductor layer containing an element that promotes crystallization, and heat treatment (at 550 ° C. to 750 ° C. for 3 minutes to 24 hours) is performed. The element that promotes crystallization contained in the crystalline semiconductor layer moves into the semiconductor layer containing argon, and the element that promotes crystallization in the crystalline semiconductor layer is removed or reduced. After that, the semiconductor layer containing argon that has become a gettering sink is removed. An n-type semiconductor layer including phosphorus (P) which is an impurity element imparting n-type is formed over the crystalline semiconductor layer. The semiconductor layer having n-type functions as a source region and a drain region. In this embodiment, an n-type semiconductor layer is formed using a semi-amorphous semiconductor. The semiconductor layer and the n-type semiconductor layer formed in the above steps are processed into a desired shape, so that the semiconductor layer 107, the semiconductor layer 108, the n-type semiconductor layer 109, and the n-type semiconductor layer 110 are formed ( (See FIG. 3). In this embodiment mode, the mask layer used for processing the semiconductor layer and the n-type semiconductor layer also uses a droplet discharge method, and thus the shape of the semiconductor layer is reflected in the shape having a node.

The wettability of the surfaces over the n-type semiconductor layer 109, the n-type semiconductor layer 110, and the gate insulating layer 105 is controlled. In this embodiment mode, the material 102 having low wettability is formed in order to control the wettability of the surface to be lower. As a substance having low wettability, a substance containing a fluorocarbon chain or a substance containing a silane coupling agent can be used. In this embodiment mode, FAS is used as the substance 102 with low wettability, and a FAS film is formed by a coating method. This wettability is with respect to a composition containing a liquid conductive material constituting a source electrode layer or a drain electrode layer formed in a later step.

A mask made of an insulator such as resist or polyimide is formed using a droplet discharge method, and a through-hole 125 is formed in a part of the gate insulating layer 105 by etching using the mask, and a lower layer side thereof is formed. A part of the arranged gate electrode layer 104 is exposed (see FIG. 4). In this step, a substance with low wettability existing at the through hole 125 is also removed. The etching process may be either plasma etching (dry etching) or wet etching, but plasma etching is suitable for processing a large area substrate. As an etching gas, a fluorine-based or chlorine-based gas such as CF ₄ , NF ₃ , Cl ₂ , or BCl ₃ may be used, and an inert gas such as He or Ar may be appropriately added. Further, if an atmospheric pressure discharge etching process is applied, a local electric discharge process is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

A mask used in processing into a desired shape for forming the through hole 125 can also be formed by selectively discharging the composition. When the mask is selectively formed in this way, there is an effect that the processing step is simplified. For the mask, a resin material such as an epoxy resin, a phenol resin, a novolac resin, an acrylic resin, a melamine resin, or a urethane resin is used. In addition, a composition comprising an organic material such as benzocyclobutene, parylene, fluorinated arylene ether, permeable polyimide, a compound material obtained by polymerization of a siloxane polymer, a water-soluble homopolymer and a water-soluble copolymer It is formed by a droplet discharge method using a material or the like. Alternatively, a commercially available resist material containing a photosensitizer may be used. For example, a novolak resin that is a typical positive resist and a naphthoquinonediazide compound that is a photosensitizer, a base resin that is a negative resist, diphenylsilanediol, and An acid generator or the like may be used. Whichever material is used, the surface tension and viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant or the like.

In this embodiment, it is preferable to control wettability of a formation region as a pretreatment when a mask for processing is formed by a droplet discharge method. By controlling the wettability and the droplet diameter at the time of ejection, it can be stably formed in a desired shape (line width or the like). This step can be applied as a pretreatment of any formed material (insulating layer, conductive layer, mask layer, wiring layer, etc.) when a liquid material is used.

    A liquid conductive material is included on the semiconductor layer 109 having n-type and the semiconductor layer 110 having n-type by the droplet discharge device 118a, the droplet discharge device 118b, the droplet discharge device 118c, and the droplet discharge device 118d. The composition is discharged as in Embodiment 1 to form the source or drain electrode layer 111, the source or drain electrode layer 112, the source or drain electrode layer 113, and the source or drain electrode layer 114. (See FIG. 4). A source electrode layer or a drain electrode layer formed in a node shape by two discharges has a uniform interval without being in contact with the adjacent source electrode layer or the drain electrode layer by shifting the center of the droplet to be discharged. Formed. Even if the distance between the source electrode layer and the drain electrode layer is designed to be narrow, it can be formed without contact due to poor formation. Since the channel width is determined by the distance between the source electrode layer and the drain electrode layer, a thin film transistor including such a source electrode layer and a drain electrode layer can operate at high speed and has high reliability.

    Similarly, in contact with the source or drain electrode layer 111, the source or drain electrode layer 112, the source or drain electrode layer 113, and the source or drain electrode layer 114 using a droplet discharge method, A wiring layer 115, a wiring layer 116, and a wiring layer 117 are formed.

    The source or drain electrode layer 111, the source or drain electrode layer 112, the source or drain electrode layer 113, the source or drain electrode layer 114, the wiring layer 115, the wiring layer 116, and the wiring layer 117 are formed as desired. After forming the pattern, the remaining low wettability substance may be left, or unnecessary portions may be removed. The removal may be performed by ashing or etching with oxygen or the like. The source or drain electrode layer can also be used as a mask. In this embodiment, the source or drain electrode layer 111, the source or drain electrode layer 112, the source or drain electrode layer 113, the source or drain electrode layer 113, the wiring layer 115, the wiring layer 116, After the wiring layer 117 is formed, ultraviolet light is irradiated to decompose and remove the remaining low wettability substance (see FIG. 5).

The wiring layer 115 also functions as a source wiring layer, and the wiring layer 117 also functions as a power supply line. After forming the source or drain electrode layer 111, the source or drain electrode layer 112, the source or drain electrode layer 113, and the source or drain electrode layer 114, the semiconductor layer 107, the semiconductor layer 108, and the n-type The semiconductor layer 109 having n and the semiconductor layer 110 having n-type are processed into desired shapes. In this embodiment mode, a mask is formed and processed by a droplet discharge method; however, a semiconductor layer or an n-type semiconductor layer may be processed by etching using the source electrode layer and the drain electrode layer as a mask.

The source or drain electrode layer 111, the source or drain electrode layer 112, the source or drain electrode layer 113, the source or drain electrode layer 114, the wiring layer 115, the wiring layer 116, and the wiring layer 117 are formed. As a conductive material, use a composition mainly composed of metal particles such as Ag (silver), Au (gold), Cu (copper), W (tungsten), Al (aluminum), Mo (molybdenum). Can do. Further, light-transmitting indium tin oxide (ITO), ITSO made of indium tin oxide and silicon oxide, organic indium, organic tin, zinc oxide, titanium nitride, or the like may be combined.

In the through hole 125 formed in the gate insulating layer 105, the wiring layer 116 and the gate electrode layer 104 are electrically connected. A part of the wiring layer 117 forms a capacitor element.

    By combining the droplet discharge method, material loss can be prevented and costs can be reduced as compared to the entire surface coating formation by spin coating or the like. According to the present invention, wirings and the like can be stably formed even if they are designed to be densely and complicatedly arranged due to downsizing and thinning.

Next, a first electrode layer 119 is formed by selectively discharging a composition containing a conductive material over the gate insulating layer 105 (see FIG. 6). When light is emitted from the substrate 100 side, the first electrode layer 119 is made of indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), and indium zinc oxide containing zinc oxide (ZnO). A predetermined pattern is formed by a composition containing a material (IZO (indium zinc oxide)), zinc oxide (ZnO), ZnO doped with gallium (Ga), tin oxide (SnO ₂ ), etc. May be.

Further, it is preferably formed of indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), or the like by a sputtering method. More preferably, indium tin oxide containing silicon oxide is used by a sputtering method using a target containing 2 to 10% by weight of silicon oxide in ITO. In addition, a conductive material in which ZnO is doped with gallium (Ga), indium zinc oxide (IZO (IZO) formed using a target in which silicon oxide is included and indium oxide is mixed with 2 to 20 wt% zinc oxide (ZnO). indium zinc oxide)) film may be used. After the first electrode layer 119 is formed by a sputtering method, a mask layer may be formed by a droplet discharge method and formed into a desired pattern by etching. In this embodiment, the first electrode layer 119 is formed using a light-transmitting conductive material by a droplet discharge method, and specifically includes indium tin oxide, ITO, and silicon oxide. It is formed using ITSO.

In this embodiment mode, the first electrode layer which is a gate electrode layer, a semiconductor layer, a source electrode layer or a drain electrode layer, or a pixel electrode layer is formed directly by a plurality of discharge processes or by a plurality of discharge processes. The example formed using the mask layer formed in the shape which has a node was shown in detail. Therefore, as illustrated in FIG. 6A, the gate electrode layer, the semiconductor layer, the source electrode layer, the drain electrode layer, and the first electrode layer reflect the shape of the droplets, and the shape is not linear. The shape has nodes with non-uniform width.

  The present invention is particularly used for stable formation of the source electrode layer and the drain electrode layer, and other gate electrode layers, semiconductor layers, and the like may be processed with a resist mask or the like. Such an example is shown in FIG. 34, since the present invention is used when forming the source or drain electrode layer 111 and the source or drain electrode layer 112, the source or drain electrode layer 111 and the source or drain electrode layer 112 are also used. The layer 112 can be formed stably even at a narrow interval. The same applies to the source or drain electrode layer 113 and the source or drain electrode layer 114.

The first electrode layer 119 can also be selectively formed over the gate insulating layer 105 before the source or drain electrode layer 113 is formed. In this case, in this embodiment mode, the connection structure of the source or drain electrode layer 113 and the first electrode layer 119 is a structure in which the source or drain electrode layer 113 is stacked over the first electrode layer. It becomes. When the first electrode layer 119 is formed before the source electrode layer or the drain electrode layer 113, the first electrode layer 119 can be formed in a flat formation region. Therefore, the first electrode layer 119 can be formed in a flat formation region. .

Alternatively, a structure in which an insulating layer serving as an interlayer insulating layer is formed over the source or drain electrode layer 113 and electrically connected to the first electrode layer 119 by a wiring layer may be used. In this case, instead of forming the opening (contact hole) by removing the insulating layer, a material having low wettability with respect to the insulating layer can be formed over the source or drain electrode layer 113. After that, when a composition containing an insulating material is applied by a coating method or the like, an insulating layer is formed in a region excluding a region where a substance having low wettability is formed.

After the insulating layer is solidified by heating, drying, or the like, a substance with low wettability is removed to form an opening. A wiring layer is formed so as to fill the opening, and a first electrode layer 119 is formed so as to be in contact with the wiring layer. When this method is used, there is an effect of simplifying the process because it is not necessary to form an opening by etching.

In addition, when a structure in which emitted light is emitted to the side opposite to the substrate 100 side and a top emission type EL display panel is manufactured, Ag (silver), Au (gold), Cu (copper), A composition composed mainly of metal particles such as W (tungsten) and Al (aluminum) can be used. As another method, a transparent conductive film or a light reflective conductive film is formed by a sputtering method, a mask pattern is formed by a droplet discharge method, and a first electrode layer 119 is formed by combining etching processes. Also good.

The first electrode layer 119 may be wiped with a CMP method or a polyvinyl alcohol-based porous material and polished so that the surface thereof is planarized. Further, after polishing using the CMP method, the surface of the first electrode layer 119 may be irradiated with ultraviolet rays, oxygen plasma treatment, or the like.

  Through the above steps, a TFT substrate for a display panel in which the bottom gate TFT and the first electrode layer 119 are connected to the substrate 100 is completed. The TFT of this embodiment mode is an inverted stagger type.

Next, an insulating layer 121 (also referred to as a partition wall) is selectively formed. The insulating layer 121 is formed over the first electrode layer 119 so as to have an opening. In this embodiment mode, the insulating layer 121 is formed over the entire surface, and is etched into a desired shape using a mask such as a resist. When the insulating layer 121 is formed by a droplet discharge method, a printing method, a dispenser method, or the like that can be directly and selectively formed, the etching process is not necessarily required. The insulating layer 121 can also be formed in a desired shape by the pretreatment of the present invention.

The insulating layer 121 is formed using silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, or other inorganic insulating materials, acrylic acid, methacrylic acid, and derivatives thereof, polyimide, aromatic, or aromatic. A heat-resistant polymer such as polyamide, polybenzimidazole, or a siloxane material may be used. You may form using photosensitive and non-photosensitive materials, such as an acryl and a polyimide. The insulating layer 121 preferably has a shape in which the radius of curvature continuously changes, and the coverage of the electroluminescent layer 122 and the second electrode layer 123 formed thereon is improved.

Alternatively, after the insulating layer 121 is formed by discharging a composition by a droplet discharge method, the surface may be pressed and flattened by pressure in order to improve the flatness. As a pressing method, unevenness may be reduced by scanning a roller-shaped object on the surface, or the surface may be pressed vertically with a flat plate-like object. Alternatively, the surface may be softened or dissolved with a solvent or the like, and the surface irregularities may be removed with an air knife. Further, polishing may be performed using a CMP method. This step can be applied when the surface is flattened when unevenness is generated by the droplet discharge method. When flatness is improved by this step, display unevenness of the display panel can be prevented and a high-definition image can be displayed.

A light emitting element is formed over a substrate 100 which is a TFT substrate for a display panel (see FIG. 7).

Before the electroluminescent layer 122 is formed, heat treatment is performed at 200 ° C. under atmospheric pressure to remove moisture adsorbed in the first electrode layer 119 and the insulating layer 121 or on the surface thereof. In addition, it is preferable to perform heat treatment at 200 to 400 ° C., preferably 250 to 350 ° C. under reduced pressure, and to form the electroluminescent layer 122 by vacuum deposition or droplet discharge under reduced pressure without being exposed to the air as it is. .

As the electroluminescent layer 122, materials that emit red (R), green (G), and blue (B) light are selectively formed by an evaporation method using an evaporation mask or the like. A material that emits red (R), green (G), and blue (B) light can be formed by a droplet discharge method (such as a low-molecular or high-molecular material) in the same manner as a color filter. In this case, a mask is not used. Both are preferable because RGB can be separately applied. A second electrode layer 123 is stacked over the electroluminescent layer 122 to complete a display device having a display function using a light emitting element.

Although not shown, it is effective to provide a passivation film so as to cover the second electrode layer 123. The protective film provided when forming the display device may have a single layer structure or a multilayer structure. As the passivation film, silicon nitride (SiN), silicon oxide (SiO ₂ ), silicon oxynitride (SiON), silicon nitride oxide (SiNO), aluminum nitride (AlN), aluminum oxynitride (AlON), nitrogen content is oxygen It is made of an insulating film containing aluminum nitride oxide (AlNO) or aluminum oxide, diamond-like carbon (DLC), or nitrogen-containing carbon film (CN _X ) that is higher than the content, and a single layer or a combination of the insulating films is used. Can do. For example, a laminate such as a nitrogen-containing carbon film (CN _x ) or silicon nitride (SiN), or an organic material can be used, or a laminate of polymers such as styrene polymer may be used. A siloxane material may also be used.

At this time, it is preferable to use a film with good coverage as the passivation film, and it is effective to use a carbon film, particularly a DLC film. Since the DLC film can be formed in the temperature range from room temperature to 100 ° C., it can be easily formed over the electroluminescent layer having low heat resistance. The DLC film is formed by a plasma CVD method (typically, an RF plasma CVD method, a microwave CVD method, an electron cyclotron resonance (ECR) CVD method, a hot filament CVD method, etc.), a combustion flame method, a sputtering method, or an ion beam evaporation method. It can be formed by laser vapor deposition. The reaction gas used for film formation was hydrogen gas and a hydrocarbon-based gas (for example, CH ₄ , C ₂ H ₂ , C ₆ H _6, etc.), ionized by glow discharge, and negative self-bias was applied. Films are formed by accelerated collision of ions with the cathode. The CN film may be formed using C ₂ H ₄ gas and N ₂ gas as reaction gases. The DLC film has a high blocking effect against oxygen and can suppress oxidation of the electroluminescent layer. Therefore, the problem that the electroluminescent layer is oxidized during the subsequent sealing process can be prevented.

As shown in FIG. 8B, a sealant 136 is formed and sealed using a sealing substrate 140. After that, a flexible wiring board may be connected to a gate wiring layer formed by being electrically connected to the gate electrode layer 103 to be electrically connected to the outside. The same applies to the source wiring layer formed by being electrically connected to the wiring layer 115 which is also the source wiring layer.

    A filler 135 is sealed between the substrate 100 having elements and the sealing substrate 140 for sealing. A dripping method can be used to enclose the filler as in the case of the liquid crystal material. Instead of the filler 135, an inert gas such as nitrogen may be filled. Further, by installing the desiccant in the display device, the light emitting element can be prevented from being deteriorated by moisture. The desiccant may be placed on the sealing substrate 140 side or on the substrate 100 side having elements, and may be placed in a region where the sealant 136 is formed with a recess formed in the substrate. In addition, when it is installed in a location corresponding to a region that does not contribute to display, such as a drive circuit region or a wiring region of the sealing substrate 140, the aperture ratio is not lowered even if the desiccant is an opaque substance. The filler 135 may be formed so as to include a hygroscopic material and may have a function of a desiccant. Thus, a display device having a display function using a light-emitting element is completed (see FIG. 8).

In addition, an FPC 139 is bonded to a terminal electrode layer 137 for electrically connecting the inside and the outside of the display device with an anisotropic conductive film 138 to be electrically connected to the terminal electrode layer 137.

    FIG. 8A shows a top view of the display device. As shown in FIG. 8A, the pixel region 150, the scanning line driving region 151a, the scanning line driving region 151b, and the connection region 153 are sealed between the substrate 100 and the sealing substrate 140 by a sealant 136. A signal line driver circuit 152 formed by an IC driver is provided on the substrate 100. A thin film transistor 133 and a thin film transistor 134 are provided in the driver circuit region, and a thin film transistor 131 and a thin film transistor 130 are provided in the pixel region, respectively.

Note that in this embodiment mode, a case where a light-emitting element is sealed with a glass substrate is shown; however, the sealing process is a process for protecting the light-emitting element from moisture and is mechanically sealed with a cover material. Either a method, a method of encapsulating with a thermosetting resin or an ultraviolet light curable resin, or a method of encapsulating with a thin film having a high barrier ability such as a metal oxide or a nitride is used. As the cover material, glass, ceramics, plastic, or metal can be used. However, when light is emitted to the cover material side, it must be translucent. In addition, the cover material and the substrate on which the light emitting element is formed are bonded together using a sealing material such as a thermosetting resin or an ultraviolet light curable resin, and the resin is cured by heat treatment or ultraviolet light irradiation treatment to form a sealed space. Form. It is also effective to provide a hygroscopic material typified by barium oxide in this sealed space. This hygroscopic material may be provided in contact with the sealing material, or may be provided on the partition wall or in the peripheral portion so as not to block light from the light emitting element. Further, the space between the cover material and the substrate on which the light emitting element is formed can be filled with a thermosetting resin or an ultraviolet light curable resin. In this case, it is effective to add a moisture absorbing material typified by barium oxide in the thermosetting resin or the ultraviolet light curable resin.

In the present embodiment, the switching TFT has been described in detail for a single gate structure, but a multi-gate structure such as a double gate structure may be used. FIG. 36 shows an example in which the thin film transistor 130 has a double gate structure. FIG. 36A is a top view of a pixel, and FIG. 36B is a cross-sectional view taken along line XY in FIG. The thin film transistor 130 is in contact with the gate electrode layer 103a, the gate electrode layer 103b, the semiconductor layer 107, the semiconductor layer 109a having n-type, the semiconductor layer 109b having n-type, and the semiconductor layer 109c having n-type in contact with a source electrode layer or a drain The electrode layer 111, the source or drain electrode layer 120, and the source or drain electrode layer 112 are provided. As described above, even when three or more source electrode layers or drain electrode layers are continuously adjacent to each other, the present invention can be stably formed at equal intervals.

In the case where a semiconductor is manufactured using a SAS or a crystalline semiconductor, an impurity region can be formed by adding an impurity imparting one conductivity type. In this case, the semiconductor layer may have impurity regions having different concentrations. For example, the vicinity of the channel region of the semiconductor layer and the region stacked with the gate electrode layer may be low-concentration impurity regions, and the outer region may be high-concentration impurity regions.

As described above, in the present embodiment, various patterns are directly formed on the substrate by using the droplet discharge method, thereby using a glass substrate of the fifth generation or later in which one side exceeds 1000 mm. However, a display panel can be easily manufactured.

According to the present invention, a desired pattern can be stably formed. In addition, there is little material loss, and cost reduction can be achieved. Therefore, a high-performance and highly reliable display device can be manufactured with high yield.

(Embodiment 3)
Embodiment modes of the present invention will be described with reference to FIGS. More specifically, a method for manufacturing a display device including a thin film transistor having a top gate planar structure to which the present invention is applied will be described. 13A to 18A are top views of a display device pixel portion, and FIGS. 13B to 18B are lines E- in FIGS. 13A to 18A. FIG. 19A is also a top view of the display device, and FIG. 19B is a cross-sectional view taken along line OW and line EP in FIG. 19A. Note that an example of a liquid crystal display device using a liquid crystal material as a display element is shown. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

As the substrate 200, a glass substrate made of barium borosilicate glass, alumino borosilicate glass, or the like, a quartz substrate, a metal substrate, or a plastic substrate having heat resistance that can withstand the processing temperature in this manufacturing process is used. Note that an insulating layer may be formed over the substrate 200. The insulating layer is formed as a single layer or a stacked layer using an oxide material or a nitride material containing silicon by a method such as a CVD method, a plasma CVD method, a sputtering method, or a spin coating method. This insulating layer may not be formed, but has an effect of blocking contaminants from the substrate 200.

    A conductive film 201 is formed over the substrate 200. The conductive film 201 can be formed by a CVD method, a sputtering method, a droplet discharge method, or the like. The material of the conductive film 201 is an element selected from Ag, Au, Ni, Pt, Pd, Ir, Rh, Ta, W, Ti, Mo, Al, and Cu, or an alloy material or compound containing the element as a main component What is necessary is just to form with a material. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used. Alternatively, a single layer structure or a multi-layer structure may be used, for example, a two-layer structure of a tungsten nitride (WN) film and a molybdenum (Mo) film, or a tungsten film, an alloy of aluminum and silicon (Al—Si). A three-layer structure in which a film and a titanium nitride film are sequentially stacked may be employed. In this embodiment mode, Al is used for the conductive film 201.

    In this embodiment, a mask layer is formed over the conductive film 201 by a droplet discharge method, the conductive film 201 is processed into a desired shape, and a source electrode layer and a drain electrode layer are formed. Therefore, in order to form the source electrode layer and the drain electrode layer that determine the channel width with high control, a mask layer is formed as described in Embodiment Mode 1. The wettability with respect to the composition containing the mask layer forming material on the surface of the conductive film 201 is controlled. In this embodiment mode, since it is desired to form a pixel region with a fine design, it is necessary to form a source electrode layer and a drain electrode layer with thin lines. Therefore, in this embodiment, treatment for further reducing the wettability of the surface of the conductive film 201 is performed so that the droplets are not wetted and spread. Specifically, a substance 202 having low wettability is formed over the conductive film 201 (see FIG. 13).

    As a substance having low wettability, a substance containing a fluorocarbon chain or a substance containing a silane coupling agent can be used. In this embodiment mode, FAS is used as the substance 202 having low wettability, and a FAS film is formed by a coating method. This wettability is for a liquid composition containing a mask layer forming material to be formed in a later step. In the present embodiment, when the mask layer is formed, the contact angle of the formation region with respect to the composition containing the mask layer forming material is preferably 20 degrees or more, more preferably 20 degrees or more and 40 degrees or less.

    A composition containing a mask layer forming material is discharged over the substance 202 with low wettability in two stages by a droplet discharge device 213 to form a mask layer 203a and a mask layer 203b. Adjacent mask layer 203a and mask layer 203b are ejected while being shifted so that the centers of the droplets do not overlap in the line width direction so that mask layers formed in the same stage are not adjacent to each other. The mask layer 203a and the mask layer 203b are formed in a continuous shape by overlapping dots by a plurality of stages of ejection. Therefore, the line width is not constant and the shape has nodes as shown in FIG. In this embodiment, since the droplet discharge position is controlled in the discharging step, the adjacent mask layer 203a and the mask layer 203b do not come into contact with each other, and the adjacent portions of the nodes can be avoided. . Therefore, the distance between the mask layer 203a and the mask layer 203b can be set narrow and can be formed stably. The mask layer 204a, the mask layer 204b, and the mask layer 204c are also ejected in a plurality of stages by a droplet ejection method to form a continuous shape (see FIG. 14).

    The conductive film 201 is processed into a desired shape using the mask layer 203a, the mask layer 203b, the mask layer 204a, the mask layer 204b, and the mask layer 204c, and the source or drain electrode layer 205 and the source or drain electrode layer 206 are processed. Then, the capacitor wiring layer 207 is formed (see FIG. 15). The source or drain electrode layer 205 and the source or drain electrode layer 206 can be formed in a desired shape which is arranged with a stable interval and does not cause a shape defect. Since the distance between the conductive layers can be reduced, the channel width can be reduced by using the conductive layers as a source electrode layer and a drain electrode layer. Therefore, a high-performance and highly reliable semiconductor device capable of high-speed operation can be manufactured. Since defects due to shape defects are reduced at the time of manufacturing, the yield is improved and the productivity is increased.

    In this embodiment, after the source or drain electrode layer 205, the source or drain electrode layer 206, and the capacitor wiring layer 207 are formed, the mask layer is removed, and then ultraviolet light is applied to the substance with low wettability. 202 is disassembled and removed.

    An n-type semiconductor layer is formed in the source or drain electrode layer 205 and the source or drain electrode layer 206, and is etched with a mask made of resist or the like. The resist may be formed using a droplet discharge method. A semiconductor layer is formed over the n-type semiconductor layer and processed again using a mask or the like. Thus, an n-type semiconductor layer 208a, an n-type semiconductor layer 208b, and a semiconductor layer 209 are formed (see FIG. 16). The n-type semiconductor layer includes a semiconductor layer containing an impurity element imparting n-type at a higher concentration and a semiconductor layer containing an impurity element imparting n-type at a lower concentration from the source or drain electrode layer side. It is good also as laminated | stacked.

Next, the gate insulating layer 212 is formed over the source electrode layer, the drain electrode layer, and the semiconductor layer. The gate insulating layer 212 may be formed of a material such as a silicon oxide material or a nitride material, and may be a stacked layer or a single layer. In this embodiment, a stacked layer of a silicon nitride film, a silicon oxide film, and a silicon nitride film is used.

    Next, a mask made of a resist or the like is formed over the gate insulating layer 212, and the gate insulating layer 212 is etched to form a through hole 215 (see FIG. 17). In this embodiment mode, a mask is selectively formed by a droplet discharge method.

    A composition containing a conductive material is discharged onto the gate insulating layer 212 by the droplet discharge device 214 to form the gate electrode layer 210. Similarly to the formation of the source electrode layer or the drain electrode layer, the wettability of the formation region of the gate electrode layer may be controlled. In this embodiment mode, wettability control is performed on the formation region of the gate electrode layer 210 to form a continuous shape by a plurality of stages of discharge. Therefore, the gate electrode layer 210 also has a shape having a node. Note that although not illustrated, wettability control at the time of forming the gate electrode layer 210 may be performed as if the material 202 having low wettability was formed over the conductive film 201.

Similarly to the source electrode layer and the drain electrode layer, the pixel electrode layer 211 is formed by forming a conductive film and then using a mask layer by a droplet discharge method. Therefore, the pixel electrode layer 211 also has a shape having a curvature in the periphery reflecting the shape of the mask layer formed by a droplet discharge method (see FIG. 18A). The pixel electrode layer 211 and the source or drain electrode layer 206 are electrically connected to each other through the previously formed through-hole 215. The pixel electrode layer 211 can be formed using a material similar to that of the first electrode layer 119 in Embodiment 2, and in the case of manufacturing a transmissive liquid crystal display panel, indium tin oxide (ITO), silicon oxide It may be formed in a predetermined pattern by a composition containing indium tin oxide (ITSO) containing zinc, zinc oxide (ZnO), tin oxide (SnO ₂ ), and the like, and may be formed by baking. In this manner, the thin film transistor 250 which is a forward staggered thin film transistor of this embodiment is manufactured (see FIG. 18B).

In this embodiment, the gate electrode layer, the semiconductor layer, the source or drain electrode layer, and the pixel electrode layer are directly formed by a plurality of discharge processes or formed into shapes having nodes by a plurality of discharge processes. An example of using the mask layer is shown in detail. Therefore, as shown in FIG. 18A, the gate electrode layer, the semiconductor layer, the source or drain electrode layer, and the pixel electrode layer reflect the shape of the liquid droplets, and the shape is not linear, and the line width is The shape has uneven nodes.

  The present invention is particularly used for stable formation of the source electrode layer and the drain electrode layer, and other gate electrode layers, semiconductor layers, and the like may be processed with a resist mask or the like. Such an example is shown in FIG. Also in FIG. 35, since the present invention is used when forming the source or drain electrode layer 205 and the source or drain electrode layer 206, the source or drain electrode layer 205 and the source or drain electrode layer 205 are also used. The layer 206 can be formed stably even at a narrow interval.

Next, an insulating layer 261 called an alignment film is formed by a dispenser method, a printing method, or a spin coating method so as to cover the pixel electrode layer 211 and the thin film transistor 250. Note that the insulating layer 261 can be selectively formed by a screen printing method or an offset printing method. Then, rubbing is performed. Subsequently, a sealant 282 is formed in a peripheral region where pixels are formed by a droplet discharge method.

    After that, an insulating substrate 263 functioning as an alignment film, a colored layer 264 functioning as a color filter, a conductor layer 265 functioning as a counter electrode, a counter substrate 266 provided with a polarizing plate 267 and a substrate 200 having TFTs are connected to a spacer 281. And a liquid crystal display device 262 can be provided in the gap (see FIGS. 18 and 19). A polarizing plate 268 is also formed on the side of the substrate 200 that does not have a TFT. A filler may be mixed in the sealing material, and a shielding film (black matrix) or the like may be formed on the counter substrate 266. Note that as a method for forming the liquid crystal layer 226, a dispenser type (dropping type) or a dip type (pumping type) in which liquid crystal is injected using a capillary phenomenon after the counter substrate 266 is attached can be used.

    A liquid crystal dropping injection method employing a dispenser method will be described with reference to FIG. In FIG. 30, 40 is a control device, 42 is an imaging means, 43 is a head, 33 is a liquid crystal, 35 and 45 are markers, 34 is a barrier layer, 32 is a sealing material, 30 is a TFT substrate, and 20 is a counter substrate. A closed loop is formed by the sealing material 32, and the liquid crystal 33 is dropped from the head 43 once or plural times therein. The head 43 includes a plurality of nozzles, and a large amount of liquid crystal material can be dropped at a time, thereby improving the throughput. When the viscosity of the liquid crystal material is high, the liquid crystal material is continuously discharged and adhered to the formation region while being connected. On the other hand, when the viscosity of the liquid crystal material is low, the liquid crystal material is ejected intermittently and droplets are dropped. At that time, a barrier layer 34 is provided to prevent the sealing material 32 and the liquid crystal 33 from reacting. Subsequently, the substrates are bonded together in a vacuum, and thereafter UV curing is performed to fill the liquid crystal. Further, a sealing material may be formed on the TFT substrate side, and the liquid crystal may be dropped.

    The spacer may be provided by dispersing particles of several μm, but in this embodiment, a method of forming a resin film on the entire surface of the substrate and then processing it into a desired shape is adopted. After applying such a spacer material with a spinner, it is formed into a predetermined pattern by exposure and development processing. Further, it is cured by heating at 150 to 200 ° C. in a clean oven or the like. The spacers produced in this way can have different shapes depending on the conditions of exposure and development processing, but preferably, the spacers are columnar and the top is flat, so that the opposite substrate is When combined, the mechanical strength of the liquid crystal display device can be ensured. The shape of the spacer can be conical or pyramidal, and there is no particular limitation.

A connection portion is formed to connect the inside of the display device formed by the above steps and an external wiring board. The insulator layer in the connection portion is removed by ashing using oxygen gas at or near atmospheric pressure. This treatment is performed using oxygen gas and one or more selected from hydrogen, CF ₄ , NF ₃ , and CHF ₃ . In this step, in order to prevent damage and destruction due to static electricity, ashing is performed after sealing using the counter substrate. However, if there is little influence from static electricity, it may be performed at any timing. .

    Subsequently, the terminal electrode layer 287 that is electrically connected to the pixel portion is provided with an FPC 286 that is a wiring substrate for connection through an anisotropic conductive layer 285 (see FIG. 19B). The FPC 286 plays a role of transmitting an external signal or potential. Through the above steps, a liquid crystal display device having a display function can be manufactured.

    FIG. 19A shows a top view of a liquid crystal display device. As shown in FIG. 19A, the pixel region 290, the scanning line driving region 291a, and the scanning line driving region 291b are sealed between the substrate 200 and the counter substrate 280 by a sealant 282, and are formed on the substrate 200. A signal line driver circuit 292 formed by an IC driver is provided. A driving circuit including a thin film transistor 283 and a thin film transistor 284 is provided in the driving region.

    Since the thin film transistor 283 and the thin film transistor 284 are n-channel thin film transistors in the peripheral driver circuit in this embodiment, an NMOS circuit including the thin film transistors 283 and 284 is provided.

    In this embodiment mode, an NMOS configuration is used in the drive circuit region to function as an inverter. As described above, in the case of the configuration of only PMOS and NMOS, the gate electrode layer and the source electrode layer or the drain electrode layer of some TFTs are connected.

    In this embodiment mode, the switching TFT has a single gate structure, but may have a double gate structure or a plurality of multi-gate structures. In the case where a semiconductor is manufactured using a SAS or a crystalline semiconductor, an impurity region can be formed by adding an impurity imparting one conductivity type. In this case, the semiconductor layer may have impurity regions having different concentrations. For example, the vicinity of the channel region of the semiconductor layer and the region stacked with the gate electrode layer may be low-concentration impurity regions, and the outer region may be high-concentration impurity regions.

As described above, in this embodiment, the process can be simplified. In addition, by forming various components (parts) and a mask layer directly on the substrate using the droplet discharge method, it is easy to use glass substrates of 5th generation and later with one side exceeding 1000 mm. A display panel can be manufactured.

    According to the present invention, a component constituting a display device can be formed in a desired pattern with good controllability. In addition, there is little material loss, and cost reduction can be achieved. Accordingly, a high-performance and highly reliable liquid crystal display device can be manufactured with high yield.

(Embodiment 4)
A thin film transistor is formed by applying the present invention, and a display device can be formed using the thin film transistor. When a light-emitting element is used and an n-channel transistor is used as a transistor for driving the light-emitting element, The light emitted from the light emitting element performs any one of bottom emission, top emission, and dual emission. Here, a stacked structure of light-emitting elements corresponding to each case will be described with reference to FIGS.

In this embodiment mode, channel protective thin film transistors 461, 471, and 481 to which the present invention is applied are used. The thin film transistor 481 is provided over a light-transmitting substrate 480, and includes a gate electrode layer 493, a gate insulating film 497, a semiconductor layer 494, an n-type semiconductor layer 495a, an n-type semiconductor layer 495b, and low wettability. A substance 482a, a substance 482b with low wettability, a source or drain electrode layer 487a, a source or drain electrode layer 487b, and a channel protective layer 496 are formed. When the source or drain electrode layer 487a and the source or drain electrode layer 487b are also formed using the droplet discharge method as described in Embodiment 1, the source and drain electrode layers are in desired positions. They can be formed at intervals. Therefore, since the channel width is determined by the distance between the source electrode layer and the drain electrode layer, even if the distance between the source electrode layer and the drain electrode layer is designed to be narrow, it can be formed without contact due to poor formation. The thin film transistor 481 having such a source electrode layer and a drain electrode layer can operate at high speed and has high reliability.

In this embodiment, a crystalline semiconductor layer is used as the semiconductor layer, and an n-type semiconductor layer is used as the one-conductivity-type semiconductor layer. Instead of forming an n-type semiconductor layer, conductivity may be imparted to the semiconductor layer by performing plasma treatment with a PH ₃ gas. The semiconductor layer is not limited to this embodiment mode, and an amorphous semiconductor layer can also be used as shown in Embodiment Mode 1. In the case where a crystalline semiconductor layer such as polysilicon is used as in this embodiment mode, an impurity having one conductivity type is formed by introducing (adding) an impurity into the crystalline semiconductor layer without forming a one conductivity type semiconductor layer. A region may be formed. In addition, an organic semiconductor such as pentacene can be used, and when an organic semiconductor is selectively formed by a droplet discharge method or the like, a processing step into a desired shape can be simplified.

In this embodiment, an amorphous semiconductor layer is crystallized as the semiconductor layer 494 to form a crystalline semiconductor layer. In the crystallization step, an element (also referred to as a catalyst element or a metal element) that promotes crystallization is added to the amorphous semiconductor layer, and crystallization is performed by heat treatment (at 550 ° C. to 750 ° C. for 3 minutes to 24 hours). As elements for promoting crystallization, metal elements for promoting crystallization of silicon include iron (Fe), nickel (Ni), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd). One or plural types selected from osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), and gold (Au) can be used. In this embodiment, nickel is used.

In order to remove or reduce the element that promotes crystallization from the crystalline semiconductor layer, a semiconductor layer containing an impurity element is formed in contact with the crystalline semiconductor layer and functions as a gettering sink. As the impurity element, an impurity element imparting n-type conductivity, an impurity element imparting p-type conductivity, a rare gas element, or the like can be used. For example, phosphorus (P), nitrogen (N), arsenic (As), antimony (Sb ), Bismuth (Bi), boron (B), helium (He), neon (Ne), argon (Ar), Kr (krypton), and Xe (xenon) can be used. In this embodiment, a semiconductor layer including an impurity element functioning as a gettering sink is formed using an n-type semiconductor layer including phosphorus (P) that is an impurity element imparting n-type conductivity. An n-type semiconductor layer is formed over the crystalline semiconductor layer containing an element that promotes crystallization, and heat treatment (at 550 ° C. to 750 ° C. for 3 minutes to 24 hours) is performed. The element that promotes crystallization contained in the crystalline semiconductor layer moves into the semiconductor layer having n-type, and the element that promotes crystallization in the crystalline semiconductor layer is removed or reduced. It is formed. On the other hand, the n-type semiconductor layer becomes an n-type semiconductor layer containing a metal element which is an element that promotes crystallinity, and then processed into a desired shape to have an n-type semiconductor layer 495a. The semiconductor layer 495b is formed. Thus, the n-type semiconductor layer functions as a gettering sink of the semiconductor layer 494 and also functions as a source region and a drain region as it is.

In this embodiment mode, the crystallization step and the gettering step of the semiconductor layer are performed by a plurality of heat treatments; however, the crystallization step and the gettering step can be performed by a single heat treatment. In this case, an amorphous semiconductor layer is formed, an element that promotes crystallization is added, a semiconductor layer serving as a gettering sink is formed, and then heat treatment is performed.

In this embodiment, the gate insulating layer is formed by stacking a plurality of layers, and a silicon nitride oxide film and a silicon oxynitride film are formed as the gate insulating film 497 from the gate electrode layer 493 side to have a two-layer stacked structure. The insulating layers to be stacked are preferably formed continuously while switching the reaction gas at the same temperature without breaking the vacuum in the same chamber. If formed continuously without breaking the vacuum, it is possible to prevent the interface between the stacked films from being contaminated.

For the channel protective layer 496, polyimide, polyvinyl alcohol, or the like may be dropped by a droplet discharge method. As a result, the exposure process can be omitted. As the channel protective layer, inorganic materials (silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, etc.), photosensitive or non-photosensitive organic materials (organic resin materials) (polyimide, acrylic, polyamide, polyimide amide, resist) , Benzocyclobutene, etc.), a material having a low dielectric constant (Low-k material), or a film made of a plurality of kinds, or a stack of these films. A siloxane material may also be used. As a manufacturing method, a vapor deposition method such as a plasma CVD method or a thermal CVD method, or a sputtering method can be used. Alternatively, a droplet discharge method, a printing method (a method for forming a pattern such as screen printing or offset printing), or a dispenser method can be used. A coating film obtained by a coating method can also be used.

First, a case where light is emitted to the substrate 480 side, that is, a case where bottom emission is performed will be described with reference to FIG. In this case, the first electrode layer 484 is formed in contact with the source or drain electrode layer 487b so as to be electrically connected to the thin film transistor 481, and the electroluminescent layer 485 and the second electrode layer 486 are formed thereover. Are sequentially stacked. The substrate 480 through which light is transmitted needs to have a light-transmitting property with respect to at least light in the visible region. Next, the case where radiation is performed on the side opposite to the substrate 460, that is, the case where top surface radiation is performed will be described with reference to FIG. The thin film transistor 461 can be formed in a manner similar to that of the thin film transistor described above.

A source or drain electrode layer 462 which is electrically connected to the thin film transistor 461 is in contact with and electrically connected to the first electrode layer 463. A first electrode layer 463, an electroluminescent layer 464, and a second electrode layer 465 are stacked in this order. The source or drain electrode layer 462 is a reflective metal layer, and reflects light emitted from the light emitting element to the upper surface of the arrow. Since the source or drain electrode layer 462 is stacked with the first electrode layer 463, a light-transmitting material is used for the first electrode layer 463 even if light is transmitted. Is reflected by the source or drain electrode layer 462 and radiates to the side opposite to the substrate 460. Needless to say, the first electrode layer 463 may be formed using a reflective metal film. Since light emitted from the light-emitting element is emitted through the second electrode layer 465, the second electrode layer 465 is formed using a light-transmitting material at least in the visible region. Finally, a case where light is emitted to the substrate 470 side and the opposite side, that is, a case where dual emission is performed will be described with reference to FIG. The thin film transistor 471 is also a channel protective thin film transistor. The first electrode layer 472 is electrically connected to the source or drain electrode layer 475 which is electrically connected to the semiconductor layer of the thin film transistor 471. A first electrode layer 472, an electroluminescent layer 473, and a second electrode layer 474 are stacked in this order. At this time, when both the first electrode layer 472 and the second electrode layer 474 are formed with a light-transmitting material or a thickness capable of transmitting light at least in the visible region, dual emission is realized. In this case, the insulating layer through which light is transmitted and the substrate 470 also need to have a light-transmitting property with respect to at least light in the visible region.

A mode of a light-emitting element which can be applied in this embodiment mode is shown in FIG. The light-emitting element has a structure in which an electroluminescent layer 860 is sandwiched between a first electrode layer 870 and a second electrode layer 850. It is necessary to select materials for the first electrode layer and the second electrode layer in consideration of the work function, and the first electrode layer and the second electrode layer are both anodes or cathodes depending on the pixel configuration. sell. In this embodiment mode, since the polarity of the driving TFT is an n-channel type, it is preferable that the first electrode layer be a cathode and the second electrode layer be an anode. In the case where the polarity of the driving TFT is a p-channel type, the first electrode layer may be an anode and the second electrode layer may be a cathode.

11A and 11B show the case where the first electrode layer 870 is an anode and the second electrode layer 850 is a cathode, and the electroluminescent layer 860 is formed from the first electrode layer 870 side. , Buffer layer 804 composed of a stack of HIL (hole injection layer) and HTL (hole transport layer), EML (light emitting layer) 803, buffer layer composed of a stack of ETL (electron transport layer) and EIL (electron injection layer) It is preferable to sequentially stack 802 and the second electrode layer 850, and the second electrode layer 850 is formed thereover. FIG. 11A illustrates a structure in which light is emitted from the first electrode layer 870. The first electrode layer 870 includes an electrode layer 805 made of a light-transmitting oxide conductive material, The electrode layer 850 includes, from the electroluminescent layer 860 side, an electrode layer 801 containing an alkali metal or alkaline earth metal such as LiF or MgAg and an electrode layer 800 formed of a metal material such as aluminum. FIG. 11B illustrates a structure in which light is emitted from the second electrode layer 850, and the first electrode layer 870 is formed using a metal such as aluminum or titanium or a concentration equal to or lower than the stoichiometric composition ratio with the metal. The electrode layer 807 is formed of a metal material containing nitrogen and the electrode layer 806 is formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%. The second electrode layer 850 is formed of an electrode layer 801 containing an alkali metal or alkaline earth metal such as LiF or MgAg and a metal material such as aluminum from the electroluminescent layer 860 side. Although each layer is configured to have a thickness of 100 nm or less so that light can be transmitted, light can be emitted from the second electrode layer 850.

FIGS. 11C and 11D show the case where the first electrode layer 870 is a cathode, the second electrode layer 850 is an anode, and the electroluminescent layer 860 is a first electrode layer that is a cathode. From the 870 side, a buffer layer 802 consisting of a laminate of EIL (electron injection layer) and ETL (electron transport layer), an EML (light emitting layer) 803, and a laminate of HTL (hole transport layer) and HIL (hole injection layer). The buffer layer 804 is preferably stacked in that order, and a second electrode layer 850 which is an anode is formed thereover. FIG. 11C illustrates a structure in which light is emitted from the first electrode layer 870. The first electrode layer 870 includes an electrode layer containing an alkali metal or an alkaline earth metal such as LiF or MgAg from the electroluminescent layer 860 side. 801 and an electrode layer 800 formed of a metal material such as aluminum, but each layer emits light from the first electrode layer 870 by setting the thickness to 100 nm or less so that light can be transmitted. It becomes possible to do. The second electrode layer includes, from the electroluminescent layer 860 side, a second electrode layer 806 formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%, a metal such as aluminum or titanium, or the The electrode layer 807 is formed of a metal material containing nitrogen at a concentration equal to or lower than the stoichiometric composition ratio of metal. FIG. 11D illustrates a structure in which light is emitted from the second electrode layer 850. The first electrode layer 870 includes an electrode layer containing an alkali metal or an alkaline earth metal such as LiF or MgAg from the electroluminescent layer 860 side. 801 and an electrode layer 800 formed of a metal material such as aluminum. The film thickness is large enough to reflect light emitted from the electroluminescent layer 860. The second electrode layer 850 includes an electrode layer 805 made of an oxide conductive material that transmits at least light in the visible region. The electroluminescent layer can have a single layer structure or a mixed structure in addition to the laminated structure.

In addition, as the electroluminescent layer, materials that emit red (R), green (G), and blue (B) light are selectively formed by an evaporation method using an evaporation mask, respectively. A material that emits red (R), green (G), and blue (B) light can be formed by a droplet discharge method (such as a low-molecular or high-molecular material) in the same manner as a color filter. In this case, a mask is not used. Both are preferable because RGB can be separately applied.

In the case of a top emission type, when light-transmitting ITO or ITSO is used for the second electrode layer, BzOs—Li in which Li is added to a benzoxazole derivative (BzOs) or the like can be used. Further, for example, EML may be Alq ₃ doped with a dopant (such as DCM in the case of R, DMQD in the case of G) corresponding to the emission colors of R, G, and B.

Note that the electroluminescent layer is not limited to the above materials. For example, instead of CuPc or PEDOT, an oxide such as molybdenum oxide (MoOx: x = 2 to 3) and α-NPD or rubrene can be co-evaporated to improve the hole injection property. The material of the electroluminescent layer can be used as an organic material (including a low molecule or a polymer), or a composite material of an organic material and an inorganic material. Hereinafter, materials for forming the light emitting element will be described in detail.

Among the charge injecting and transporting substances, substances having a particularly high electron transporting property include, for example, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), Bis (10-hydroxybenzo [h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) (-4-phenylphenolato) -aluminum (abbreviation: BAlq), quinoline skeleton or And metal complexes having a benzoquinoline skeleton. As a substance having a high hole-transport property, for example, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD), 4,4′-bis [ N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD) or 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: TDATA) ), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) (ie, benzene ring-nitrogen) And a compound having a bond of

Among the charge injecting and transporting materials, materials having a particularly high electron injecting property include alkali metal or alkaline earth metal compounds such as lithium fluoride (LiF), cesium fluoride (CsF), and calcium fluoride. Can be mentioned. In addition, a mixture of a substance having a high electron transporting property such as Alq ₃ and an alkaline earth metal such as magnesium (Mg) may be used.

Among the charge injecting and transporting materials, examples of the material having a high hole injecting property include molybdenum oxide (MoOx), vanadium oxide (VOx), ruthenium oxide (RuOx), tungsten oxide (WOx), and manganese oxide. Examples thereof include metal oxides such as (MnOx). In addition, phthalocyanine compounds such as phthalocyanine (abbreviation: H ₂ Pc) and copper phthalocyanine (CuPc) can be given.

The light emitting layer may be configured to perform color display by forming light emitting layers having different emission wavelength bands for each pixel. Typically, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) is formed. In this case as well, it is possible to improve color purity and prevent mirror reflection (reflection) of the pixel portion by providing a filter that transmits light in the emission wavelength band on the light emission side of the pixel. Can do. By providing the filter, it is possible to omit a circularly polarized plate that has been conventionally required, and it is possible to eliminate the loss of light emitted from the light emitting layer. Furthermore, a change in color tone that occurs when the pixel portion (display screen) is viewed obliquely can be reduced.

There are various kinds of light emitting materials. As a low-molecular organic light-emitting material, 4-dicyanomethylene-2-methyl-6- [2- (1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] -4H-pyran (abbreviation: DCJT) 4-dicyanomethylene-2-t-butyl-6- [2- (1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] -4H-pyran (abbreviation: DCJTB), periflanthene, 2 , 5-dicyano-1,4-bis [2- (10-methoxy-1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] benzene, N, N′-dimethylquinacridone (abbreviation: DMQd ), Coumarin 6, Coumarin 545T, Tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), 9,9′-bianthryl, 9,10-diphenylanthracene (abbreviation: DPA), 9,10-bis (2-naphthyl) anthracene (abbreviation: DNA) or the like can be used. Other substances may also be used.

On the other hand, the high molecular organic light emitting material has higher physical strength than the low molecular weight material, and the durability of the device is high. In addition, since the film can be formed by coating, the device can be manufactured relatively easily. The structure of the light emitting element using the polymer organic light emitting material is basically the same as that when the low molecular weight organic light emitting material is used. From the cathode side, the cathode, the organic light emitting layer, and the anode are stacked in this order. Become. However, when forming a light emitting layer using a high molecular weight organic light emitting material, it is difficult to form a laminated structure as in the case of using a low molecular weight organic light emitting material. . Specifically, it is a laminated structure in the order of the cathode, the light emitting layer, the hole transport layer, and the anode from the cathode side.

Since the light emission color is determined by the material for forming the light emitting layer, a light emitting element exhibiting desired light emission can be formed by selecting these materials. Examples of the polymer electroluminescent material that can be used for forming the light emitting layer include polyparaphenylene vinylene, polyparaphenylene, polythiophene, and polyfluorene.

Examples of the polyparaphenylene vinylene include poly (paraphenylene vinylene) [PPV] derivatives, poly (2,5-dialkoxy-1,4-phenylene vinylene) [RO-PPV], poly (2- (2′- Ethyl-hexoxy) -5-methoxy-1,4-phenylenevinylene) [MEH-PPV], poly (2- (dialkoxyphenyl) -1,4-phenylenevinylene) [ROPh-PPV] and the like. Examples of polyparaphenylene include derivatives of polyparaphenylene [PPP], poly (2,5-dialkoxy-1,4-phenylene) [RO-PPP], poly (2,5-dihexoxy-1,4-phenylene). ) And the like. The polythiophene series includes polythiophene [PT] derivatives, poly (3-alkylthiophene) [PAT], poly (3-hexylthiophene) [PHT], poly (3-cyclohexylthiophene) [PCHT], poly (3-cyclohexyl). -4-methylthiophene) [PCHMT], poly (3,4-dicyclohexylthiophene) [PDCHT], poly [3- (4-octylphenyl) -thiophene] [POPT], poly [3- (4-octylphenyl) -2,2 bithiophene] [PTOPT] and the like. Examples of the polyfluorene series include polyfluorene [PF] derivatives, poly (9,9-dialkylfluorene) [PDAF], poly (9,9-dioctylfluorene) [PDOF], and the like.

Note that when a hole-transporting polymer-based organic light-emitting material is sandwiched between an anode and a light-emitting polymer-based organic light-emitting material, hole injection properties from the anode can be improved. In general, an acceptor material dissolved in water is applied by spin coating or the like. In addition, since it is insoluble in an organic solvent, it can be stacked with the above-described light-emitting organic light-emitting material. Examples of the hole-transporting polymer organic light emitting material include a mixture of PEDOT and camphor sulfonic acid (CSA) as an acceptor material, a mixture of polyaniline [PANI] and polystyrene sulfonic acid [PSS] as an acceptor material, and the like. .

The light emitting layer can be configured to emit monochromatic or white light. In the case of using a white light emitting material, color display can be made possible by providing a filter (colored layer) that transmits light of a specific wavelength on the light emission side of the pixel.

To form a light emitting layer that emits white light, for _{example, Alq 3, Alq 3, Alq} 3 doped with Nile Red which is partly red light emitting pigment, p-EtTAZ, by TPD (aromatic diamine) evaporation A white color can be obtained by sequentially laminating. In the case where the EL is formed by a coating method using spin coating, it is preferable that baking is performed by vacuum heating after coating. For example, a poly (ethylenedioxythiophene) / poly (styrenesulfonic acid) aqueous solution (PEDOT / PSS) that acts as a hole injection layer is applied and baked on the entire surface, and then a luminescent center dye (1, 1,4,4-tetraphenyl-1,3-butadiene (TPB), 4-dicyanomethylene-2-methyl-6- (p-dimethylamino-styryl) -4H-pyran (DCM1), Nile Red, Coumarin 6 Etc.) A doped polyvinyl carbazole (PVK) solution may be applied to the entire surface and fired.

The light emitting layer can also be formed as a single layer, and an electron transporting 1,3,4-oxadiazole derivative (PBD) may be dispersed in hole transporting polyvinyl carbazole (PVK). Further, white light emission can be obtained by dispersing 30 wt% PBD as an electron transporting agent and dispersing an appropriate amount of four kinds of dyes (TPB, coumarin 6, DCM1, Nile red). In addition to the light-emitting element that can emit white light as shown here, a light-emitting element that can obtain red light emission, green light emission, or blue light emission can be manufactured by appropriately selecting the material of the light-emitting layer.

In addition to the singlet excited light emitting material, a triplet excited light emitting material containing a metal complex or the like may be used for the light emitting layer. For example, among red light emitting pixels, green light emitting pixels, and blue light emitting pixels, a red light emitting pixel having a relatively short luminance half time is formed of a triplet excitation light emitting material, and the other A singlet excited light emitting material is used. The triplet excited luminescent material has a feature that the light emission efficiency is good, so that less power is required to obtain the same luminance. That is, when applied to a red pixel, the amount of current flowing through the light emitting element can be reduced, so that reliability can be improved. As a reduction in power consumption, a red light-emitting pixel and a green light-emitting pixel may be formed using a triplet excitation light-emitting material, and a blue light-emitting pixel may be formed using a singlet excitation light-emitting material. By forming a green light-emitting element having high human visibility with a triplet excited light-emitting material, power consumption can be further reduced.

Examples of triplet excited luminescent materials include those using a metal complex as a dopant, and metal complexes having a third transition series element platinum as the central metal and metal complexes having iridium as the central metal are known. Yes. The triplet excited light-emitting material is not limited to these compounds, and a compound having the above structure and having an element belonging to group 8 to 10 in the periodic table as a central metal can also be used.

The substances forming the light-emitting layer listed above are examples, and functionalities such as a hole injection transport layer, a hole transport layer, an electron injection transport layer, an electron transport layer, a light emission layer, an electron block layer, and a hole block layer are included. A light emitting element can be formed by appropriately stacking each layer. Moreover, you may form the mixed layer or mixed junction which combined these each layer. The layer structure of the light emitting layer can be changed. Instead of having a specific electron injection region or light emitting region, a modification in which an electrode layer is provided or a light emitting material is dispersed is provided in the present invention. As long as it does not depart from the spirit of the present invention, it can be permitted.

A light-emitting element formed using the above materials emits light by being forward-biased. A pixel of a display device formed using a light-emitting element can be driven by a simple matrix method or an active matrix method. In any case, each pixel emits light by applying a forward bias at a specific timing, but is in a non-light emitting state for a certain period. By applying a reverse bias during this non-light emitting time, the reliability of the light emitting element can be improved. The light emitting element has a degradation mode in which the light emission intensity decreases under a constant driving condition and a degradation mode in which the non-light emitting area is enlarged in the pixel and the luminance is apparently decreased. However, alternating current that applies a bias in the forward and reverse directions. By performing a typical drive, the progress of deterioration can be slowed and the reliability of the light emitting device can be improved. Further, either digital driving or analog driving can be applied.

Therefore, although not shown in FIG. 12, a color filter (colored layer) may be formed over a sealing substrate facing a substrate having elements. The color filter (colored layer) can be selectively formed by a droplet discharge method. When a color filter (colored layer) is used, high-definition display can be performed. This is because the color filter (colored layer) can correct a broad peak to be sharp in the emission spectrum of each RGB.

As described above, the case where a material that emits light of each RGB is formed has been described. However, full color display can be performed by forming a material that emits light of a single color and combining a color filter and a color conversion layer. The color filter (colored layer) and the color conversion layer may be formed on, for example, a sealing substrate and attached to the substrate. In addition, as described above, any of the material that emits monochromatic light, the color filter (colored layer), and the color conversion layer can be formed by a droplet discharge method.

Of course, monochromatic light emission may be displayed. For example, an area color type display device may be formed using monochromatic light emission. As the area color type, a passive matrix type display unit is suitable, and characters and symbols can be mainly displayed.

    In the above configuration, a material having a low work function can be used as the cathode, and for example, Ca, Al, calcium fluoride, MgAg, AlLi, or the like is desirable. The electroluminescent layer may be any of a single layer type, a laminated type, and a mixed type having no layer interface. It is also formed from singlet materials, triplet materials, or combinations thereof, charge injection / transport materials containing organic compounds or inorganic compounds, and light-emitting materials, and low molecular organic compounds and medium molecular organic compounds (sublimation) based on the number of molecules. And an organic compound having a molecular number of 20 or less, or a chained molecule having a length of 10 μm or less), including one or more layers selected from macromolecular organic compounds, You may combine with the injection | pouring transport property or the hole injection transport property inorganic compound. The first electrode layer 484, the second electrode layer 465, the first electrode layer 472, and the second electrode layer 474 are formed using a transparent conductive film that transmits light. For example, indium oxide in addition to ITO and ITSO A transparent conductive film formed using a target mixed with 2 to 20 wt% zinc oxide (ZnO) is used. Note that plasma treatment in an oxygen atmosphere or heat treatment in a vacuum atmosphere is preferably performed before the first electrode layer 484, the first electrode layer 463, and the first electrode layer 472 are formed. The partition wall is formed using a material containing silicon, an organic material, and a compound material. A porous film may be used. However, it is preferable to use a photosensitive or non-photosensitive material such as acrylic or polyimide because the side surface has a shape in which the radius of curvature continuously changes and the upper thin film is formed without being cut off. This embodiment mode can be freely combined with Embodiment Mode 1 and Embodiment Mode 2.

(Embodiment 5)
Next, a mode in which a driver circuit for driving is mounted on the display panel manufactured in Embodiment Modes 2 to 4 will be described.

  First, a display device employing a COG method is described with reference to FIG. A pixel portion 2701 for displaying information such as characters and images is provided over the substrate 2700. A substrate provided with a plurality of drive circuits is divided into a rectangular shape, and a divided drive circuit (also referred to as a driver IC) 2751 is mounted on the substrate 2700. FIG. 27A illustrates a mode in which an FPC 2750 is mounted on the tip of a plurality of driver ICs 2751 and driver ICs 2751. Alternatively, the size of the division may be approximately the same as the length of the side of the pixel portion on the signal line side, a single driver IC may be provided, and the FPC 2750 may be mounted on the tip of the driver IC.

  Alternatively, a TAB method may be employed. In that case, a plurality of FPCs 2750 may be attached and mounted, and a driver IC may be mounted on the FPC 2750 as illustrated in FIG. As in the case of the COG method, a single driver IC may be mounted on a single FPC 2750. In this case, a metal piece or the like for fixing the driver IC may be attached together due to strength problems.

  A plurality of driver ICs mounted on these display panels may be formed on a rectangular substrate having a side of 300 mm to 1000 mm or more from the viewpoint of improving productivity.

  That is, a plurality of circuit patterns having a drive circuit portion and an input / output terminal as one unit may be formed on the substrate, and finally divided and taken out. The long side of the driver IC may be formed in a rectangular shape having a long side of 15 to 80 mm and a short side of 1 to 6 mm in consideration of the length of one side of the pixel unit and the pixel pitch. Or a length obtained by adding one side of the pixel portion and one side of each driver circuit.

  The advantage of the external dimensions of the driver IC over the IC chip lies in the length of the long side. When a driver IC formed with a long side of 15 to 80 mm is used, the number required for mounting corresponding to the pixel portion is as follows. This is less than when an IC chip is used, and the manufacturing yield can be improved. Further, when a driver IC is formed over a glass substrate, the shape of the substrate used as a base is not limited, and thus productivity is not impaired. This is a great advantage compared with the case where the IC chip is taken out from the circular silicon wafer.

  In the case where the scan line side driver circuit 3702 is formed over the substrate as shown in FIG. 26B, a driver IC in which a signal line side driver circuit is formed is mounted in a region outside the pixel portion 3701. Is done. These driver ICs are drive circuits on the signal line side. In order to form a pixel portion corresponding to RGB full color, 3072 signal lines are required in the XGA class, and 4800 lines are required in the UXGA class. The signal lines formed in such a number are divided into several blocks at the end of the pixel portion 3701 to form lead lines, and are collected according to the pitch of the output terminals of the driver IC.

  The driver IC is preferably formed of a crystalline semiconductor formed over a substrate, and the crystalline semiconductor is preferably formed by irradiating continuous-emitting laser light. Therefore, a continuous light emitting solid state laser or gas laser is used as an oscillator for generating the laser light. When a continuous light emission laser is used, a transistor can be formed using a polycrystalline semiconductor layer having a large grain size with few crystal defects. In addition, since the mobility and response speed are good, high-speed driving is possible, the operating frequency of the element can be improved as compared with the prior art, and there is less variation in characteristics, so that high reliability can be obtained. Note that for the purpose of further improving the operating frequency, the channel length direction of the transistor and the scanning direction of the laser light are preferably matched. This is because, in the laser crystallization process using a continuous-wave laser, the highest mobility is obtained when the channel length direction of the transistor and the scanning direction of the laser beam with respect to the substrate are substantially parallel (preferably −30 ° to 30 °). Is obtained. Note that the channel length direction corresponds to the direction in which current flows in the channel formation region, in other words, the direction in which charges move. The transistor thus fabricated has an active layer composed of a polycrystalline semiconductor layer in which crystal grains extend in the channel direction, which means that the crystal grain boundaries are formed substantially along the channel direction. means.

  In order to perform laser crystallization, it is preferable to significantly narrow down the laser beam, and the width of the laser beam shape (beam spot) should be about 1 mm to 3 mm, which is the same width of the short side of the driver IC. Is good. In order to ensure a sufficient and efficient energy density for the irradiated object, the laser light irradiation region is preferably linear. However, the line shape here does not mean a line in a strict sense, but means a rectangle or an ellipse having a large aspect ratio. For example, the aspect ratio is 2 or more (preferably 10 or more and 10,000 or less). In this manner, a method for manufacturing a display device with improved productivity can be provided by setting the width of the laser beam shape (beam spot) to the same length as the short side of the driver IC.

  As shown in FIGS. 27A and 27B, driver ICs may be mounted as both the scanning line driver circuit and the signal line driver circuit. In that case, the specifications of the driver ICs used on the scanning line side and the signal line side may be different.

In the pixel portion, a signal line and a scanning line intersect to form a matrix, and a transistor is arranged corresponding to each intersection. The present invention is characterized in that a TFT having an amorphous semiconductor or a semi-amorphous semiconductor as a channel portion is used as a transistor arranged in a pixel portion. The amorphous semiconductor is formed by a method such as a plasma CVD method or a sputtering method. A semi-amorphous semiconductor can be formed by a plasma CVD method at a temperature of 300 ° C. or lower. For example, even a non-alkali glass substrate having an outer dimension of 550 × 650 mm has a film thickness necessary for forming a transistor. Is formed in a short time. Such a feature of the manufacturing technique is effective in manufacturing a large-screen display device. In addition, a semi-amorphous TFT can obtain a field effect mobility of ² to 10 cm ² / V · sec by forming a channel formation region with SAS. In addition, when the present invention is used, a pattern can be formed in a desired shape with good controllability, and such a fine wiring with a short channel width can be stably formed without causing a defect such as a short circuit. . A TFT having electric characteristics necessary for sufficiently functioning a pixel can be formed. Therefore, this TFT can be used as a switching element for a pixel or an element constituting a driving circuit on the scanning line side. Therefore, a display panel that realizes system-on-panel can be manufactured.

By using TFTs in which the semiconductor layer is formed of SAS, the scanning line side driver circuit can also be integrally formed on the substrate. In the case of using TFTs in which the semiconductor layer is formed of AS, the scanning line side driver circuit and the signal Both of the line side driver circuits may be mounted by driver ICs.

In that case, it is preferable that the specifications of the driver ICs used on the scanning line side and the signal line side are different. For example, although a transistor constituting the driver IC on the scanning line side is required to have a withstand voltage of about 30 V, the driving frequency is 100 kHz or less, and a relatively high speed operation is not required. Therefore, it is preferable to set the channel length (L) of the transistors forming the driver on the scanning line side to be sufficiently large. On the other hand, it is sufficient for the transistor of the driver IC on the signal line side to have a withstand voltage of about 12V, but the drive frequency is about 65 MHz at 3V, and high speed operation is required. Therefore, it is preferable to set the channel length and the like of the transistors constituting the driver on the micron rule. When the present invention is used, fine pattern formation can be performed with good controllability, and it is possible to sufficiently cope with such micron rule.

The method for mounting the driver IC is not particularly limited, and a COG method, a wire bonding method, or a TAB method can be used.

  By setting the thickness of the driver IC to be the same as that of the counter substrate, the height between the two becomes substantially the same, which contributes to the reduction in thickness of the entire display device. In addition, since each substrate is made of the same material, thermal stress is not generated even when a temperature change occurs in the display device, and the characteristics of a circuit made of TFTs are not impaired. In addition, the number of driver ICs to be mounted on one pixel portion can be reduced by mounting the drive circuit with a driver IC that is longer than the IC chip as shown in this embodiment.

  As described above, a driver circuit can be incorporated in the display panel.

(Embodiment 6)
An example of a protection circuit included in the display device of the present invention will be described.

As shown in FIG. 27B, a protection circuit 2713 can be formed between the external circuit and the internal circuit. The protection circuit is composed of one or a plurality of elements selected from a TFT, a diode, a resistance element, a capacitance element, and the like, and the configurations and operations of some protection circuits will be described below. First, the configuration of an equivalent circuit diagram of a protection circuit arranged between an external circuit and an internal circuit and corresponding to one input terminal will be described with reference to FIG. The protection circuit illustrated in FIG. 24A includes p-channel thin film transistors 7220 and 7230, capacitor elements 7210 and 7240, and a resistance element 7250. The resistance element 7250 is a two-terminal resistor, and an input voltage Vin (hereinafter referred to as Vin) is applied to one end, and a low potential voltage VSS (hereinafter referred to as VSS) is applied to the other end.

  The protection circuit illustrated in FIG. 24B is an equivalent circuit diagram in which the p-channel thin film transistors 7220 and 7230 are substituted with rectifying diodes 7260 and 7270. The protection circuit illustrated in FIG. 24C is an equivalent circuit diagram in which the p-channel thin film transistors 7220 and 7230 are substituted with TFTs 7350, 7360, 7370, and 7380. Further, as a protection circuit having a different structure from the above, the protection circuit illustrated in FIG. 24D includes resistors 7280 and 7290 and an n-channel thin film transistor 7300. A protection circuit illustrated in FIG. 24E includes resistors 7280 and 7290, a p-channel thin film transistor 7310, and an n-channel thin film transistor 7320. By providing the protection circuit, a rapid change in potential can be prevented, and destruction or damage of the element can be prevented, so that reliability is improved. Note that the element forming the protection circuit is preferably formed using an amorphous semiconductor with excellent withstand voltage. This embodiment mode can be freely combined with the above embodiment modes.

    This embodiment mode can be used in combination with each of Embodiment Modes 1 to 5.

(Embodiment 7)
A structure of a pixel of the display panel described in this embodiment will be described with reference to an equivalent circuit diagram illustrated in FIG. In this embodiment, an example in which a light-emitting element (EL element) is used as a display element of a pixel is described.

  In the pixel shown in FIG. 10A, a signal line 710, a power supply line 711, a power supply line 712, a power supply line 713 are arranged in the column direction, and a scanning line 714 is arranged in the row direction. The TFT 701 is a switching TFT, the TFT 703 is a driving TFT, the TFT 704 is a current control TFT, and further includes a capacitor 702 and a light emitting element 705.

  The pixel shown in FIG. 10C is different from the pixel shown in FIG. 10A except that the gate electrode of the TFT 703 is connected to the power supply line 712 arranged in the row direction. is there. That is, both pixels shown in FIGS. 10A and 10C show the same equivalent circuit diagram. However, when the power supply line 712 is arranged in the column direction (FIG. 10A) and in the case where the power supply line 712 is arranged in the row direction (FIG. 10C), each power supply line is conductive on a different layer. Formed with body layers. Here, attention is paid to the wiring to which the gate electrode of the TFT 703 is connected, and in order to indicate that the layers for manufacturing these are different, FIGS. 10A and 10C are separately illustrated.

As a feature of the pixel shown in FIGS. 10A and 10C, a TFT 703 and a TFT 704 are connected in series in the pixel, and the channel length L ₃ , channel width W _{3 of} the TFT 703, channel length L _{4 of the} TFT 704, channel width W ₄ may be set to satisfy L ₃ / W ₃ : L ₄ / W ₄ = 5 to 6000: 1. As an example of satisfying 6000: 1, there is a case where L ₃ is 500 μm, W ₃ is 3 μm, L ₄ is 3 μm, and W ₄ is 100 μm.

Note that the TFT 703 operates in a saturation region and has a role of controlling a current value flowing through the light emitting element 705, and the TFT 704 has a role of operating in a linear region and controls supply of current to the light emitting element 705. Both TFTs preferably have the same conductivity type in terms of manufacturing process. The TFT 703 may be a depletion type TFT as well as an enhancement type. In the present invention having the above structure, since the TFT 704 operates in a linear region, a slight change in V _GS of the TFT 704 does not affect the current value of the light emitting element 705. That is, the current value of the light emitting element 705 is determined by the TFT 703 operating in the saturation region. The present invention having the above structure can provide a display device in which luminance unevenness of a light emitting element due to variation in TFT characteristics is improved and image quality is improved.

  In the pixel shown in FIGS. 10A to 10D, a TFT 701 controls input of a video signal to the pixel. When the TFT 701 is turned on and a video signal is input into the pixel, the capacitor 702 The video signal is held in Note that FIGS. 10A and 10C illustrate a structure in which the capacitor 702 is provided; however, the present invention is not limited to this, and the capacity for holding a video signal can be covered by a gate capacity or the like. The capacitor 702 is not necessarily provided explicitly.

  The light-emitting element 705 has a structure in which an electroluminescent layer is sandwiched between two electrodes, and a potential difference is generated between the pixel electrode and the counter electrode (between the anode and the cathode) so that a forward bias voltage is applied. Is provided. The electroluminescent layer is composed of a wide variety of materials such as organic materials and inorganic materials. The luminescence in the electroluminescent layer includes light emission (fluorescence) when returning from a singlet excited state to a ground state, and a triplet excited state. And light emission (phosphorescence) when returning to the ground state.

  The pixel shown in FIG. 10B has the same pixel structure as that shown in FIG. 10A except that a TFT 706 and a scanning line 716 are added. Similarly, the pixel illustrated in FIG. 10D has the same pixel structure as that illustrated in FIG. 10C except that a TFT 706 and a scanning line 716 are added.

  The TFT 706 is controlled to be turned on or off by a newly arranged scanning line 716. When the TFT 706 is turned on, the charge held in the capacitor 702 is discharged, and the TFT 704 is turned off. That is, the arrangement of the TFT 706 can forcibly create a state in which no current flows through the light emitting element 705. 10B and 10D can improve the duty ratio because the lighting period can be started at the same time as or immediately after the start of the writing period without waiting for signal writing to all the pixels. It becomes possible.

  In the pixel shown in FIG. 10E, a signal line 750, a power supply line 751, a power supply line 752, and a scanning line 753 are arranged in the column direction. Further, the TFT 741 is a switching TFT, the TFT 743 is a driving TFT, and further includes a capacitor element 742 and a light emitting element 744. The pixel shown in FIG. 10F has the same pixel structure as that shown in FIG. 10E except that a TFT 745 and a scanning line 754 are added. Note that the duty ratio of the structure in FIG. 10F can also be improved by the arrangement of the TFTs 745.

    As described above, when the present invention is used, a pattern such as a wiring can be formed accurately and stably without causing defective formation, so that high electrical characteristics and reliability can be imparted to the TFT. Therefore, it can sufficiently cope with applied technology for improving the display capability of the pixel in accordance with the purpose of use.

    This embodiment mode can be used in combination with each of Embodiment Modes 1, 2, and 4 to 6.

(Embodiment 8)
This embodiment will be described with reference to FIG. FIG. 9 shows an example in which an EL display module is formed using a TFT substrate 2800 manufactured by applying the present invention. In FIG. 9, a pixel portion including pixels is formed over the TFT substrate 2800.

  In FIG. 9, the same TFT as that formed in the pixel or the gate of the TFT and one of the source and the drain is connected between the driving circuit and the pixel outside the pixel portion, and similar to the diode. The protection circuit portion 2801 operated in the above is provided. As the driver circuit 2809, a driver IC formed of a single crystal semiconductor, a stick driver IC formed of a polycrystalline semiconductor film over a glass substrate, a driver circuit formed of SAS, or the like is applied.

  The TFT substrate 2800 is fixed to the sealing substrate 2820 through spacers 2806a and 2806b formed by a droplet discharge method. The spacer is preferably provided to keep the distance between the two substrates constant even when the substrate is thin and the area of the pixel portion is increased. Resin material having light-transmitting property at least in the visible region in the gap between the TFT substrate 2800 and the sealing substrate 2820 on the light-emitting element 2804 and the light-emitting element 2805 connected to the TFT 2802 and the TFT 2803, respectively. May be solidified by filling, or may be filled with anhydrous nitrogen or inert gas.

FIG. 9 shows a case where the light-emitting element 2804 and the light-emitting element 2805 have a top emission type (top emission type) configuration, in which light is emitted in the direction of the arrow shown in the drawing. Each pixel can perform multicolor display by changing the emission color of the pixels to red, green, and blue. At this time, by forming the colored layer 2807a, the colored layer 2807b, and the colored layer 2807c corresponding to each color on the sealing substrate 2820 side, the color purity of the emitted light can be increased. Alternatively, the pixel may be combined with a colored layer 2807a, a colored layer 2807b, or a colored layer 2807c as a white light emitting element.

  A driver circuit 2809 which is an external circuit is connected to a scanning line or a signal line connection terminal provided at one end of the external circuit board 2811 through a wiring board 2810. Further, a heat pipe 2813 and a heat radiating plate 2812 which are pipe-like high-efficiency heat conduction devices used for transferring heat to the outside of the device in contact with or close to the TFT substrate 2800 are provided to enhance the heat radiation effect. It is good also as a structure.

  Although the top emission EL module is shown in FIG. 9, the configuration of the light emitting element and the arrangement of the external circuit board may be changed to have a bottom emission structure, and of course, a dual emission structure in which light is emitted from both the upper and lower surfaces. In the case of a top emission type structure, an insulating layer serving as a partition wall may be colored and used as a black matrix. The partition walls can be formed by a droplet discharge method, and may be formed by mixing a resin material such as polyimide with a pigment-based black resin, carbon black, or the like, or may be a laminate thereof.

  In addition, the EL display module may block reflected light of light incident from the outside using a retardation plate or a polarizing plate. In the case of a top emission display device, an insulating layer serving as a partition may be colored and used as a black matrix. This partition wall can also be formed by a droplet discharge method or the like. Carbon black or the like may be mixed with a pigment-based black resin or a resin material such as polyimide, or may be laminated. A different material may be discharged to the same region a plurality of times by a droplet discharge method to form a partition wall. As the phase difference plate, a λ / 4 plate and a λ / 2 plate may be used and designed so as to control light. As a structure, it becomes a structure of a light emitting element, a sealing substrate (sealing material), a phase difference plate, a phase difference plate (λ / 4, λ / 2), a polarizing plate in order from the TFT element substrate side. The emitted light passes through these and is emitted to the outside from the polarizing plate side. The retardation plate and the polarizing plate may be installed on the side from which light is emitted, and may be installed on both sides as long as the display is a double-sided emission type that emits light on both sides. Further, an antireflection film may be provided outside the polarizing plate. This makes it possible to display a higher-definition and precise image.

  In the TFT substrate 2800, a sealing structure may be formed by attaching a resin film to the side where the pixel portion is formed using a sealing material or an adhesive resin. Although glass sealing using a glass substrate is described in this embodiment mode, various sealing methods such as resin sealing using a resin, plastic sealing using a plastic, and film sealing using a film can be used. A gas barrier film for preventing the permeation of water vapor may be provided on the surface of the resin film. By adopting a film sealing structure, further reduction in thickness and weight can be achieved.

    This embodiment mode can be used in combination with each of Embodiment Modes 1, 2, and 4 to 7.

(Embodiment 9)
This embodiment will be described with reference to FIGS. 20A and 20B. 20A and 20B illustrate an example in which a liquid crystal display module is formed using a TFT substrate 2600 manufactured by applying the present invention.

    FIG. 20A illustrates an example of a liquid crystal display module, in which a TFT substrate 2600 and a counter substrate 2601 are fixed to each other with a sealant 2602, and a pixel portion 2603 and a liquid crystal layer 2604 are provided therebetween to form a display region. The colored layer 2605 is necessary for color display. In the case of the RGB method, a colored layer corresponding to each color of red, green, and blue is provided corresponding to each pixel. Polarizing plates 2606 and 2607 and a lens film 2613 are provided outside the TFT substrate 2600 and the counter substrate 2601. The light source is composed of a cold cathode tube 2610 and a reflection plate 2611. A circuit board 2612 is connected to a wiring circuit 2608 and a TFT substrate 2600 by a flexible wiring board 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. . The liquid crystal display module uses a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, an ASM (Axial Symmetrical Aligned Micro mode, etc.). Can do.

    In particular, a display device manufactured according to the present invention can have higher performance by using an OCB mode capable of high-speed response. FIG. 20B is an example in which the OCB mode is applied to the liquid crystal display module of FIG. 20A, and is an FS-LCD (Field sequential-LCD). The FS-LCD emits red light, green light, and blue light in one frame period, and can perform color display by combining images using time division. Further, since each light emission is performed by a light emitting diode or a cold cathode tube, a color filter is unnecessary. Therefore, since it is not necessary to arrange the color filters of the three primary colors, 9 times as many pixels can be displayed with the same area. On the other hand, since three colors of light are emitted in one frame period, a high-speed response of the liquid crystal is required. When the FS mode and the OCB mode are applied to the display device of the present invention, a display device or a liquid crystal television device with higher performance and higher image quality can be completed.

    The liquid crystal layer in the OCB mode has a so-called π cell structure. The π cell structure is a structure in which the pretilt angles of liquid crystal molecules are aligned in a plane-symmetric relationship with respect to the center plane between the active matrix substrate and the counter substrate. The alignment state of the π cell structure is splay alignment when no voltage is applied between the substrates, and shifts to bend alignment when a voltage is applied. When a voltage is further applied, the bend-aligned liquid crystal molecules are aligned perpendicularly to both substrates, and light is transmitted. In the OCB mode, high-speed response that is about 10 times faster than the conventional TN mode can be realized.

    Further, as a mode corresponding to the FS mode, HV-FLC, SS-FLC, or the like using a ferroelectric liquid crystal (FLC) capable of high-speed operation can be used. In the OCB mode, nematic liquid crystal having a relatively low viscosity is used, and in HV-FLC and SS-FLC, smectic liquid crystal is used. it can.

    In addition, the high-speed optical response speed of the liquid crystal display module is increased by narrowing the cell gap of the liquid crystal display module. The speed can also be increased by reducing the viscosity of the liquid crystal material. The increase in speed is more effective when the pixel (dot) pitch in the pixel region of the TN mode liquid crystal display module is 30 μm or less.

    The liquid crystal display module in FIG. 20B is a transmissive liquid crystal display module, and a red light source 2910a, a green light source 2910b, and a blue light source 2910c are provided as light sources. A control unit 2912 is installed to control on / off of the red light source 2910a, the green light source 2910b, and the blue light source 2910c. The light emission of each color is controlled by the control unit 2912, light enters the liquid crystal, an image is synthesized using time division, and color display is performed.

    As described above, when the present invention is used, a highly delicate and highly reliable liquid crystal display module can be manufactured.

    This embodiment mode can be used in combination with each of Embodiment Mode 1, Embodiment Mode 3, Embodiment Mode 5, and Embodiment Mode 6.

(Embodiment 10)
A television device can be completed with the display device formed according to the present invention. FIG. 21 is a block diagram illustrating a main configuration of the television device. In the display panel, only the pixel portion 601 is formed as shown in FIG. 26A, and the scan line side driver circuit 603 and the signal line side driver circuit 602 have a TAB method as shown in FIG. And a case where the TFT is formed by a COG method as shown in FIG. 27A, a TFT is formed as shown in FIG. 26B, and the pixel portion 601 and the scanning line side driver circuit 603 are mounted on the substrate. In the case where the signal line side driver circuit 602 is formed as a separate driver IC and formed integrally therewith, and the pixel portion 601, the signal line side driver circuit 602, and the scanning line side driver circuit 603 are mounted on the substrate as shown in FIG. However, any form is possible.

    As other external circuit configurations, on the input side of the video signal, among the signals received by the tuner 604, the video signal amplifier circuit 605 that amplifies the video signal, and the signals output from the video signal amplifier circuit 605 are red, green, and blue colors. And a control circuit 607 for converting the video signal into the input specification of the driver IC. The control circuit 607 outputs signals to the scanning line side and the signal line side, respectively. In the case of digital driving, a signal dividing circuit 608 may be provided on the signal line side and an input digital signal may be divided into m pieces and supplied.

    Of the signals received by the tuner 604, the audio signal is sent to the audio signal amplification circuit 609, and the output is supplied to the speaker 613 through the audio signal processing circuit 610. The control circuit 611 receives the receiving station (reception frequency) and volume control information from the input unit 612 and sends a signal to the tuner 604 and the audio signal processing circuit 610.

These liquid crystal display modules and EL display modules can be assembled into a housing as shown in FIGS. 23A and 23B to complete a television device. When the EL display module as shown in FIG. 9 is used, the EL television device can be completed. When the liquid crystal display module as shown in FIGS. 20A and 20B is used, a liquid crystal television device can be completed. A main screen 2003 is formed by the display module, and a speaker portion 2009, operation switches, and the like are provided as other accessory equipment. Thus, a television device can be completed according to the present invention.

A display panel 2002 is incorporated in a housing 2001, and general television broadcasting is received by a receiver 2005, and connected to a wired or wireless communication network via a modem 2004 (one direction (from a sender to a receiver)). ) Or bi-directional (between the sender and the receiver, or between the receivers). The television device can be operated by a switch incorporated in the housing or a separate remote control device 2006, and the remote control device 2006 also includes a display unit 2007 for displaying information to be output. good.

  In addition, the television device may have a configuration in which a sub screen 2008 is formed using the second display panel in addition to the main screen 2003 to display channels, volume, and the like. In this configuration, the main screen 2003 may be formed using an EL display panel with an excellent viewing angle, and the sub screen may be formed using a liquid crystal display panel that can display with low power consumption. In order to prioritize the reduction in power consumption, the main screen 2003 may be formed using a liquid crystal display panel, the sub screen may be formed using an EL display panel, and the sub screen may blink. When the present invention is used, a highly reliable display device can be obtained even when such a large substrate is used and a large number of TFTs and electronic components are used.

FIG. 23B illustrates a television device having a large display portion of 20 to 80 inches, for example, which includes a housing 2010, a display portion 2011, a remote control device 2012 that is an operation portion, a speaker portion 2013, and the like. The present invention is applied to manufacture of the display portion 2011. The television set in FIG. 23B is a wall-hanging type and does not require a large installation space.

  Of course, the present invention is not limited to a television device, but can be applied to various uses such as a monitor for a personal computer, an information display board in a railway station or airport, an advertisement display board in a street, etc. can do.

(Embodiment 11)
Various display devices can be manufactured by applying the present invention. That is, the present invention can be applied to various electronic devices in which these display devices are incorporated in a display portion.

  Such electronic devices include video cameras, digital cameras, projectors, head mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, game machines, personal digital assistants (mobile computers, mobile phones, electronic books, etc.) ), An image reproducing device including a recording medium (specifically, an apparatus including a display capable of reproducing a recording medium such as Digital Versatile Disc (DVD) and displaying the image). Examples thereof are shown in FIG.

  FIG. 22A illustrates a personal computer, which includes a main body 2101, a housing 2102, a display portion 2103, a keyboard 2104, an external connection port 2105, a pointing mouse 2106, and the like. The present invention is applied to manufacturing the display portion 2103. When the present invention is used, a highly reliable high-quality image can be displayed even if the size is reduced and wiring and the like are refined.

  FIG. 22B shows an image reproduction device (specifically, a DVD reproduction device) provided with a recording medium, which includes a main body 2201, a housing 2202, a display portion A 2203, a display portion B 2204, and a recording medium (DVD etc.) reading portion 2205. , An operation key 2206, a speaker portion 2207, and the like. The display portion A2203 mainly displays image information, and the display portion B2204 mainly displays character information. The present invention is applied to the manufacture of the display portion A2203 and the display portion B2204. When the present invention is used, a highly reliable high-quality image can be displayed even if the size is reduced and wiring and the like are refined.

FIG. 22C illustrates a mobile phone, which includes a main body 2301, an audio output portion 2302, an audio input portion 2303, a display portion 2304, operation switches 2305, an antenna 2306, and the like. By applying the display device manufactured according to the present invention to the display portion 2304, a highly reliable and high-quality image can be displayed even in a mobile phone that is downsized and wiring and the like are precise.

FIG. 22D illustrates a video camera, which includes a main body 2401, a display portion 2402, a housing 2403, an external connection port 2404, a remote control reception portion 2405, an image receiving portion 2406, a battery 2407, an audio input portion 2408, an eyepiece portion 2409, and an operation. Key 2410 and the like. The present invention can be applied to the display portion 2402. By applying the display device manufactured according to the present invention to the display portion 2304, a highly reliable and high-quality image can be displayed even with a video camera that is downsized and wiring and the like are precise. This embodiment mode can be freely combined with the above embodiment modes.
(Embodiment 12)

According to the present invention, a semiconductor device functioning as a chip having a processor circuit (also referred to as a wireless chip, a wireless processor, a wireless memory, or a wireless tag) can be formed. The semiconductor device of the present invention has a wide range of uses. For example, banknotes, coins, securities, certificates, bearer bonds, packaging containers, books, recording media, personal items, vehicles, foods, clothing It can be used in health supplies, daily necessities, medicines and electronic devices.

Banknotes and coins are money that circulates in the market, and include those that are used in the same way as money in a specific area (cash vouchers), commemorative coins, and the like. Securities refer to checks, securities, promissory notes, and the like, and can be provided with a chip 90 having a processor circuit (see FIG. 28A). The certificate refers to a driver's license, a resident's card, and the like, and a chip 91 having a processor circuit can be provided (see FIG. 28B). Personal belongings refer to bags, glasses, and the like, and can be provided with a chip 96 including a processor circuit (see FIG. 28C). Bearer bonds refer to stamps, gift cards, and various gift certificates. Packaging containers refer to wrapping paper such as lunch boxes, plastic bottles, and the like, and can be provided with a chip 93 having a processor circuit (see FIG. 28D). Books refer to books, books, and the like, and can be provided with a chip 94 including a processor circuit (see FIG. 28E). The recording medium refers to DVD software, video tape, or the like, and can be provided with a chip 95 including a processor circuit (see FIG. 28F). The vehicles refer to vehicles such as bicycles, ships, and the like, and can be provided with a chip 97 including a processor circuit (see FIG. 28G). Foods refer to food products, beverages, and the like. Clothing refers to clothing, footwear, and the like. Health supplies refer to medical equipment, health equipment, and the like. Livingware refers to furniture, lighting equipment, and the like. Chemicals refer to pharmaceuticals, agricultural chemicals, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (TV receivers, flat-screen TV receivers), mobile phones, and the like.

    Forgery can be prevented by providing a chip having a processor circuit on bills, coins, securities, certificates, bearer bonds, and the like. In addition, by installing chips with processor circuits in personal items such as packaging containers, books, recording media, personal items, foods, daily necessities, electronic devices, etc., the efficiency of inspection systems and rental store systems can be improved. Can be planned. By providing a chip having a processor circuit to vehicles, health supplies, medicines, and the like, counterfeiting and theft can be prevented, and medicines can prevent mistakes in taking medicine. As a method for providing a chip having a processor circuit, the chip is provided on the surface of an article or embedded in the article. For example, a book may be embedded in paper, and a package made of an organic resin may be embedded in the organic resin.

Further, by applying a chip having a processor circuit that can be formed according to the present invention to an object management or distribution system, the function of the system can be enhanced. For example, by reading information recorded on a chip having a processor circuit provided on a tag with a reader / writer provided on the side of the belt conveyor, information such as a distribution process and a delivery destination is read out. Package distribution can be performed easily.

    A structure of a chip having a processor circuit which can be formed according to the present invention will be described with reference to FIG. A chip having a processor circuit is formed of a thin film integrated circuit 9303 and an antenna 9304 connected thereto. Further, the thin film integrated circuit and the antenna are sandwiched between cover materials 9301 and 9302. The thin film integrated circuit 9303 may be bonded to the cover material with an adhesive. In FIG. 29, one thin film integrated circuit 9303 is bonded to a cover material 9301 with an adhesive 9320 interposed therebetween.

The thin film integrated circuit 9303 is formed in the same manner as the TFT described in any of the above embodiments, and is peeled off by a peeling step and provided on the cover material. When the source electrode layer and the drain electrode layer of the TFT of the thin film integrated circuit 9303 are also formed using a droplet discharge method as described in Embodiment Mode 1, the source electrode layer and the drain electrode layer have a gap at a desired position. Can be formed. Since the channel width is determined by the distance between the source electrode layer and the drain electrode layer, even if the distance between the source electrode layer and the drain electrode layer is designed to be narrow, it can be formed without contact due to poor formation. A thin film transistor having such a source electrode layer and a drain electrode layer can operate at high speed and has high reliability. The semiconductor element used for the thin film integrated circuit 9303 is not limited to this. For example, a memory element, a diode, a photoelectric conversion element, a resistance element, a coil, a capacitor element, an inductor, or the like can be used in addition to the TFT.

As shown in FIG. 29, an interlayer insulating film 9311 is formed over the TFT of the thin film integrated circuit 9303, and an antenna 9304 connected to the TFT through the interlayer insulating film 9311 is formed. A barrier film 9312 made of a silicon nitride film or the like is formed over the interlayer insulating film 9311 and the conductive layer 9313.

The antenna 9304 is formed by discharging droplets having a conductor such as gold, silver, copper, or the like by a droplet discharge method, followed by drying and baking. By forming the antenna by a droplet discharge method, the number of steps can be reduced, and the cost can be reduced accordingly.

Cover materials 9301 and 9302 are films (made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, etc.), paper made of a fibrous material, base film (polyester, polyamide, inorganic vapor deposition film, paper, etc.) And a laminated film of an adhesive synthetic resin film (acrylic synthetic resin, epoxy synthetic resin, etc.) are preferably used. The film is bonded to the object by thermocompression bonding. When performing the bonding process, the film is either an adhesive layer provided on the outermost surface of the film or a layer provided on the outermost layer (adhesion). (Not the layer) is melted by heat treatment and bonded by pressure.

Further, by using an incineration-free pollution material such as paper, fiber, carbon graphite or the like for the cover material, it is possible to incinerate or cut a chip having a used processor circuit. Further, a chip having a processor circuit using these materials does not generate toxic gas even if it is incinerated, and is therefore pollution-free.

    Note that in FIG. 29, a chip having a processor circuit is provided on the cover material 9301 through an adhesive 9320; however, instead of the cover material 9301, a chip having a processor circuit may be attached to an article for use. .

    In this embodiment, an example in which a mask layer is manufactured using the present invention over a substrate having a surface with controlled wettability will be described.

    Two conductive films processed into a desired shape were stacked on a substrate, and a mask layer was formed thereon. Assuming that two parallel conductive layers are formed by processing the conductive film, the mask layer is formed into a desired shape of the conductive layer.

    A glass substrate was used as the substrate, and a first conductive film made of TaN and a second conductive film made of W were laminated. FAS was formed on the second conductive film by a coating method, and the wettability of the formation region of the mask layer was controlled. A liquid composition containing a mask layer forming material was discharged onto the surface of the second conductive film whose wettability was controlled using a droplet discharge method. The substrate was heated and the heating temperature was 45 degrees (° C.). The main component of the composition containing the mask layer forming material was polyimide, and surflon and ethylene glycol-n-monobutyl ether were mixed as a solvent. The droplet diameter immediately after adhering to the droplet formation region was 70 μm, and the overlap of the droplets was 20 μm. An optical micrograph of the produced mask layer is shown in FIG. As shown in FIG. 31A, a mask layer 83 and a mask layer 84 are formed adjacent to each other.

    A droplet discharge method will be described in detail with reference to FIG. FIG. 31B is a schematic diagram schematically showing the formed mask layer and the shape immediately after the droplets are attached to the formation region. The droplet discharge is roughly divided into four stages. As shown in the side of the schematic diagram, the first stage is a circle with an oblique diagonal line on the left, and the second stage is A circle with a diagonal line to the right is shown, the third stage is a circle indicated by a one-dot chain line, and the fourth stage is a circle indicated by a dotted line. A center line 85 indicates a line connecting the centers of the droplets ejected when the mask layer 83 is formed, and a center line 86 is a line connecting the centers of the droplets ejected when the mask layer 84 is formed. It is.

    In each stage, the droplets ejected in the same stage are ejected so as not to contact each other. In this embodiment, the interval between droplets ejected at the same stage is 100 μm. The droplet ejected in the third stage and the droplet ejected in the first stage are overlapped by 20 μm on the center line 85, and the droplet ejected in the fourth stage and the droplet ejected in the second stage are center lines. It was made to overlap 20 micrometers on 86. Further, on each center line 85 and center line 86, the liquid droplets were discharged so that the center of the droplet of the next stage comes to a position shifted by 50 μm from the center of the liquid droplet discharged in the previous stage.

    Both the mask layer 83 and the mask layer 84 are not formed as a continuous mask layer by one discharge, but as a continuous mask layer by two stages of discharge. Therefore, the liquid composition discharged earlier starts to solidify as the solvent in the composition evaporates over time. Therefore, since the liquid composition discharged so as to overlap the previously discharged composition has more fluidity, it flows toward the previously discharged composition and adheres to the formation region. The shape just after is not stopped. Therefore, as shown in FIG. 31, a mask layer 83 and a mask layer 84 having nodes having a large line width in the region of the composition discharged earlier and a thin line width in the region of the composition discharged later are formed. .

    In this embodiment, when the adjacent mask layers are formed, the second-stage droplet is located on the center line 85 and the center line 86 of each droplet at a position shifted from the center of the droplet ejected in the first stage. Discharge so that the center of Therefore, since the positions of the maximum line widths of the nodes included in the mask layer 83 and the mask layer 84 are also shifted, the mask layer 83 and the mask layer 84 are formed with an interval without contacting each other. Therefore, in this example, it was confirmed that a mask layer and a conductive layer having a desired shape could be manufactured without problems such as electrical characteristics caused by shape defects.

  When the first conductive film and the second conductive film are processed using the mask layer 83 and the mask layer 84, a conductive film having a desired shape that is arranged with a narrow conductive layer and does not cause a defective shape is provided. A layer can be formed. Since the distance between the conductive layers can be reduced, the channel width can be reduced by using the conductive layers as a source electrode layer and a drain electrode layer. Therefore, a high-performance and highly reliable semiconductor device capable of high-speed operation can be manufactured. Since defects due to shape defects are reduced at the time of manufacturing, the yield is improved and the productivity is increased.

  In this example, an example of a thin film transistor in which a source electrode layer and a drain electrode layer are formed using the mask layer formed in Example 1 is described.

  The thin film transistor formed in this example is shown in FIG. FIG. 32A is an optical micrograph of a thin film transistor, and FIG. 32B is a schematic diagram of a cross-sectional view taken along line QR in FIG. The thin film transistor manufactured in this embodiment is provided over an insulating layer 61 formed over a substrate 60 made of a glass substrate, and includes a gate electrode layer 62, a gate insulating layer 63, a semiconductor layer 64, and a semiconductor layer having one conductivity type. 65a, a semiconductor layer 65b having one conductivity type, a source or drain electrode layer 66a, and a source or drain electrode layer 66b.

  In addition, the characteristics shown in FIG. 33 can be obtained from the thin film transistor manufactured in this example. Three samples were measured. The solid line in FIG. 33 indicates the drain current (hereinafter also referred to as ID) value with respect to the gate voltage (hereinafter also referred to as VG) when the drain voltage (hereinafter also referred to as VD) value is 1V and 14V. Shows changes. On the other hand, the dotted line in FIG. 33 shows the change in field effect mobility (hereinafter also referred to as μFE) with respect to the VG value when the VD value is 1V and when the VD value is 14V.

  The insulating layer 61 is formed with a thickness of 100 nm using silicon oxynitride (SiON), the gate electrode layer 62 is formed with a thickness of 100 nm using tungsten, and the semiconductor layer 64 is an amorphous silicon film. A thickness of 100 nm was formed. An n-type semiconductor layer having a thickness of 100 nm was formed as the semiconductor layer 65a having one conductivity type and the semiconductor layer 65b having one conductivity type. The source or drain electrode layer 66a and the source or drain electrode layer 66b were stacked with a molybdenum film of 100 nm and an aluminum film of 100 nm.

  In this embodiment, the source electrode layer or drain electrode layer 66a and the source electrode layer or drain are formed using the mask layer having a desired shape which is arranged with a narrow interval and does not cause a shape defect as described in Embodiment 1. Processing to the electrode layer 66b was performed. Accordingly, the distance between the source or drain electrode layer 66a and the source or drain electrode layer 66b can be reduced, so that the channel width can be reduced. Therefore, a high-performance and highly reliable semiconductor device capable of high-speed operation can be manufactured. In addition, since defects due to shape defects are reduced at the time of manufacturing, the yield is improved and the productivity is increased.

The conceptual diagram explaining this invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 6A and 6B illustrate a display device of the present invention. Sectional drawing explaining the structural example of EL display module of this invention. FIG. 10 is a circuit diagram illustrating a structure of a pixel that can be applied to an EL display panel of the present invention. 3A and 3B each illustrate a structure of a light-emitting element that can be applied to the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 6A and 6B illustrate a display device of the present invention. 6A and 6B illustrate a display device of the present invention. Sectional drawing explaining the structural example of the liquid crystal display module of this invention. 1 is a block diagram illustrating a main configuration of an electronic device to which the present invention is applied. FIG. 11 illustrates an electronic device to which the present invention is applied. FIG. 11 illustrates an electronic device to which the present invention is applied. The figure which shows the protection circuit to which this invention is applied. 2A and 2B illustrate a structure of a droplet discharge device that can be applied to the present invention. The top view of the display apparatus of this invention. The top view of the display apparatus of this invention. 1 is a diagram showing a semiconductor device to which the present invention is applied. 1 is a diagram showing a semiconductor device to which the present invention is applied. The figure explaining the structure of the droplet dripping apparatus which can be applied to this invention. The experimental data of the sample produced in Example 1. The experimental data of the sample produced in Example 1. The experimental data of the sample produced in Example 1. The top view of the display apparatus of this invention. The top view of the display apparatus of this invention. 6A and 6B illustrate a display device of the present invention.

Claims (21)

A first wiring having a plurality of line widths;
A second wiring having a plurality of line widths;
The side ends of the first wiring and the second wiring have a wavy shape,
The first wiring and the second wiring are line symmetric with respect to a central axis,
The semiconductor device is characterized in that an interval between the first wiring and the second wiring is constant. A first wiring having a continuously changing line width;
A second wiring having a continuously changing line width;
The side ends of the first wiring and the second wiring have a continuous wavy shape,
The first wiring and the second wiring are line symmetric with respect to a central axis,
The semiconductor device is characterized in that an interval between the first wiring and the second wiring is constant. A first wiring having a periodically changing line width;
A second wiring whose line width is periodically changed,
The side ends of the first wiring and the second wiring have a wavy shape,
The first wiring and the second wiring are line symmetric with respect to a central axis,
The semiconductor device is characterized in that an interval between the first wiring and the second wiring is constant. A gate electrode layer, a gate insulating layer, a semiconductor layer, a source electrode layer, and a drain electrode layer;
The source electrode layer and the drain electrode layer have a plurality of line widths,
The side ends of the first wiring and the second wiring have a wavy shape,
The source electrode layer and the drain electrode layer are line symmetric with respect to a central axis,
The semiconductor device is characterized in that a distance between the source electrode layer and the drain electrode layer is constant. A gate electrode layer, a gate insulating layer, a semiconductor layer, a source electrode layer, and a drain electrode layer;
The line width of the source electrode layer and the drain electrode layer is continuously changed,
Side edges of the source electrode layer and the drain electrode layer have a continuous wavy shape,
The source electrode layer and the drain electrode layer are line symmetric with respect to a central axis,
The semiconductor device is characterized in that a distance between the source electrode layer and the drain electrode layer is constant. A gate electrode layer, a gate insulating layer, a semiconductor layer, a source electrode layer, and a drain electrode layer;
The line width of the source electrode layer and the drain electrode layer is periodically changed,
Side edges of the source electrode layer and the drain electrode layer have a wavy shape,
The source electrode layer and the drain electrode layer are line symmetric with respect to a central axis,
The semiconductor device is characterized in that a distance between the source electrode layer and the drain electrode layer is constant. A plurality of first droplets having a center on a first line in the substrate plane ejected by a first ejection step of a plurality of droplets made of a composition containing a conductive material on the substrate, and a plurality of droplets The first line formed by a plurality of third droplets having a center on the first line discharged between the first droplets by the second discharging step A first line that is symmetrical about the line;
A plurality of second droplets having a center on a second line parallel to the first line ejected by the first ejection step, and between the second droplets by the second ejection step A second wiring line formed symmetrically with respect to the second line, formed by a plurality of fourth droplets having a center on the discharged second line;
The semiconductor device is characterized in that an interval between the first wiring and the second wiring is constant.   8. The electronic device according to claim 1, wherein the semiconductor device is a display device, a video camera, a digital camera, a personal computer, or a portable information terminal. A plurality of first droplets having a center on a first line in the substrate surface by a first ejection step of a plurality of droplets made of a composition containing a conductive material on the substrate, and the first A plurality of second droplets each having a center on a second line parallel to the first line,
By ejecting a plurality of third droplets having a center on the first line between the first droplets by the second ejection step of the plurality of droplets, A plurality of fourth droplets having a center on the second line are ejected between a first conductive layer that is line symmetric with respect to the plurality of line widths and the second droplet. Thus, a second conductive layer that is line-symmetric with respect to the second line and has a plurality of line widths is formed with a predetermined interval, respectively. Method. A plurality of first droplets having a center on a first line in the substrate surface by a first ejection step of a plurality of droplets made of a composition containing a conductive material on the substrate, and the first A plurality of second droplets each having a center on a second line parallel to the first line,
By ejecting a plurality of third droplets having a center on the first line between the first droplets by the second ejection step of the plurality of droplets, A plurality of fourth droplets having a center on the second line are disposed between the first conductive layer that is line-symmetric with respect to the first conductive layer whose line width continuously changes and the second droplet. By discharging, a second conductive layer that is line-symmetric with respect to the second line and whose line width continuously changes is formed with a certain interval, respectively. A method for manufacturing a semiconductor device. A plurality of first droplets having a center on a first line in the substrate surface by a first ejection step of a plurality of droplets made of a composition containing a conductive material on the substrate, and the first A plurality of second droplets each having a center on a second line parallel to the first line,
By ejecting a plurality of third droplets having a center on the first line between the first droplets by the second ejection step of the plurality of droplets, A plurality of fourth droplets having a center on the second line are disposed between the first conductive layer that is line symmetric with respect to the first conductive layer whose line width changes periodically and the second droplet. By discharging, a second conductive layer that is line-symmetric with respect to the first line and whose line width periodically changes is formed with a certain interval, respectively. A method for manufacturing a semiconductor device.   12. The method for manufacturing a semiconductor device according to claim 9, wherein side end portions of the first conductive layer and the second conductive layer have a continuous wave shape.   12. The method for manufacturing a semiconductor device according to claim 9, wherein side end portions of the first conductive layer and the second conductive layer are wavy.   14. The process according to claim 9, wherein a process for controlling wettability with respect to the composition containing the conductive material is performed on a region to which a plurality of droplets made of the composition containing the conductive material adhere. A method for manufacturing a semiconductor device. Forming a conductive film on the substrate;
A plurality of first droplets having a center on a first line in the substrate surface by a first discharge step of a plurality of droplets made of a composition including a mask layer material on the conductive film; A plurality of second droplets each having a center on a second line parallel to the first line;
By ejecting a plurality of third droplets having a center on the first line between the first droplets by the second ejection step of the plurality of droplets, A plurality of fourth droplets having a center on the second line are ejected between the second mask and the first mask layer having line symmetry and a plurality of line widths. A second mask layer that is symmetrical with respect to the second line and has a plurality of line widths,
A semiconductor device, wherein the conductive film is processed using the first mask layer and the second mask layer to form a first conductive layer and a second conductive layer having a predetermined interval. Manufacturing method. Forming a conductive film on the substrate;
A plurality of first droplets having a center on a first line in the substrate surface by a first discharge step of a plurality of droplets made of a composition including a mask layer material on the conductive film; A plurality of second droplets each having a center on a second line parallel to the first line;
By ejecting a plurality of third droplets having a center on the first line between the first droplets by the second ejection step of the plurality of droplets, A plurality of fourth droplets having a center on the second line are disposed between the second mask and the first mask layer that is line symmetric with respect to the line width and the second droplet. By discharging, a second mask layer that is line-symmetric with respect to the second line and whose line width continuously changes is formed, respectively.
A semiconductor device, wherein the conductive film is processed using the first mask layer and the second mask layer to form a first conductive layer and a second conductive layer having a predetermined interval. Manufacturing method. Forming a conductive film on the substrate;
A plurality of first droplets having a center on a first line in the substrate surface by a first discharge step of a plurality of droplets made of a composition including a mask layer material on the conductive film; A plurality of second droplets each having a center on a second line parallel to the first line;
By ejecting a plurality of third droplets having a center on the first line between the first droplets by the second ejection step of the plurality of droplets, A plurality of fourth droplets having a center on the second line are provided between the second mask and the first mask layer that is line symmetric with respect to the line width and periodically changes. By discharging, a second mask layer that is line symmetric with respect to the second line and whose line width periodically changes is formed, respectively.
A semiconductor device, wherein the conductive film is processed using the first mask layer and the second mask layer to form a first conductive layer and a second conductive layer having a predetermined interval. Manufacturing method.   18. The method for manufacturing a semiconductor device according to claim 15, wherein side end portions of the first mask layer and the second mask layer have a continuous wave shape.   18. The method for manufacturing a semiconductor device according to claim 15, wherein side end portions of the first mask layer and the second mask layer are wavy.   20. The method for manufacturing a semiconductor device according to claim 15, wherein a treatment for controlling wettability with respect to the composition including the mask layer material is performed on the conductive film.   21. The method for manufacturing a semiconductor device according to claim 14, wherein a substance having a fluorocarbon group or a substance containing a silane coupling agent is formed as the treatment for controlling the wettability.