JP2006237187A - 樹脂封止型半導体パッケージの製造方法 - Google Patents
樹脂封止型半導体パッケージの製造方法 Download PDFInfo
- Publication number
- JP2006237187A JP2006237187A JP2005048259A JP2005048259A JP2006237187A JP 2006237187 A JP2006237187 A JP 2006237187A JP 2005048259 A JP2005048259 A JP 2005048259A JP 2005048259 A JP2005048259 A JP 2005048259A JP 2006237187 A JP2006237187 A JP 2006237187A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- sealing
- solvent
- resin
- semiconductor package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
【解決手段】 複数の同一パターンが碁盤目状に形成されたリードフレームの各パターンのダイパッドに半導体素子をダイボンドする工程と、半導体素子の電極パッドとリードフレームのインナーリードをワイヤによりワイヤボンドする工程と、リードフレームの隣接するパッケージ間のアウターリード上に溶剤可溶性樹脂を設ける工程と、リードフレーム上に実装された複数の半導体素子を封止樹脂で片面一括封止する封止工程と、封止工程の後にリードフレームを溶剤に浸漬することで溶剤可溶性樹脂を溶解除去する工程と、各々のパッケージに分離個片化する工程とを有する。
【選択図】 図1
Description
以下、本発明の実施の形態1に係る樹脂封止型半導体パッケージの製造方法について図1及び図2を用いて説明する。図1は、各工程における横断面図、図2は各工程におけるアウターリード切断位置における別方向から見た断面図である。
以下、本発明の実施の形態2に係る樹脂封止型半導体パッケージの製造方法について図3及び図4を用いて説明する。図3は、各工程における横断面図、図4は各工程におけるアウターリード切断位置における別方向から見た断面図である。図1又は図2と同様の構成要素には同じ番号を付し、説明を省略する。
図5は、本発明の実施の形態3に係る半導体パッケージの製造方法における封止工程を示す横断面図である。図示のように、片面一括封止に用いるシート状樹脂15aをリードフレーム11上に載置している。封止装置として真空ラミネータまたは真空プレスを用いる。
12 半導体素子
13 ワイヤ
14 溶剤可溶性樹脂
15 封止樹脂
15a シート状樹脂
17,17a めっき皮膜
Claims (4)
- 複数の同一パターンが碁盤目状に形成されたリードフレームの各パターンのダイパッドに半導体素子をダイボンドする工程と、
前記半導体素子の電極パッドと前記リードフレームのインナーリードをワイヤによりワイヤボンドする工程と、
前記リードフレームの隣接するパッケージ間のアウターリード上に溶剤可溶性樹脂を設ける工程と、
前記リードフレーム上に実装された複数の前記半導体素子を封止樹脂で片面一括封止する封止工程と、
前記封止工程の後に前記リードフレームを溶剤に浸漬することで前記溶剤可溶性樹脂を溶解除去する工程と、
各々のパッケージに分離個片化する工程とを有することを特徴とする半導体パッケージの製造方法。 - 前記溶剤可溶性樹脂を溶解除去した後に前記アウターリードに外装めっきをする工程を更に有することを特徴とする請求項1に記載の半導体パッケージの製造方法。
- 前記リードフレームに半導体素子をダイボンドする前に、前記リードフレームの少なくともアウターリードとなる領域に外装めっきをする工程を更に有することを特徴とする請求項1に記載の半導体パッケージの製造方法。
- 前記溶剤可溶性樹脂の高さを前記ワイヤの高さよりも高くし、前記片面一括封止にシート状樹脂を用いることを特徴とする請求項1〜3の何れか1項に記載の半導体パッケージの製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005048259A JP4418764B2 (ja) | 2005-02-24 | 2005-02-24 | 樹脂封止型半導体パッケージの製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005048259A JP4418764B2 (ja) | 2005-02-24 | 2005-02-24 | 樹脂封止型半導体パッケージの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006237187A true JP2006237187A (ja) | 2006-09-07 |
JP4418764B2 JP4418764B2 (ja) | 2010-02-24 |
Family
ID=37044527
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005048259A Expired - Fee Related JP4418764B2 (ja) | 2005-02-24 | 2005-02-24 | 樹脂封止型半導体パッケージの製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4418764B2 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008108872A (ja) * | 2006-10-25 | 2008-05-08 | Denso Corp | モールドパッケージおよびその製造方法 |
JP2014154785A (ja) * | 2013-02-12 | 2014-08-25 | Seiko Instruments Inc | 樹脂封止型半導体装置およびその製造方法 |
KR20150103337A (ko) | 2013-11-07 | 2015-09-09 | 아사히 가라스 가부시키가이샤 | 이형 필름, 및 반도체 패키지의 제조 방법 |
-
2005
- 2005-02-24 JP JP2005048259A patent/JP4418764B2/ja not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008108872A (ja) * | 2006-10-25 | 2008-05-08 | Denso Corp | モールドパッケージおよびその製造方法 |
JP2014154785A (ja) * | 2013-02-12 | 2014-08-25 | Seiko Instruments Inc | 樹脂封止型半導体装置およびその製造方法 |
KR20150103337A (ko) | 2013-11-07 | 2015-09-09 | 아사히 가라스 가부시키가이샤 | 이형 필름, 및 반도체 패키지의 제조 방법 |
US9613832B2 (en) | 2013-11-07 | 2017-04-04 | Asahi Glass Company, Limited | Mold release film and process for producing semiconductor package |
Also Published As
Publication number | Publication date |
---|---|
JP4418764B2 (ja) | 2010-02-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7439097B2 (en) | Taped lead frames and methods of making and using the same in semiconductor packaging | |
US8329509B2 (en) | Packaging process to create wettable lead flank during board assembly | |
TWI337775B (en) | Partially patterned lead frames and methods of making and using the same in semiconductor packaging | |
US7799611B2 (en) | Partially patterned lead frames and methods of making and using the same in semiconductor packaging | |
US6777265B2 (en) | Partially patterned lead frames and methods of making and using the same in semiconductor packaging | |
EP1335427B1 (en) | Resin-moulded semiconductor device | |
KR100789348B1 (ko) | 부분적으로 패터닝된 리드 프레임 및 이를 제조하는 방법및 반도체 패키징에서 이를 이용하는 방법 | |
TWI291756B (en) | Low cost lead-free preplated leadframe having improved adhesion and solderability | |
US20020074672A1 (en) | Semiconductor package without substrate and method of manufacturing same | |
JPH11260985A (ja) | リードフレーム,樹脂封止型半導体装置及びその製造方法 | |
JP2005223331A (ja) | リードフレーム、これを利用した半導体チップパッケージ及びその製造方法 | |
TWI274409B (en) | Process for manufacturing sawing type leadless semiconductor packages | |
US9659842B2 (en) | Methods of fabricating QFN semiconductor package and metal plate | |
JP2003174131A (ja) | 樹脂封止型半導体装置及びその製造方法 | |
JP4418764B2 (ja) | 樹脂封止型半導体パッケージの製造方法 | |
US20020048851A1 (en) | Process for making a semiconductor package | |
JP5299411B2 (ja) | リードフレームの製造方法 | |
JP4570797B2 (ja) | 半導体装置の製造方法 | |
JP2002134654A (ja) | 樹脂封止型半導体装置及びその製造方法 | |
JP2003188332A (ja) | 半導体装置およびその製造方法 | |
JP4033969B2 (ja) | 半導体パッケージ、その製造方法及びウェハキャリア | |
JP2002026192A (ja) | リードフレーム | |
JP4362902B2 (ja) | 樹脂封止型半導体装置の製造方法 | |
JP2002026168A (ja) | 半導体装置およびその製造方法 | |
JP2012186207A (ja) | リードフレーム、それを用いた半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20061222 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080818 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090818 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20091008 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20091124 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20091130 |
|
R150 | Certificate of patent (=grant) or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121204 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121204 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131204 Year of fee payment: 4 |
|
LAPS | Cancellation because of no payment of annual fees |