JP2006229195A - Semiconductor nonvolatile memory and its manufacturing method - Google Patents

Semiconductor nonvolatile memory and its manufacturing method Download PDF

Info

Publication number
JP2006229195A
JP2006229195A JP2005354507A JP2005354507A JP2006229195A JP 2006229195 A JP2006229195 A JP 2006229195A JP 2005354507 A JP2005354507 A JP 2005354507A JP 2005354507 A JP2005354507 A JP 2005354507A JP 2006229195 A JP2006229195 A JP 2006229195A
Authority
JP
Japan
Prior art keywords
film
nonvolatile memory
oxide film
memory device
silicon oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005354507A
Other languages
Japanese (ja)
Inventor
Tatsunori Kaneoka
竜範 金岡
Yoshiteru Maruyama
祥輝 丸山
Tomoshi Yamamoto
智志 山本
Toshiya Uenishi
俊哉 植西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2005354507A priority Critical patent/JP2006229195A/en
Priority to US11/335,504 priority patent/US20060166440A1/en
Publication of JP2006229195A publication Critical patent/JP2006229195A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02329Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
    • H01L21/02332Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/3143Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3144Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/511Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/518Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor nonvolatile memory in which leakage current is hard to generate in tunnel insulating film, and to provide its manufacturing method. <P>SOLUTION: A silicon nitriding oxide film 2b constituting a tunnel insulating film 2 is formed by processing a surface of silicon nitriding oxide film 2a in radical nitriding. Defect is hard to generate in a film formed by a radical nitriding process in comparison with oxynitride film by CVD method. And, by the radical nitriding process, damage caused by plasma is little compared with a conventional simple plasma nitriding process. Therefore, the semiconductor nonvolatile memory, in which the leakage current is hard to generate in the tunnel insulating film, can be obtained. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明は、トンネル絶縁膜を有する半導体不揮発性記憶装置及びその製造方法に関する。   The present invention relates to a semiconductor nonvolatile memory device having a tunnel insulating film and a manufacturing method thereof.

下記特許文献1のうちその実施の形態3においては、半導体不揮発性記憶装置のトンネル絶縁膜1を、熱酸化膜21とCVD(Chemical Vapor Deposition)法で形成された窒化膜23との積層構造で構成することが記載されている。   In Embodiment 3 of the following Patent Document 1, the tunnel insulating film 1 of the semiconductor nonvolatile memory device has a laminated structure of a thermal oxide film 21 and a nitride film 23 formed by a CVD (Chemical Vapor Deposition) method. The composition is described.

また、下記特許文献2のうちその第0026段落においては、半導体不揮発性記憶装置のトンネル絶縁膜15aを、プラズマ酸化膜の上にプラズマ窒化膜を積層した積層膜で構成することが記述されている。   In the second paragraph of Patent Document 2 below, it is described that the tunnel insulating film 15a of the semiconductor nonvolatile memory device is composed of a laminated film in which a plasma nitride film is laminated on a plasma oxide film. .

特開平11−317463号公報JP 11-317463 A 特開2004−47614号公報JP 2004-47614 A

半導体不揮発性記憶装置のトンネル絶縁膜のうち窒化膜部分をCVD法で形成すれば、窒化膜中に欠陥が生じやすかった。また、単純なプラズマ窒化処理によりトンネル絶縁膜の窒化膜部分を形成しただけでは、プラズマによるダメージが窒化膜に発生しやすかった。   If the nitride film portion of the tunnel insulating film of the semiconductor nonvolatile memory device is formed by the CVD method, defects are likely to occur in the nitride film. Further, if the nitride film portion of the tunnel insulating film is simply formed by a simple plasma nitriding process, plasma damage is likely to occur in the nitride film.

上記のような欠陥やダメージが窒化膜に発生すると、トンネル絶縁膜にリーク電流が生じやすくなり、半導体不揮発性記憶装置のデータ保持能力の低下を招く。   When such defects and damage occur in the nitride film, a leak current is likely to be generated in the tunnel insulating film, leading to a decrease in the data retention capability of the semiconductor nonvolatile memory device.

また、シリコン酸化膜の上にシリコン窒化膜を追加しても、酸化膜部分とシリコン基板等の半導体基板との界面の界面準位増大に基づく、半導体不揮発性記憶装置のデータ消去速度低下は改善しなかった。   In addition, even if a silicon nitride film is added on top of the silicon oxide film, the data erasure speed reduction of the semiconductor nonvolatile memory device is improved based on the increase in the interface state at the interface between the oxide film portion and the semiconductor substrate such as the silicon substrate I did not.

この発明は上記の事情に鑑みてなされたもので、トンネル絶縁膜にリーク電流が生じにくい半導体不揮発性記憶装置及びその製造方法を実現することを目的とする。また、トンネル絶縁膜と半導体基板との界面の界面準位が増大しにくい半導体不揮発性記憶装置及びその製造方法を実現することを目的とする。   The present invention has been made in view of the above circumstances, and an object thereof is to realize a semiconductor nonvolatile memory device in which a leak current hardly occurs in a tunnel insulating film and a manufacturing method thereof. It is another object of the present invention to realize a semiconductor nonvolatile memory device in which the interface state at the interface between the tunnel insulating film and the semiconductor substrate is unlikely to increase, and a manufacturing method thereof.

請求項1に記載の発明は、トンネル絶縁膜を含む半導体不揮発性記憶装置の製造方法であって、(a)前記トンネル絶縁膜を構成するシリコン酸化膜を半導体基板上に形成する工程と、(b)前記トンネル絶縁膜を構成する第1シリコン窒化酸化膜を前記シリコン酸化膜上に形成する工程とを備え、前記工程(b)において、前記シリコン酸化膜の表面をラジカル窒化することにより、前記第1シリコン窒化酸化膜を形成する半導体不揮発性記憶装置の製造方法である。   The invention according to claim 1 is a method for manufacturing a semiconductor nonvolatile memory device including a tunnel insulating film, wherein (a) a step of forming a silicon oxide film constituting the tunnel insulating film on a semiconductor substrate; b) forming a first silicon oxynitride film constituting the tunnel insulating film on the silicon oxide film, and radical nitriding the surface of the silicon oxide film in the step (b), A method for manufacturing a semiconductor nonvolatile memory device in which a first silicon oxynitride film is formed.

請求項3に記載の発明は、半導体基板と、前記半導体基板上に形成されたシリコン酸化膜と、前記シリコン酸化膜上に形成されたシリコン窒化酸化膜とを備え、前記シリコン酸化膜および前記シリコン窒化酸化膜は、トンネル絶縁膜を構成し、前記シリコン窒化酸化膜は、前記シリコン酸化膜の表面をラジカル窒化することにより形成された半導体不揮発性記憶装置である。   The invention according to claim 3 includes a semiconductor substrate, a silicon oxide film formed on the semiconductor substrate, and a silicon oxynitride film formed on the silicon oxide film, the silicon oxide film and the silicon oxide film The nitrided oxide film constitutes a tunnel insulating film, and the silicon nitrided oxide film is a semiconductor nonvolatile memory device formed by radical nitriding the surface of the silicon oxide film.

請求項4に記載の発明は、半導体基板と、シリコン酸化膜と、前記シリコン酸化膜上に形成された第1シリコン窒化酸化膜と、前記半導体基板と前記シリコン酸化膜との間に形成された第2シリコン窒化酸化膜とを備え、前記シリコン酸化膜、並びに、前記第1及び第2シリコン窒化酸化膜は、トンネル絶縁膜を構成する半導体不揮発性記憶装置である。   The invention according to claim 4 is formed between the semiconductor substrate, the silicon oxide film, the first silicon oxynitride film formed on the silicon oxide film, and the semiconductor substrate and the silicon oxide film. A semiconductor non-volatile memory device including a second silicon oxynitride film, wherein the silicon oxide film and the first and second silicon oxynitride films form a tunnel insulating film.

請求項1に記載の発明によれば、シリコン酸化膜の表面をラジカル窒化することにより、第1シリコン窒化酸化膜を形成する。ラジカル窒化処理により形成された膜は、CVD法による窒化膜に比べて、膜中に欠陥が生じにくい。また、ラジカル窒化処理によれば、従来の単純なプラズマ窒化処理に比べてプラズマによるダメージが少ない。よって、トンネル絶縁膜にリーク電流が生じにくい半導体不揮発性記憶装置を製造することができる。   According to the first aspect of the present invention, the first silicon oxynitride film is formed by radical nitriding the surface of the silicon oxide film. A film formed by radical nitriding is less likely to cause defects in the film than a nitride film formed by CVD. Further, the radical nitriding treatment causes less plasma damage compared to the conventional simple plasma nitriding treatment. Therefore, it is possible to manufacture a semiconductor nonvolatile memory device in which a leak current hardly occurs in the tunnel insulating film.

請求項3に記載の発明によれば、トンネル絶縁膜を構成するシリコン窒化酸化膜は、シリコン酸化膜の表面をラジカル窒化することにより形成されている。ラジカル窒化処理により形成された膜は、CVD法による窒化膜に比べて、膜中に欠陥が生じにくい。また、ラジカル窒化処理によれば、従来の単純なプラズマ窒化処理に比べてプラズマによるダメージが少ない。よって、トンネル絶縁膜にリーク電流が生じにくい半導体不揮発性記憶装置が得られる。   According to the third aspect of the present invention, the silicon oxynitride film constituting the tunnel insulating film is formed by radical nitriding the surface of the silicon oxide film. A film formed by radical nitriding is less likely to cause defects in the film than a nitride film formed by CVD. Further, the radical nitriding treatment causes less plasma damage compared to the conventional simple plasma nitriding treatment. Therefore, a semiconductor nonvolatile memory device in which a leak current hardly occurs in the tunnel insulating film can be obtained.

請求項4に記載の発明によれば、トンネル絶縁膜は、シリコン酸化膜、並びに、第1及び第2シリコン窒化酸化膜により構成される。よって、トンネル絶縁膜を更に強固にすることができ、トンネル絶縁膜にリーク電流が生じにくい半導体不揮発性記憶装置が得られる。また、半導体基板とシリコン酸化膜との間に第2シリコン窒化酸化膜が形成されているので、トンネル絶縁膜と半導体基板との界面の欠陥が生じにくく、トンネル絶縁膜と半導体基板との界面の界面準位が増大しにくい半導体不揮発性記憶装置が得られる。   According to the fourth aspect of the present invention, the tunnel insulating film is composed of the silicon oxide film and the first and second silicon oxynitride films. Therefore, the tunnel insulating film can be further strengthened, and a semiconductor nonvolatile memory device in which a leak current hardly occurs in the tunnel insulating film can be obtained. In addition, since the second silicon oxynitride film is formed between the semiconductor substrate and the silicon oxide film, defects at the interface between the tunnel insulating film and the semiconductor substrate are less likely to occur, and the interface between the tunnel insulating film and the semiconductor substrate is less likely to occur. A semiconductor nonvolatile memory device in which the interface state hardly increases can be obtained.

<実施の形態1>
本実施の形態は、トンネル絶縁膜を構成するシリコン窒化酸化膜を、シリコン酸化膜の表面をラジカル窒化することにより形成した半導体不揮発性記憶装置及びその製造方法である。
<Embodiment 1>
The present embodiment relates to a semiconductor nonvolatile memory device in which a silicon oxynitride film constituting a tunnel insulating film is formed by radical nitriding the surface of a silicon oxide film, and a method for manufacturing the same.

図1は、本実施の形態に係る半導体不揮発性記憶装置を示す図である。図1に示すように、この半導体不揮発性記憶装置は、シリコン基板等の半導体基板1を含んでいる。   FIG. 1 is a diagram showing a semiconductor nonvolatile memory device according to the present embodiment. As shown in FIG. 1, the semiconductor nonvolatile memory device includes a semiconductor substrate 1 such as a silicon substrate.

半導体基板1の表面には、シリコン酸化膜を主成分とする素子分離領域3と、半導体不揮発性記憶装置の一構成要素たるソース/ドレイン領域4とが形成されている。なお、ソース/ドレイン領域4は、半導体基板1の表面の一部にリンや砒素等のn型不純物が選択的に拡散されることにより形成された活性領域である。   Formed on the surface of the semiconductor substrate 1 are an element isolation region 3 having a silicon oxide film as a main component and a source / drain region 4 as one component of the semiconductor nonvolatile memory device. The source / drain region 4 is an active region formed by selectively diffusing n-type impurities such as phosphorus and arsenic on a part of the surface of the semiconductor substrate 1.

半導体基板1の上には、シリコン酸化膜2aが形成され、シリコン酸化膜2a上にはシリコン窒化酸化膜2bが形成されている。このシリコン窒化酸化膜2bは、後述するように、シリコン酸化膜2aの表面をラジカル窒化することにより形成されたものである。そして、シリコン酸化膜2aおよびシリコン窒化酸化膜2bで構成される積層膜が、半導体不揮発性記憶装置の1メモリセルのトンネル絶縁膜2として機能する。   A silicon oxide film 2a is formed on the semiconductor substrate 1, and a silicon oxynitride film 2b is formed on the silicon oxide film 2a. The silicon oxynitride film 2b is formed by radical nitriding the surface of the silicon oxide film 2a, as will be described later. The laminated film composed of the silicon oxide film 2a and the silicon oxynitride film 2b functions as the tunnel insulating film 2 of one memory cell of the semiconductor nonvolatile memory device.

トンネル絶縁膜2上には、リン等の不純物が添加されたポリシリコンを主成分とする浮遊ゲート電極5が形成されている。また、浮遊ゲート電極5上には、シリコン酸化膜6、シリコン窒化膜7およびシリコン酸化膜8の積層膜が形成されている。この積層膜は、半導体不揮発性記憶装置の1メモリセルの電荷保持膜15として機能する。   On the tunnel insulating film 2, a floating gate electrode 5 mainly composed of polysilicon doped with an impurity such as phosphorus is formed. A laminated film of a silicon oxide film 6, a silicon nitride film 7 and a silicon oxide film 8 is formed on the floating gate electrode 5. This stacked film functions as the charge holding film 15 of one memory cell of the semiconductor nonvolatile memory device.

電荷保持膜15上には、リン等の不純物が添加されたポリシリコンを主成分とする制御ゲート電極9が形成されている。そして、制御ゲート電極9の上面及び側面、並びに、電荷保持膜15、浮遊ゲート電極5およびトンネル絶縁膜2の側面を覆うように、シリコン酸化膜を主成分とする電気的絶縁膜10が形成されている。電気的絶縁膜10は、隣接する半導体不揮発性記憶装置のメモリセル間の電気的絶縁を図るため、設けられている。   On the charge retention film 15, a control gate electrode 9 mainly composed of polysilicon doped with an impurity such as phosphorus is formed. Then, an electrical insulating film 10 mainly composed of a silicon oxide film is formed so as to cover the upper and side surfaces of the control gate electrode 9 and the side surfaces of the charge holding film 15, the floating gate electrode 5 and the tunnel insulating film 2. ing. The electrical insulating film 10 is provided in order to achieve electrical insulation between memory cells of adjacent semiconductor nonvolatile memory devices.

半導体基板1上には、素子分離領域3、電気的絶縁膜10およびソース/ドレイン領域4を覆うように、シリコン酸化膜等を主成分とする層間絶縁膜12が形成されている。また、層間絶縁膜12上には、より上層の層間絶縁膜14が形成されている。   On the semiconductor substrate 1, an interlayer insulating film 12 mainly composed of a silicon oxide film or the like is formed so as to cover the element isolation region 3, the electrical insulating film 10 and the source / drain region 4. Further, an upper interlayer insulating film 14 is formed on the interlayer insulating film 12.

層間絶縁膜12内および層間絶縁膜12表面には、ソース/ドレイン領域4に導通するコンタクト金属配線11が形成されている。また、層間絶縁膜14内および層間絶縁膜14表面には、コンタクト金属配線11に導通するコンタクト金属配線13が形成されている。   In the interlayer insulating film 12 and on the surface of the interlayer insulating film 12, contact metal wiring 11 that is conductive to the source / drain region 4 is formed. Further, a contact metal wiring 13 that is electrically connected to the contact metal wiring 11 is formed in the interlayer insulating film 14 and on the surface of the interlayer insulating film 14.

次に、本実施の形態に係る半導体不揮発性記憶装置の製造方法について、図2〜図5を用いて説明する。   Next, a method for manufacturing the semiconductor nonvolatile memory device according to the present embodiment will be described with reference to FIGS.

まず、図2に示すように、半導体基板1の表面の所定の領域に、熱酸化法等により素子分離領域3を形成する。   First, as shown in FIG. 2, an element isolation region 3 is formed in a predetermined region on the surface of the semiconductor substrate 1 by a thermal oxidation method or the like.

次に、図3に示すように、トンネル絶縁膜2を構成するシリコン酸化膜2aを半導体基板1上に形成する。このシリコン酸化膜2aは、例えば熱酸化法により形成すればよい。より具体的には、例えば650〜900℃での水素と酸素との燃焼反応を利用したパイロジェニック酸化法や、あるいは、650〜1150℃の温度、50Torr以下の圧力下で生じる酸素と水素との反応により生成される酸化ラジカルを利用したラジカル酸化法等により、シリコン酸化膜2aを形成すればよい。   Next, as shown in FIG. 3, a silicon oxide film 2 a constituting the tunnel insulating film 2 is formed on the semiconductor substrate 1. The silicon oxide film 2a may be formed by, for example, a thermal oxidation method. More specifically, for example, a pyrogenic oxidation method using a combustion reaction between hydrogen and oxygen at 650 to 900 ° C., or oxygen and hydrogen generated at a temperature of 650 to 1150 ° C. and a pressure of 50 Torr or less. The silicon oxide film 2a may be formed by a radical oxidation method using oxidized radicals generated by the reaction.

次に、図4に示すように、トンネル絶縁膜2を構成するシリコン窒化酸化膜2bをシリコン酸化膜2a上に形成する。このシリコン窒化酸化膜2bは、シリコン酸化膜2aの表面をラジカル窒化(Radical Nitridation)することにより形成する。具体的には、アルゴンで希釈した窒素をプラズマ分解する過程で得られる、窒素ラジカルを利用すればよい。   Next, as shown in FIG. 4, a silicon oxynitride film 2b constituting the tunnel insulating film 2 is formed on the silicon oxide film 2a. The silicon oxynitride film 2b is formed by radical nitridation of the surface of the silicon oxide film 2a. Specifically, nitrogen radicals obtained in the process of plasma decomposition of nitrogen diluted with argon may be used.

従来のプラズマ窒化法では、窒素を含むガスの直流グロー放電によって高いエネルギー状態のプラズマを発生させ、このプラズマ生成で得られる窒素分子などのイオンが、処理物を加熱昇温すると同時に表面を活性化させていた。一方、ラジカル窒化法では、窒素を含むガスのグロー放電を精密に制御する。これにより、イオン密度が小さく、かつ、低いエネルギー状態のプラズマを発生させながら、高活性なラジカル(活性種)を有効に生成させて窒化処理を行うことができる。   In the conventional plasma nitriding method, a high energy plasma is generated by direct current glow discharge of a gas containing nitrogen, and ions such as nitrogen molecules obtained by this plasma generation activate the surface at the same time as the temperature of the treatment is increased by heating. I was letting. On the other hand, in radical nitriding, glow discharge of nitrogen-containing gas is precisely controlled. Thus, nitriding can be performed by effectively generating highly active radicals (active species) while generating plasma with a low ion density and a low energy state.

ラジカル窒化の条件としては例えば、窒素をプラズマ分解するためのラジカル窒化装置のマイクロ波パワーを1〜4kWとし、アルゴンガスと窒素ガスとの流量比をアルゴン:窒素=1:0.02〜0.1とし、温度を250〜600℃とし、圧力を0.1〜5Torrとすればよい。また、マイクロ波により発生した高密度プラズマ領域からシリコン酸化膜2a表面を充分に離せばよい。それにより、シリコン酸化膜2a表面にはプラズマダメージの原因の一つである窒素イオンの数を少なくし、窒素ラジカルの数を増やすことができ、欠陥の少ないシリコン窒化酸化膜2bを形成することができる。   As the conditions for radical nitriding, for example, the microwave power of a radical nitriding apparatus for plasma decomposition of nitrogen is set to 1 to 4 kW, and the flow ratio of argon gas to nitrogen gas is set to argon: nitrogen = 1: 0.02-0. 1, the temperature may be 250 to 600 ° C., and the pressure may be 0.1 to 5 Torr. The surface of the silicon oxide film 2a may be sufficiently separated from the high-density plasma region generated by the microwave. As a result, the number of nitrogen ions, which is one of the causes of plasma damage, can be reduced on the surface of the silicon oxide film 2a, the number of nitrogen radicals can be increased, and the silicon oxynitride film 2b with few defects can be formed. it can.

なお、この条件下にて発明者らが実際に形成したシリコン窒化酸化膜2bを、X線光電子分光分析法(XPS)にて解析したところ、1nm程度の膜厚となっていた。また、シリコン窒化酸化膜2b内の窒素含有量は、アルゴンガスと窒素ガスの流量比や、圧力、窒化時間等、ラジカル窒化の条件を適宜設定することにより、調節することができる。   When the silicon oxynitride film 2b actually formed by the inventors under these conditions was analyzed by X-ray photoelectron spectroscopy (XPS), the film thickness was about 1 nm. Further, the nitrogen content in the silicon oxynitride film 2b can be adjusted by appropriately setting radical nitriding conditions such as a flow ratio of argon gas and nitrogen gas, pressure, nitriding time, and the like.

次に、図5に示すように、シリコン窒化酸化膜2b上に浮遊ゲート電極5となる導電膜を形成する。浮遊ゲート電極5となる導電膜は、例えばモノシラン(SiH4)とホスフィン(PH3)を用いたCVD法により形成可能である。形成時の温度を例えば500〜550℃とすることにより、浮遊ゲート電極5は、リンが添加されたポリシリコン膜として形成される。なお、リンの添加濃度は、モノシラン(SiH4)とホスフィン(PH3)とのガス流量比の設定により制御可能である。 Next, as shown in FIG. 5, a conductive film to be the floating gate electrode 5 is formed on the silicon oxynitride film 2b. The conductive film to be the floating gate electrode 5 can be formed by, for example, a CVD method using monosilane (SiH 4 ) and phosphine (PH 3 ). By setting the temperature at the time of formation to, for example, 500 to 550 ° C., the floating gate electrode 5 is formed as a polysilicon film to which phosphorus is added. Note that the concentration of phosphorus added can be controlled by setting the gas flow ratio of monosilane (SiH 4 ) and phosphine (PH 3 ).

次に、CVD法により浮遊ゲート電極5となる導電膜上に、シリコン酸化膜6、シリコン窒化膜7およびシリコン酸化膜8を形成し、さらに、浮遊ゲート電極5となる導電膜と同様の製法により制御ゲート電極9となる導電膜を形成する。   Next, a silicon oxide film 6, a silicon nitride film 7 and a silicon oxide film 8 are formed on the conductive film to be the floating gate electrode 5 by the CVD method, and further, by the same manufacturing method as the conductive film to be the floating gate electrode 5. A conductive film to be the control gate electrode 9 is formed.

この後、フォトリソグラフィ及びエッチング技術を用いて、上記制御ゲート電極9となる導電膜までの積層構造をパターニングすることにより、図1における、トンネル絶縁膜2、浮遊ゲート電極5、電荷保持膜15および制御ゲート電極9の積層構造が形成される。   After that, by using photolithography and etching techniques, the laminated structure up to the conductive film that becomes the control gate electrode 9 is patterned, so that the tunnel insulating film 2, the floating gate electrode 5, the charge holding film 15 in FIG. A laminated structure of the control gate electrode 9 is formed.

本実施の形態に係る半導体不揮発性記憶装置及びその製造方法によれば、シリコン酸化膜2aの表面をラジカル窒化することにより、トンネル絶縁膜2を構成するシリコン窒化酸化膜2bを形成する。ラジカル窒化処理により形成された膜は、CVD法による窒化膜に比べて、膜中に欠陥が生じにくい。また、ラジカル窒化処理によれば、従来の単純なプラズマ窒化処理に比べてプラズマによるダメージが少ない。よって、トンネル絶縁膜2にリーク電流が生じにくい半導体不揮発性記憶装置を製造することができる。   According to the semiconductor nonvolatile memory device and the manufacturing method thereof according to the present embodiment, the surface of the silicon oxide film 2a is radical-nitrided to form the silicon oxynitride film 2b constituting the tunnel insulating film 2. A film formed by radical nitriding is less likely to cause defects in the film than a nitride film formed by CVD. Further, the radical nitriding treatment causes less plasma damage compared to the conventional simple plasma nitriding treatment. Therefore, it is possible to manufacture a semiconductor nonvolatile memory device in which a leak current hardly occurs in the tunnel insulating film 2.

図6は、本実施の形態に係る半導体不揮発性記憶装置のデータ保持特性を、従来の半導体不揮発性記憶装置のデータ保持特性と比較することにより、本実施の形態に係る半導体不揮発性記憶装置の効果を示した図である。   FIG. 6 shows a comparison of the data retention characteristics of the semiconductor nonvolatile memory device according to the present embodiment with the data retention characteristics of the conventional semiconductor nonvolatile memory device. It is the figure which showed the effect.

図6では、縦軸に不良品割合が10ppb(Parts Per Billion)となるまでのデータ保持時間をとり、横軸にトンネル絶縁膜2の膜厚をとっている。このうち、グラフGH1が従来の半導体不揮発性記憶装置のデータ保持特性であり、グラフGH2が本実施の形態に係る半導体不揮発性記憶装置のデータ保持特性である。   In FIG. 6, the vertical axis represents the data retention time until the defective ratio reaches 10 ppb (Parts Per Billion), and the horizontal axis represents the thickness of the tunnel insulating film 2. Among these, the graph GH1 is the data retention characteristic of the conventional semiconductor nonvolatile memory device, and the graph GH2 is the data retention characteristic of the semiconductor nonvolatile memory device according to the present embodiment.

グラフGH2の値から判るように、本実施の形態に係る半導体不揮発性記憶装置のデータ保持特性は、従来の特性に比べて一桁以上、データ保持時間が長い。これは、トンネル絶縁膜2にリーク電流が生じにくいことから、本実施の形態に係る半導体不揮発性記憶装置の電荷保持能力がきわめて高いことを意味している。   As can be seen from the value of the graph GH2, the data retention characteristic of the semiconductor nonvolatile memory device according to the present embodiment is one digit or more longer than the conventional characteristic. This means that since the leak current hardly occurs in the tunnel insulating film 2, the charge retention capability of the semiconductor nonvolatile memory device according to the present embodiment is extremely high.

<実施の形態2>
本実施の形態は、実施の形態1に係る半導体不揮発性記憶装置及びその製造方法の変形例であって、実施の形態1におけるシリコン酸化膜2aと半導体基板1の間に、トンネル絶縁膜2を構成する他のシリコン窒化酸化膜を形成するようにしたものである。
<Embodiment 2>
The present embodiment is a modification of the semiconductor nonvolatile memory device and the manufacturing method thereof according to the first embodiment. The tunnel insulating film 2 is provided between the silicon oxide film 2a and the semiconductor substrate 1 in the first embodiment. Another silicon oxynitride film to be formed is formed.

図7は、本実施の形態に係る半導体不揮発性記憶装置を示す図である。図7に示すように、この半導体不揮発性記憶装置は、図1の半導体不揮発性記憶装置に比べて、半導体基板1とシリコン酸化膜2aとの間に形成された他のシリコン窒化酸化膜2cを備えている点のみが異なる。そして、シリコン酸化膜2aおよびシリコン窒化酸化膜2b,2cで構成される積層膜が、半導体不揮発性記憶装置の1メモリセルのトンネル絶縁膜2として機能する。   FIG. 7 is a diagram showing a semiconductor nonvolatile memory device according to the present embodiment. As shown in FIG. 7, this semiconductor nonvolatile memory device has another silicon oxynitride film 2c formed between the semiconductor substrate 1 and the silicon oxide film 2a as compared with the semiconductor nonvolatile memory device of FIG. The only difference is the provision. The stacked film composed of the silicon oxide film 2a and the silicon oxynitride films 2b and 2c functions as the tunnel insulating film 2 of one memory cell of the semiconductor nonvolatile memory device.

このように、トンネル絶縁膜2が、シリコン酸化膜2a、及び、シリコン窒化酸化膜2b,2cにより構成されるので、トンネル絶縁膜2を更に強固にすることができ、トンネル絶縁膜2にリーク電流がより生じにくい半導体不揮発性記憶装置が得られる。また、半導体基板1とシリコン酸化膜2aとの間にシリコン窒化酸化膜2cが形成されているので、トンネル絶縁膜2と半導体基板1との界面の欠陥が生じにくく、トンネル絶縁膜2と半導体基板1との界面の界面準位が増大しにくい半導体不揮発性記憶装置が得られる。   Thus, since the tunnel insulating film 2 is composed of the silicon oxide film 2a and the silicon oxynitride films 2b and 2c, the tunnel insulating film 2 can be further strengthened, and a leakage current is generated in the tunnel insulating film 2. Thus, a semiconductor non-volatile memory device that is less likely to generate is obtained. Further, since the silicon oxynitride film 2c is formed between the semiconductor substrate 1 and the silicon oxide film 2a, defects at the interface between the tunnel insulating film 2 and the semiconductor substrate 1 are unlikely to occur, and the tunnel insulating film 2 and the semiconductor substrate Thus, a semiconductor nonvolatile memory device in which the interface state at the interface with 1 is hardly increased can be obtained.

その他の点については、実施の形態1に係る半導体不揮発性記憶装置と同様のため、説明を省略する。   Since other points are the same as those of the semiconductor nonvolatile memory device according to the first embodiment, description thereof is omitted.

次に、本実施の形態に係る半導体不揮発性記憶装置の製造方法について、図8〜図10を用いて説明する。   Next, a method for manufacturing the semiconductor nonvolatile memory device according to the present embodiment will be described with reference to FIGS.

まず、実施の形態1の図2および図3と同様にして、半導体基板1の表面に熱酸化法等により素子分離領域3を形成し、その後、熱酸化法等によりおよびシリコン酸化膜2aを半導体基板1上に形成する。   First, as in FIGS. 2 and 3 of the first embodiment, the element isolation region 3 is formed on the surface of the semiconductor substrate 1 by a thermal oxidation method or the like, and then the silicon oxide film 2a is formed by a thermal oxidation method or the like on the semiconductor It is formed on the substrate 1.

次に、図8に示すように、シリコン酸化膜2aと半導体基板1との間に、シリコン窒化酸化膜2cを形成する。このシリコン窒化酸化膜2cは、一酸化窒素(NO)、亜酸化窒素(N2O)またはアンモニア(NH3)の雰囲気中でアニール処理(処理温度は、例えば800〜1150℃)を行うことにより形成する。 Next, as shown in FIG. 8, a silicon oxynitride film 2 c is formed between the silicon oxide film 2 a and the semiconductor substrate 1. The silicon oxynitride film 2c is annealed (treatment temperature is, for example, 800 to 1150 ° C.) in an atmosphere of nitric oxide (NO), nitrous oxide (N 2 O), or ammonia (NH 3 ). Form.

次に、図9に示すように、シリコン酸化膜2aの表面をラジカル窒化することにより、シリコン窒化酸化膜2bをシリコン酸化膜2a上に形成する。ラジカル窒化の条件は、実施の形態1の場合と同様とすればよい。   Next, as shown in FIG. 9, a silicon oxynitride film 2b is formed on the silicon oxide film 2a by radical nitriding the surface of the silicon oxide film 2a. The radical nitriding conditions may be the same as those in the first embodiment.

次に、図10に示すように、シリコン窒化酸化膜2b上に浮遊ゲート電極5となる導電膜を、実施の形態1の場合と同様に形成する。   Next, as shown in FIG. 10, a conductive film to be the floating gate electrode 5 is formed on the silicon oxynitride film 2b in the same manner as in the first embodiment.

次に、CVD法により浮遊ゲート電極5となる導電膜上に、シリコン酸化膜6、シリコン窒化膜7およびシリコン酸化膜8を形成し、さらに、浮遊ゲート電極5となる導電膜と同様の製法により制御ゲート電極9となる導電膜を形成する。   Next, a silicon oxide film 6, a silicon nitride film 7 and a silicon oxide film 8 are formed on the conductive film to be the floating gate electrode 5 by the CVD method, and further, by the same manufacturing method as the conductive film to be the floating gate electrode 5. A conductive film to be the control gate electrode 9 is formed.

この後、フォトリソグラフィ及びエッチング技術を用いて、上記制御ゲート電極9となる導電膜までの積層構造をパターニングすることにより、図7における、トンネル絶縁膜2、浮遊ゲート電極5、電荷保持膜15および制御ゲート電極9の積層構造が形成される。   After that, by using photolithography and etching techniques, the laminated structure up to the conductive film that becomes the control gate electrode 9 is patterned, so that the tunnel insulating film 2, the floating gate electrode 5, the charge holding film 15 in FIG. A laminated structure of the control gate electrode 9 is formed.

本実施の形態に係る半導体不揮発性記憶装置においても、シリコン窒化酸化膜2bは、シリコン酸化膜2aの表面をラジカル窒化することにより形成される。よって、トンネル絶縁膜2にリーク電流がより生じにくい半導体不揮発性記憶装置が得られる。   Also in the semiconductor nonvolatile memory device according to the present embodiment, silicon oxynitride film 2b is formed by radical nitriding the surface of silicon oxide film 2a. Therefore, a semiconductor nonvolatile memory device in which a leak current is less likely to be generated in the tunnel insulating film 2 can be obtained.

また、本実施の形態に係る半導体不揮発性記憶装置の製造方法は、一酸化窒素、亜酸化窒素またはアンモニア雰囲気中でアニール処理を行い、シリコン酸化膜2aと半導体基板1との間に、トンネル絶縁膜2を構成するシリコン窒化酸化膜2cを形成する工程をさらに備える。よって、さらにトンネル絶縁膜2を強固にすることができ、リーク電流がより生じにくい半導体不揮発性記憶装置を製造することができる。また、トンネル絶縁膜2と半導体基板1との界面の欠陥が生じにくく、トンネル絶縁膜2と半導体基板1との界面の界面準位が増大しにくい半導体不揮発性記憶装置を製造することができる。   Further, in the method for manufacturing the semiconductor nonvolatile memory device according to the present embodiment, the tunnel insulation is performed between the silicon oxide film 2a and the semiconductor substrate 1 by performing an annealing process in a nitrogen monoxide, nitrous oxide or ammonia atmosphere. A step of forming a silicon oxynitride film 2c constituting the film 2 is further provided. Therefore, the tunnel insulating film 2 can be further strengthened, and a semiconductor nonvolatile memory device that is less prone to leak current can be manufactured. Further, it is possible to manufacture a semiconductor nonvolatile memory device in which defects at the interface between the tunnel insulating film 2 and the semiconductor substrate 1 are unlikely to occur and the interface state at the interface between the tunnel insulating film 2 and the semiconductor substrate 1 is unlikely to increase.

図11は、本実施の形態に係る半導体不揮発性記憶装置のデータ消去速度の低下によるデータ消去動作不良率を、シリコン窒化酸化膜2cを有しない、シリコン酸化膜2a及びシリコン窒化膜2bの二層からなるトンネル絶縁膜2を備える半導体不揮発性記憶装置のデータ消去動作不良率と比較することにより、本実施の形態に係る半導体不揮発性記憶装置の効果を示す図である。   FIG. 11 shows the data erasure operation failure rate due to a decrease in the data erasing speed of the semiconductor nonvolatile memory device according to the present embodiment. The silicon oxynitride film 2c does not have the silicon oxide film 2a and the silicon nitride film 2b. It is a figure which shows the effect of the semiconductor non-volatile memory device which concerns on this Embodiment by comparing with the data erasing operation failure rate of a semiconductor non-volatile memory device provided with the tunnel insulating film 2 which consists of these.

図11では、縦軸にデータ消去動作不良の累積の割合を採り、横軸にデータ書き込み動作及びデータ消去動作の繰り返し回数を採っている。このうちグラフGH3が、シリコン窒化酸化膜2cを有しない、シリコン酸化膜2a及びシリコン窒化膜2bの二層からなるトンネル絶縁膜2を備える半導体不揮発性記憶装置のデータ消去動作不良率であり、一方、グラフGH4が、本実施の形態に係る半導体不揮発性記憶装置のデータ消去動作不良率である。   In FIG. 11, the vertical axis represents the cumulative rate of data erasure operation failure, and the horizontal axis represents the number of repetitions of the data write operation and data erasure operation. Of these graphs, GH3 is the data erasure operation failure rate of the semiconductor nonvolatile memory device that does not have the silicon oxynitride film 2c and includes the tunnel insulating film 2 composed of two layers of the silicon oxide film 2a and the silicon nitride film 2b. Graph GH4 shows the data erasure operation failure rate of the semiconductor nonvolatile memory device according to the present embodiment.

グラフGH4の値から分かるように、本実施の形態に係る半導体不揮発性記憶装置のデータ消去動作不良率は、シリコン酸化膜2a及びシリコン窒化膜2bの二層からなるトンネル絶縁膜2を備える半導体不揮発性記憶装置のデータ消去動作不良率よりも低い。これは、データ書き込み動作とデータ消去動作の繰り返しによる、トンネル絶縁膜2と半導体基板1との間の界面準位の増大が起こりにくいため、本実施の形態に係る半導体不揮発性記憶装置のデータ消去速度の劣化が極めて少ないことを意味している。   As can be seen from the value of the graph GH4, the data erasure operation failure rate of the semiconductor nonvolatile memory device according to the present embodiment is the semiconductor nonvolatile memory including the tunnel insulating film 2 composed of the silicon oxide film 2a and the silicon nitride film 2b. Lower than the data erasure operation failure rate of the volatile storage device. This is because the interface state between the tunnel insulating film 2 and the semiconductor substrate 1 is unlikely to increase due to the repetition of the data writing operation and the data erasing operation, so that the data erasing of the semiconductor nonvolatile memory device according to the present embodiment is performed. This means that there is very little speed degradation.

本実施の形態に係る半導体不揮発性記憶装置のデータ保持特性についても、本願発明者らは、図6の場合と同様、良好な結果を得ることができた。   Regarding the data retention characteristics of the semiconductor nonvolatile memory device according to the present embodiment, the inventors of the present application were able to obtain good results as in the case of FIG.

実施の形態1に係る半導体不揮発性記憶装置を示す図である。1 is a diagram showing a semiconductor nonvolatile memory device according to a first embodiment. 実施の形態1に係る半導体不揮発性記憶装置の製造方法を示す図である。6 is a diagram showing a method for manufacturing the semiconductor nonvolatile memory device according to the first embodiment. FIG. 実施の形態1に係る半導体不揮発性記憶装置の製造方法を示す図である。6 is a diagram showing a method for manufacturing the semiconductor nonvolatile memory device according to the first embodiment. FIG. 実施の形態1に係る半導体不揮発性記憶装置の製造方法を示す図である。6 is a diagram showing a method for manufacturing the semiconductor nonvolatile memory device according to the first embodiment. FIG. 実施の形態1に係る半導体不揮発性記憶装置の製造方法を示す図である。6 is a diagram showing a method for manufacturing the semiconductor nonvolatile memory device according to the first embodiment. FIG. 実施の形態1に係る半導体不揮発性記憶装置の効果を示す図である。It is a figure which shows the effect of the semiconductor non-volatile memory device which concerns on Embodiment 1. FIG. 実施の形態2に係る半導体不揮発性記憶装置を示す図である。4 is a diagram showing a semiconductor nonvolatile memory device according to a second embodiment. FIG. 実施の形態2に係る半導体不揮発性記憶装置の製造方法を示す図である。10 is a diagram showing a method for manufacturing the semiconductor nonvolatile memory device according to the second embodiment. FIG. 実施の形態2に係る半導体不揮発性記憶装置の製造方法を示す図である。10 is a diagram showing a method for manufacturing the semiconductor nonvolatile memory device according to the second embodiment. FIG. 実施の形態2に係る半導体不揮発性記憶装置の製造方法を示す図である。10 is a diagram showing a method for manufacturing the semiconductor nonvolatile memory device according to the second embodiment. FIG. 実施の形態2に係る半導体不揮発性記憶装置の効果を示す図である。It is a figure which shows the effect of the semiconductor non-volatile memory device concerning Embodiment 2. FIG.

符号の説明Explanation of symbols

1 半導体基板、2 トンネル絶縁膜、2a シリコン酸化膜、2b,2c シリコン窒化酸化膜。
1 Semiconductor substrate, 2 tunnel insulating film, 2a silicon oxide film, 2b, 2c silicon oxynitride film.

Claims (5)

トンネル絶縁膜を含む半導体不揮発性記憶装置の製造方法であって、
(a)前記トンネル絶縁膜を構成するシリコン酸化膜を半導体基板上に形成する工程と、
(b)前記トンネル絶縁膜を構成する第1シリコン窒化酸化膜を前記シリコン酸化膜上に形成する工程と
を備え、
前記工程(b)において、前記シリコン酸化膜の表面をラジカル窒化することにより、前記第1シリコン窒化酸化膜を形成する
半導体不揮発性記憶装置の製造方法。
A method for manufacturing a semiconductor nonvolatile memory device including a tunnel insulating film,
(A) forming a silicon oxide film constituting the tunnel insulating film on a semiconductor substrate;
(B) forming a first silicon oxynitride film constituting the tunnel insulating film on the silicon oxide film,
A method of manufacturing a semiconductor nonvolatile memory device, wherein in the step (b), the first silicon oxynitride film is formed by radical nitriding the surface of the silicon oxide film.
請求項1に記載の半導体不揮発性記憶装置の製造方法であって、
(c)前記工程(a)の後であって前記工程(b)の前に、一酸化窒素、亜酸化窒素またはアンモニア雰囲気中でアニール処理を行い、前記シリコン酸化膜と前記半導体基板との間に、前記トンネル絶縁膜を構成する第2シリコン窒化酸化膜を形成する工程
をさらに備える半導体不揮発性記憶装置の製造方法。
A method for manufacturing a semiconductor nonvolatile memory device according to claim 1, comprising:
(C) After the step (a) and before the step (b), an annealing process is performed in an atmosphere of nitrogen monoxide, nitrous oxide, or ammonia, and between the silicon oxide film and the semiconductor substrate. A method for manufacturing a semiconductor nonvolatile memory device, further comprising the step of forming a second silicon oxynitride film constituting the tunnel insulating film.
半導体基板と、
前記半導体基板上に形成されたシリコン酸化膜と、
前記シリコン酸化膜上に形成されたシリコン窒化酸化膜と
を備え、
前記シリコン酸化膜および前記シリコン窒化酸化膜は、トンネル絶縁膜を構成し、
前記シリコン窒化酸化膜は、前記シリコン酸化膜の表面をラジカル窒化することにより形成された
半導体不揮発性記憶装置。
A semiconductor substrate;
A silicon oxide film formed on the semiconductor substrate;
A silicon oxynitride film formed on the silicon oxide film,
The silicon oxide film and the silicon oxynitride film constitute a tunnel insulating film,
The silicon nitride oxide film is a semiconductor nonvolatile memory device formed by radical nitriding the surface of the silicon oxide film.
半導体基板と、
シリコン酸化膜と、
前記シリコン酸化膜上に形成された第1シリコン窒化酸化膜と、
前記半導体基板と前記シリコン酸化膜との間に形成された第2シリコン窒化酸化膜と
を備え、
前記シリコン酸化膜、並びに、前記第1及び第2シリコン窒化酸化膜は、トンネル絶縁膜を構成する
半導体不揮発性記憶装置。
A semiconductor substrate;
Silicon oxide film,
A first silicon oxynitride film formed on the silicon oxide film;
A second silicon oxynitride film formed between the semiconductor substrate and the silicon oxide film;
The silicon oxide film, and the first and second silicon oxynitride films are semiconductor nonvolatile memory devices constituting a tunnel insulating film.
請求項4に記載の半導体不揮発性記憶装置であって、
前記第1シリコン窒化酸化膜は、前記シリコン酸化膜の表面をラジカル窒化することにより形成された
半導体不揮発性記憶装置。
The semiconductor nonvolatile memory device according to claim 4,
The first silicon nitride oxide film is a semiconductor nonvolatile memory device formed by radical nitriding the surface of the silicon oxide film.
JP2005354507A 2005-01-24 2005-12-08 Semiconductor nonvolatile memory and its manufacturing method Pending JP2006229195A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2005354507A JP2006229195A (en) 2005-01-24 2005-12-08 Semiconductor nonvolatile memory and its manufacturing method
US11/335,504 US20060166440A1 (en) 2005-01-24 2006-01-20 Semiconductor nonvolatile memory device, and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005015189 2005-01-24
JP2005354507A JP2006229195A (en) 2005-01-24 2005-12-08 Semiconductor nonvolatile memory and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2006229195A true JP2006229195A (en) 2006-08-31

Family

ID=36697382

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005354507A Pending JP2006229195A (en) 2005-01-24 2005-12-08 Semiconductor nonvolatile memory and its manufacturing method

Country Status (2)

Country Link
US (1) US20060166440A1 (en)
JP (1) JP2006229195A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008053266A (en) * 2006-08-22 2008-03-06 Sony Corp Nonvolatile semiconductor memory device and its manufacturing method
US7400009B2 (en) 2001-06-28 2008-07-15 Samsung Electronics Co., Ltd. Floating trap non-volatile semiconductor memory devices including high dielectric constant blocking insulating layers
US7473959B2 (en) 2001-06-28 2009-01-06 Samsung Electronics Co., Ltd. Non-volatile semiconductor memory devices and methods of fabricating the same
KR100905276B1 (en) 2006-09-26 2009-06-30 삼성전자주식회사 Flash memory device including multylayer tunnel insulator and method of fabricating the same
US8330207B2 (en) 2006-09-26 2012-12-11 Samsung Electronics Co., Ltd. Flash memory device including multilayer tunnel insulator and method of fabricating the same
US8525275B2 (en) 2007-07-16 2013-09-03 Samsung Electronics Co., Ltd. Methods of forming non-volatile memory devices
US9761314B2 (en) 2001-06-28 2017-09-12 Samsung Electronics Co., Ltd. Non-volatile memory devices and methods of operating the same

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8008214B2 (en) * 2005-12-16 2011-08-30 Samsung Electronics Co., Ltd. Method of forming an insulation structure and method of manufacturing a semiconductor device using the same
KR100941863B1 (en) * 2008-01-02 2010-02-11 주식회사 하이닉스반도체 Tunnel insulating film of flash memory device and method of manufacturing thereof
KR100933840B1 (en) * 2008-01-17 2009-12-24 주식회사 하이닉스반도체 Manufacturing Method of Flash Memory Device
JP5356005B2 (en) * 2008-12-10 2013-12-04 株式会社東芝 Nonvolatile semiconductor memory device and manufacturing method thereof
WO2014031153A1 (en) * 2012-08-23 2014-02-27 Sixpoint Materials, Inc. Composite substrate of gallium nitride and metal oxide
TWI803348B (en) * 2022-02-24 2023-05-21 南亞科技股份有限公司 Method for fabricating semiconductor device having a shielding line for signal crosstalk suppression

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002368122A (en) * 2001-06-12 2002-12-20 Nec Corp Semiconductor device and producing method therefor
JP4358504B2 (en) * 2002-12-12 2009-11-04 忠弘 大見 Method for manufacturing nonvolatile semiconductor memory device
KR100602322B1 (en) * 2004-04-20 2006-07-14 에스티마이크로일렉트로닉스 엔.브이. A method for manufacturing a flash memory device and a flash memory device manufactured by the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7400009B2 (en) 2001-06-28 2008-07-15 Samsung Electronics Co., Ltd. Floating trap non-volatile semiconductor memory devices including high dielectric constant blocking insulating layers
US7473959B2 (en) 2001-06-28 2009-01-06 Samsung Electronics Co., Ltd. Non-volatile semiconductor memory devices and methods of fabricating the same
US9761314B2 (en) 2001-06-28 2017-09-12 Samsung Electronics Co., Ltd. Non-volatile memory devices and methods of operating the same
JP2008053266A (en) * 2006-08-22 2008-03-06 Sony Corp Nonvolatile semiconductor memory device and its manufacturing method
KR100905276B1 (en) 2006-09-26 2009-06-30 삼성전자주식회사 Flash memory device including multylayer tunnel insulator and method of fabricating the same
US8330207B2 (en) 2006-09-26 2012-12-11 Samsung Electronics Co., Ltd. Flash memory device including multilayer tunnel insulator and method of fabricating the same
US8525275B2 (en) 2007-07-16 2013-09-03 Samsung Electronics Co., Ltd. Methods of forming non-volatile memory devices

Also Published As

Publication number Publication date
US20060166440A1 (en) 2006-07-27

Similar Documents

Publication Publication Date Title
JP2006229195A (en) Semiconductor nonvolatile memory and its manufacturing method
US7985650B2 (en) Nonvolatile semiconductor memory device and method of manufacturing the same
US8524589B2 (en) Plasma treatment of silicon nitride and silicon oxynitride
US7371669B2 (en) Method of forming a gate of a semiconductor device
KR100493022B1 (en) Method for fabricating nonvolatile memory device having a structure of silicon-oxide-nitride-oxide-silicon
JP2010021204A (en) Semiconductor device and manufacturing method thereof
US8008152B2 (en) Method of manufacturing semiconductor device
JP2006203120A (en) Method for manufacturing semiconductor apparatus
JP2018157035A (en) Semiconductor device and manufacturing method of the same
US7160818B2 (en) Semiconductor device and method for fabricating same
US8163626B2 (en) Enhancing NAND flash floating gate performance
US7795123B2 (en) Method of forming gate electrode
KR100665396B1 (en) Method of manufacturing a flash memory device
JP6790808B2 (en) Semiconductor devices and their manufacturing methods
JP2009253195A (en) Method for manufacturing semiconductor device and the semiconductor device
JP2006054382A (en) Metallic silicate film, manufacturing method thereof, semiconductor device, and manufacturing method thereof
JP2000150803A (en) Manufacture of semiconductor device
TW492146B (en) Manufacturing method of semiconductor device with gate stack dielectric layer
JPH10242307A (en) Nonvolatile semiconductor memory and manufacture thereof
JPH10233504A (en) Semiconductor device and its manufacture
JP2009277737A (en) Nonvolatile semiconductor memory device, and method of manufacturing the same
JPH08153813A (en) Manufacture of nonvolatile memory transistor
KR20090035338A (en) Method for fabricating dual gate in semiconductor device
KR20060097188A (en) Method of manufacturing a flash memory cell
KR20030040733A (en) Method for forming dielectric layer in semiconductor device