TWI803348B - Method for fabricating semiconductor device having a shielding line for signal crosstalk suppression - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided. The method includes disposing a mandrel layer on a dielectric layer and patterning the mandrel layer to form a first mandrel and a second mandrel spaced apart from the first mandrel. The minimum distance between the first mandrel and the second mandrel is equal to or less than about 90 nm. The method also includes etching the dielectric layer by using the first spacer, the second spacer, the third spacer, and the fourth spacer as etching masks to form a first dielectric element, a second dielectric element, a third dielectric element, and a fourth dielectric element. The method also includes forming a first shielding line between the second dielectric element and the third dielectric element.

Description

Manufacturing method of semiconductor device with shielded lines to suppress signal crosstalk

This application claims priority to US Patent Application Nos. 17/679,302 and 17/679,482 (ie, the priority date is "February 24, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device. In particular, it relates to a semiconductor device with shielded lines to suppress signal crosstalk.

A typical memory device, such as a dynamic random access memory (DRAM) device, includes signal lines, such as word lines, and bit lines crossing the word lines.

As DRAM devices shrink, the size and/or pitch of signal lines becomes smaller and smaller, and capacitive coupling and/or inductive magnetic coupling become more significant. Electromagnetic noise or crosstalk between signal lines may also become severe, thereby degrading device performance.

The above "prior art" description is only to provide background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" shall not form part of this case.

One aspect of the present disclosure provides a semiconductor device. The semiconductor element includes: a base with a surface; a first signal line disposed on the surface of the base; and a second signal line disposed on the surface of the base and spaced from the first signal line open. The semiconductor device also includes a first shielding line between the first signal line and the second signal line. A minimum distance between the first signal line and the second signal line is equal to or less than about 90 nanometers (nm).

Another aspect of the present disclosure provides a semiconductor device. The semiconductor element includes: a base with a surface; a first signal line disposed on the surface of the base; and a second signal line disposed on the surface of the base and spaced from the first signal line open. The semiconductor device also includes a first shielding line between the first signal line and the second signal line. A minimum distance between the first signal line and the first mask line is equal to or less than about 40 nm.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device. The preparation method includes: disposing a mandrel layer on a dielectric layer, and patterning the mandrel layer to form a first mandrel and a second mandrel spaced apart from the first mandrel. A minimum distance between the first mandrel and the second mandrel is equal to or less than about 90 nanometers. The manufacturing method also includes: forming a first spacer adjacent to a first side of the first mandrel, a second spacer adjacent to a second side of the first mandrel, and forming a second spacer adjacent to the first mandrel. A third spacer adjacent to a first side of the two mandrels, and a fourth spacer adjacent to a second side of the second mandrel. The preparation method further includes: using the first spacer, the second spacer, the third spacer and the fourth spacer as an etching mask to etch the dielectric layer to form a first dielectric element , a second dielectric element, a third dielectric element and a fourth dielectric element. The manufacturing method further includes: forming a first mask line between the second dielectric element and the third dielectric element.

By forming a dummy line between two signal lines (such as an aggressive (aggressor) line and a static (victim) line) and connecting the dummy line to power or ground, it is possible to reduce or prevent interference between signal lines. Electromagnetic noise or crosstalk.

In addition, the manufacturing technique of dummy lines and signal lines may include a pitch doubling process, such as a self-aligned pitch doubling technique or a self-aligned double patterning technique. The disclosed process overcomes scaling-related lithography problems and creates denser memory arrays than conventional lithography techniques. Therefore, the performance of the element can be improved.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended patent claims.

Embodiments, or examples, of the present disclosure illustrated in the drawings will now be described in specific language. It should be understood that no limitation of the scope of the present disclosure is intended herein. Any changes or modifications to the described embodiments, and any further applications of the principles described herein, are considered to be within the ordinary skill of the art to which this disclosure pertains. Reference numbers may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another, even if they share the same reference number.

It will be understood that although the terms first, second, third etc. may be used to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the singular forms "a", "an" and "the" also include plural forms unless the context clearly dictates otherwise. It should be understood that the words "comprises" and "comprises", when used in this specification, indicate the presence of the stated features, integers, steps, operations, elements or components, but do not exclude the presence or addition of one or more other A feature, integer, step, operation, element, component, or group thereof.

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device 1 according to some embodiments of the present disclosure. In some embodiments, the semiconductor device 1 may include a circuit, such as a memory cell. In some embodiments, the memory cell may include a dynamic random access memory cell (DRAM cell).

Furthermore, the semiconductor element 1 may be or comprise a part of an integrated circuit (IC) die comprising various passive and active microelectronic components such as resistors, capacitors, inductors, diodes, , p-type field effect transistors (pFETs), n-type field effect transistors (nFETs), metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bicarrier transistors ( BJT), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, Fin Field Effect Transistors (FinFETs), other suitable IC components or combinations thereof.

As shown in FIG. 1, in some embodiments, a semiconductor device 1 may include a substrate 10, a conductive element 11, signal lines 12, 15, dielectric elements 13, 13', 16, 16', and shielding lines 14a, 14b. , and 14c.

In some embodiments, substrate 10 may include, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP) or other IV-IV, III-V or II-VI semiconductor materials. In some other embodiments, the substrate 10 may include a semiconductor substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.

Depending on the stage of IC fabrication, substrate 10 may include layers of various materials (e.g., dielectric layers, semiconductor layers, and/or conductive layers) configured to form an IC feature (e.g., doped regions, isolation features, gate features, source or drain features, interconnect features, other features, or combinations thereof).

For example, the conductive element 11 may be disposed in the substrate 10 . The fabrication technology of the conductive element 11 may come from a doped region of a bulk semiconductor substrate, or from an epitaxial layer. The conductive element 11 can be connected to, for example, a terminal of a MOSFET (such as a gate, source or drain), a terminal of a BJT (such as an emitter, a collector or a base), or other IC features in the semiconductor component 1 (such as DRAM cells) are electrically connected.

The conductive element 11 may be at least partially exposed from the substrate 10 . The signal line 12 and the signal line 15 can be electrically connected to one or more conductive elements 11 to control the operation of the semiconductor element 1 (such as a DRAM cell).

In some embodiments, the operation of the semiconductor element 1 may include a state change from a binary one to a binary zero, or vice versa. For example, a state change may involve the accumulation and/or storage of a charge, or the release of a stored charge.

In some embodiments, the conductive element 11 may include, for example, polysilicon (poly-Si), metals (such as aluminum (Al), magnesium (Mg), tungsten (W), lanthanum (La), etc.), or metal alloys. In some embodiments, the conductive element 11 may include, for example, a titanium-based material (such as titanium nitride (TiN) or titanium aluminum nitride (TiAlN)), a tantalum-based material (such as tantalum nitride (TaN), tantalum nitride Aluminum (TaAlN), or tantalum carbide (Ta2C)), or silicide (such as PtSi, TiSi2, CoSi, NiSi, MoSi2, TaSi, WSi2, etc.).

Although two conductive elements are illustrated, it is understood that the semiconductor element 1 may comprise any suitable number of conductive elements.

The signal line 12 can be disposed on the surface 101 of the substrate 10 . The signal line 12 can be electrically connected to the conductive element 11 . The width “w2” of the signal line 12 is measured in a direction substantially parallel to the surface 101 of the substrate 10 . Width w2 may be equal to or less than about 20 nanometers (nm). In some embodiments, the width w2 may be greater than the width “w1” of the conductive element 11 measured in a direction substantially parallel to the surface 101 of the substrate 10 . However, in some other embodiments, the width w2 may be equal to or smaller than the width w1.

The signal line 15 can be disposed on the surface 101 of the substrate 10 and spaced apart from the signal line 12 . The signal line 15 can be electrically connected to the conductive elements in the substrate 10 . The signal line 15 may have a width substantially equal to the width w2 of the signal line 12 .

The signal line 12 and the signal line 15 may respectively become a part of a word line and a bit line of the semiconductor device 1 . The signal line 12 and the signal line 15 may respectively include, for example, polysilicon (poly-Si), metal (such as aluminum (Al), magnesium (Mg), tungsten (W), lanthanum (La), etc.), or a metal alloy.

Although two signal lines are illustrated, it is understood that the semiconductor device 1 may include any suitable number of signal lines.

The signal line 12 may have a side 121 and a side 122 opposite to the side 121 . The side 121 and the side 122 can each be substantially perpendicular to the surface 101 of the substrate 10 . The signal line 15 can have a side 151 and a side 152 opposite to the side 151 . The side surfaces 151 and 152 may each be substantially perpendicular to the surface 101 of the substrate 10 .

In some embodiments, the minimum distance “w5” between the signal line 12 and the signal line 15 is measured in a direction substantially parallel to the surface 101 of the substrate 10 . For example, the minimum distance w5 can be measured between the side 122 of the signal line 12 and the side 151 of the signal line 15 . The minimum distance w5 may be equal to or less than about 90 nanometers.

The dielectric element 13 can contact, cover, seal or encapsulate the side surface 121 of the signal line 12 . The dielectric element 13 ′ can contact, cover, seal or encapsulate the side surface 122 of the signal line 12 . The dielectric element 16 may contact, cover, seal or encapsulate the side surface 151 of the signal line 15 . Dielectric element 16 ′ may contact, cover, seal or encapsulate side surface 152 of signal line 15 .

In some embodiments, each of the dielectric element 13 , the dielectric element 13 ′, the dielectric element 16 and the dielectric element 16 ′ can be a spacer. In some embodiments, dielectric element 13, dielectric element 13', dielectric element 16, and dielectric element 16' may each include, for example, nitride, oxide, oxynitride amorphous silicon, polysilicon Or another material suitable for the desired patterning operation as in Fig. 4H. Exemplary gap materials may include, but are not limited to, hafnium silicate (HfSiOx), hafnium oxide (HfO2), zirconium silicate (ZrSiOx), zirconium oxide (ZrO2), silicon nitride (Si3N4), silicon oxynitride (SiON) Or silicon oxide (SiO2), tetrachlorosilicate (TEOS), carbon-doped silicon, etc.

In some embodiments, the dielectric element 13 , the dielectric element 13 ′, the dielectric element 16 , and the dielectric element 16 ′ can each be a single-layer structure.

Width “w3” of each of dielectric element 13 , dielectric element 13 ′, dielectric element 16 , and dielectric element 16 ′ is measured in a direction substantially parallel to surface 101 of substrate 10 . Width w3 may be equal to or less than about 40 nm. For example, width w3 may be between about 10 nm and about 40 nm. In some embodiments, dielectric element 13, dielectric element 13', dielectric element 16, and dielectric element 16' may have the same width.

The mask lines 14 a , 14 b and 14 c may be respectively disposed on the surface 101 of the substrate 10 . The mask wire 14 a , the mask wire 14 b , and the mask wire 14 c may be part of the mask structure 14 . The mask line 14a, the mask line 14b, and the mask line 14c may be electrically connected to each other. The shield wire 14a, the shield wire 14b, and the shield wire 14c may be electrically connected to a power source or a ground.

The shielding line 14 a and the shielding line 14 b can be disposed on opposite sides of the signal line 12 . The signal line 12 can be between the shielding line 14a and the shielding line 14b. The shielding line 14b can be between the signal line 12 and the signal line 15 . The shielding line 14b and the shielding line 14c can be disposed on opposite sides of the signal line 15 . The signal line 15 can be between the shielding line 14b and the shielding line 14c.

The mask line 14a, the mask line 14b, and the mask line 14c may be called dummy lines, respectively.

The mask lines 14 a , 14 b , and 14 c may not be used to form conductive interconnections with the conductive elements 11 . In contrast, the signal line 12 and the signal line 15 can be disposed on the conductive element 11 and can be used to form a conductive interconnection with the conductive element 11 .

Shield line 14a, shield line 14b, and shield line 14c may be configured to provide signal line 12 and signal line 15 with an electromagnetic interference (EMI) shield. For example, shield line 14a, shield line 14b, and shield line 14c may be configured to provide an EMI shield to prevent signal line 12 from being interfered by signal line 15, and vice versa.

The mask lines 14a, 14b, and 14c may each include, for example, polysilicon (poly-Si), metals (such as aluminum (Al), magnesium (Mg), tungsten (W), lanthanum (La), etc. ), or metal alloys. The mask wire 14a, the mask wire 14b, and the mask wire 14c may have the same material. The mask line 14 a , the mask line 14 b and the mask line 14 c may have the same material as the signal line 12 and the signal line 15 . In some embodiments, the mask line 14 a , the mask line 14 b and the mask line 14 c may be formed in the same operation as the signal line 12 and the signal line 15 .

The width w3 of the dielectric element 13 may be the minimum distance between the shield line 14 a and the signal line 12 . The width w3 of the dielectric element 13 ′ may be the minimum distance between the shield line 14 b and the signal line 12 . The width w3 of the dielectric element 16 may be the minimum distance between the shield line 14 b and the signal line 15 . The width w3 of the dielectric element 16 ′ may be the minimum distance between the shield line 14 c and the signal line 15 .

The width “w4” of each of mask line 14a , mask line 14b , and mask line 14c is measured in a direction substantially parallel to surface 101 of substrate 10 . Width w4 may be equal to or less than about 70 nm. For example, width w4 may be between about 10 nm and 70 nm. In some embodiments, width w4 may be the minimum width of each of mask line 14a, mask line 14b, and mask line 14c. In some embodiments, the width w4 may be defined by a pitch multiplication process, such as a self-aligned pitch doubling technique or a self-aligned double patterning technique. In some embodiments, width w4 may be greater than width w3.

In some embodiments, the minimum distance w5 between the signal line 12 and the signal line 15 may be the sum of the width w4 of the mask line 14 b, the width w3 of the dielectric element 13 ′, and the width w3 of the dielectric element 16 .

As noted, width w3 may be between about 10 nm and about 40 nm, and width w4 may be between about 10 nm and about 70 nm. However, the minimum distance w5 between the signal line 12 and the signal line 15 remains equal to or smaller than about 90 nm.

As DRAM components (such as the semiconductor device 1 ) shrink, the size and/or pitch of the signal lines become smaller and smaller, and the capacitive coupling and/or inductive magnetic coupling become significant. Electromagnetic noise or crosstalk between signal lines can become severe, thereby degrading device performance.

According to some embodiments of the present disclosure, by forming a dummy line between two signal lines (such as an aggressive (aggressor) line and a static (victim) line) and connecting the dummy line to power or ground, it is possible to Reduce or prevent electromagnetic noise or crosstalk between signal lines.

In addition, the manufacturing technology of dummy lines and signal lines includes a pitch doubling process, such as a self-aligned pitch doubling technology or a self-aligned double patterning technology. The disclosed process overcomes scaling-related lithography problems and creates denser memory arrays than conventional lithography techniques. Therefore, the performance of the element can be improved.

FIG. 1B is a schematic top view illustrating a semiconductor device according to some embodiments of the present disclosure. In some embodiments, the cross-sectional view shown in FIG. 1A (or the cross-sectional view shown in FIG. 2 , or the cross-sectional view shown in FIG. 3 ) may be a cross-sectional view of a part of the semiconductor device shown in FIG. 1B .

For example, the semiconductor element 1 shown in FIG. 1A may be a top view highlighted with a dotted frame. For example, the semiconductor device 1 shown in FIG. 1A can be formed on a periphery of a memory array. In some embodiments, the circuit density of the perimeter may be less than the density of the memory array (eg, close pitch area). For example, the minimum distance between the signal line 12 and the signal line 15 can be greater than the minimum distance between two lines in the memory array.

In some embodiments, the cross-sectional view as shown in Figure 1A (or the cross-sectional view as shown in Figure 2, or the cross-sectional view as shown in Figure 3) can be in two directions, the "X" direction (corresponding to the word line the direction along which the bit lines are elongated) and the "Y" direction (corresponding to the direction along which the bit lines are elongated). In some embodiments, the word line direction may be substantially orthogonal to the bit line direction. In some other embodiments, the word line direction may not be orthogonal to the bit line direction.

In some embodiments, the signal lines of the semiconductor device 1 (such as the signal line 12 and the signal line 15 ) can be parallel. In some embodiments, the mask lines of the semiconductor device 1 (such as the mask line 14a, the mask line 14b and the mask line 14c) may be parallel. In some embodiments, the signal lines and the mask lines of the semiconductor device 1 may be parallel.

FIG. 2 is a schematic cross-sectional view illustrating a semiconductor device 2 according to some embodiments of the present disclosure. The semiconductor element 2 of FIG. 2 is similar to the semiconductor element 1 of FIG. 1A except for the differences described below.

In FIG. 2, the width w3 of each of the dielectric element 13, the dielectric element 13', the dielectric element 16, and the dielectric element 16' may be greater than that of the mask line 14a, the mask line 14b, and the mask line 14c. Each of the width w4.

FIG. 3 is a schematic cross-sectional view illustrating a semiconductor device 3 according to some embodiments of the present disclosure. The semiconductor element 3 of FIG. 3 is similar to the semiconductor element 1 of FIG. 1A except for the differences described below.

In FIG. 3, the width w3 of each of dielectric element 13, dielectric element 13', dielectric element 16, and dielectric element 16' may be substantially equal to mask line 14a, mask line 14b, and mask line Each of 14c has a width w4.

4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, 4I, 4J, and 4K illustrate stages of the fabrication method of semiconductor devices according to some embodiments of the present disclosure. At least some of these figures have been simplified in order to better understand aspects of the present disclosure. In some embodiments, the semiconductor element 1 in FIG. 1A, the semiconductor element 2 in FIG. 2, and the semiconductor element 3 in FIG. 4F, FIG. 4G, FIG. 4H, FIG. 4I, FIG. 4J and FIG. 4K were prepared by the operation.

Referring to FIG. 4A , a substrate 10 is provided in which one or more conductive elements 11 may be formed. The fabrication technology of the conductive element 11 may come from a doped region of a bulk semiconductor substrate, or an epitaxial layer. The conductive element 11 may be at least partially exposed from the substrate 10 .

In some embodiments, the fabrication techniques of the shallow trench isolation (STI) region (not shown in the figure) may include, for example, lithography, etching, deposition, and chemical mechanical polishing (CMP) processes to form in the substrate 10 to The subsequently formed signal lines are electrically isolated.

The dielectric layer 40 can be disposed on the surface 101 of the substrate 10 . In some embodiments, the dielectric layer 40 may be blanket-like disposed on the surface 101 of the substrate 10 . In some embodiments, the fabrication technique of the dielectric layer 40 may include a thermal oxidation operation, a chemical vapor deposition (CVD) operation, a low pressure chemical vapor deposition (LPCVD) operation, a plasma enhanced chemical vapor deposition ( PECVD) operation, other feasible operations or a combination thereof. Dielectric layer 40 may include materials as listed above for dielectric element 13 , dielectric element 13 ′, dielectric element 16 , and dielectric element 16 ′ in FIG. 1A .

Mandrel layer 42 may be disposed on dielectric layer 40 . The mandrel layer 42 may be blanket disposed on the dielectric layer 40 . In some embodiments, the fabrication technique of the mandrel layer 42 may include a thermal oxidation operation, a CVD operation, an LPCVD operation, a PECVD operation, other possible operations, or combinations thereof. Mandrel layer 42 may comprise, for example, nitride, oxide, amorphous silicon oxynitride, polysilicon, or other suitable materials for the desired patterning operation as in FIG. 4C.

In some embodiments, etch stop layer 41 may be formed on dielectric layer 40 prior to forming mandrel layer 42 . In some other embodiments, the etch stop layer 41 may be omitted. For the sake of brevity, the case of the etching stop layer 41 is not illustrated in the following operations.

Referring to FIG. 4B , a mask layer 43 may be disposed on the mandrel layer 42 . The mask layer 43 may include, for example, nitride, oxide, amorphous silicon oxynitride, polysilicon, or other materials suitable for the patterning operation as shown in FIG. 4C . In some embodiments, the fabrication technique of the mask layer 43 may include, for example, a CVD operation, an LPCVD operation, a PECVD operation, other feasible operations or combinations thereof.

In some embodiments, a photoresist (not shown) and another sacrificial mask material, such as an anti-reflective coating (ARC) material, may be deposited on mask layer 43 .

Referring to FIG. 4C , the patterning technique of the mask layer 43 may include lithography and etching processes to form a mask pattern 43p. The patterning technique of the mandrel layer 42 may include using the mask pattern 43p as an etch mask. Thus, mandrels 42a and 42b may be formed.

In some embodiments, mask layer 43 and mandrel layer 42 may be anisotropically etched. In some embodiments, mask layer 43 and mandrel layer 42 may be etched in the same operation. In some embodiments, mask layer 43 and mandrel layer 42 may be etched in different operations. For example, etching techniques for mask layer 43 and mandrel layer 42 may include, for example, using reactive ion etching (RIE) with different chemistries.

Mandrel 42a and mandrel 42b may have width w2 as described with respect to FIG. 1A . Width w2 may be equal to or less than about 20 nm. Mandrel 42a and mandrel 42b may be spaced apart from each other by a minimum distance w5, as described in FIG. 1A. The minimum distance w5 may be equal to or less than about 90 nanometers.

The mandrel 42a may have a side 421 and a side 422 opposite to the side 421 . The mandrel 42b may have a side 423 and a side 424 opposite to the side 423 .

Referring to FIG. 4D, the removal technique for removing mask pattern 43p from mandrel 42a and mandrel 42b may include, for example, an etching process

Referring to FIG. 4E , a conformal gap sublayer 44 may be disposed on the dielectric layer 40 to cover the mandrels 42a and 42b. The fabrication technique for conformal spacer sublayer 44 may include silicon nitride, silicon oxide, silicon oxynitride, or any type of organic or inorganic material that has etch selectivity with respect to mandrels 42a and 42b. Fabrication techniques for the conformal gap sub-layer 44 may include, for example, an atomic layer deposition (ALD) operation, a CVD operation, an LPCVD operation, a PECVD operation, other possible operations, or combinations thereof.

Referring to FIG. 4F, the conformal spacer sublayer 44 may be partially removed to form a spacer 44a adjacent to the side 421 of the mandrel 42a, a spacer 44a' adjacent to the side 422 of the mandrel 42a, and a spacer 44a' adjacent to the side 422 of the mandrel 42a. Spacers 44b adjacent to side 423 of mandrel 42b, and spacers 44b' adjacent to side 424 of mandrel 42b. For example, the etching technique for the conformal gap sublayer 44 may include a CHF3 or CF4 based RIE operation for etching silicon oxide or silicon oxynitride, or a CHF3/O2 based etching for silicon nitride.

Spacers 44 a , 44 a ′, 44 b , and 44 b ′ are each formed with a width w3 as described with respect to FIG. 1A . Width w3 may be equal to or less than about 40 nm. For example, width w3 may be between about 10 nm and about 40 nm.

Since the minimum distance w5 between the signal line 12 and the signal line 15 remains equal to or less than about 90 nm, the width w4 may be between about 10 nm and about 70 nm.

Referring to FIG. 4G , mandrel 42 a and mandrel 42 b may be removed from dielectric layer 40 , leaving spacers 44 a , 44 a ′, 44 b , and 44 b ′ on dielectric layer 40 . For example, the etching technique for mandrels 42a and 42b may include a RIE operation.

Removal of mandrel 42a and mandrel 42b results in the formation of a gap between spacer 44a and spacer 44a', and a gap between spacer 44b and spacer 44b'. The width w2 of mandrel 42a and mandrel 42b can be controlled to determine the width w2 of the gap.

Referring to FIG. 4H , the patterning technique of the dielectric layer 40 may include etching using the spacers 44 a , 44 a ′, 44 b , and 44 b ′ as an etch mask. Accordingly, dielectric element 13, dielectric element 13', dielectric element 16, and dielectric element 16' may be formed.

Dielectric element 13 , dielectric element 13 ′, dielectric element 16 , and dielectric element 16 ′ are each formed with width w3 as described with respect to FIG. 1A . Width w3 may be equal to or less than about 40 nm. For example, width w3 may be between about 10 nm and 40 nm.

Referring to FIG. 4I, the removal technique of the spacers 44a, 44a', 44b, and 44b' may include, for example, an etching process.

Referring to FIG. 4J , a conductive layer 45 may be disposed on the substrate 10 to cover the dielectric element 13 , the dielectric element 13 ′, the dielectric element 16 and the dielectric element 16 ′. The conductive layer 45 may include, for example, polycrystalline silicon (poly-Si), metals (such as aluminum (Al), magnesium (Mg), tungsten (W), lanthanum (La), etc.), or metal alloys. The fabrication technique of the conductive layer 45 may include, for example, an ALD operation, a CVD operation, an LPCVD operation, a PECVD operation, other feasible operations or combinations thereof.

Referring to FIG. 4K, the conductive layer 45 may be partially removed to form the mask line 14a, the mask line 14b, and the mask line 14c. In addition, the fabrication of the signal line 12 and the signal line 15 can be included in the same operation.

The width w4 can be defined by a pitch multiplication process, such as a self-aligned pitch multiplication technique or a self-aligned double patterning technique. Since the minimum distance w5 between the signal line 12 and the signal line 15 remains equal to or less than about 90 nm, the width w4 may be between about 10 nm and about 70 nm.

FIG. 5 is a flowchart illustrating a method 50 of fabricating a semiconductor device according to some embodiments of the present disclosure.

In some embodiments, the manufacturing method 50 may include a step S51 of disposing a mandrel layer on a dielectric layer. For example, as shown in FIG. 4A , mandrel layer 42 may be disposed on dielectric layer 40 .

In some embodiments, the manufacturing method 50 may include step S52 of patterning the mandrel layer to form a first mandrel and a second mandrel spaced apart from the first mandrel. For example, as shown in FIG. 4C , the patterning technique of the mandrel layer 42 may include etching using the mask pattern 43p as an etch. Thus, mandrels 42a and 42b may be formed. In some embodiments, the minimum distance w5 between mandrels 42a and 42b is equal to or less than about 90 nanometers.

In some embodiments, the manufacturing method 50 may include step S53, forming a first spacer adjacent to a first side of the first mandrel, a second spacer adjacent to a second side of the first mandrel. A second spacer, a third spacer adjacent to a first side of the second mandrel, and a fourth spacer adjacent to a second side of the second mandrel. For example, as shown in FIG. 4F, conformal spacer sublayer 44 may be partially removed to form spacer 44a adjacent side 421 of mandrel 42a, spacer 44a' adjacent side 422 of mandrel 42a. , the spacer 44b adjacent to the side 423 of the mandrel 42b, and the spacer 44b adjacent to the side 424 of the mandrel 42b.

In some embodiments, the manufacturing method 50 may include step S54 of etching the dielectric layer using the first spacer, the second spacer, the third spacer, and the fourth spacer as an etching mask, so as to A first dielectric element, a second dielectric element, a third dielectric element and a fourth dielectric element are formed. For example, as shown in FIG. 4H , the patterning technique of the dielectric layer 40 may include etching using the spacers 44 a , 44 a ′, 44 b , and 44 b ′ as an etching mask. Accordingly, dielectric element 13, dielectric element 13', dielectric element 16, and dielectric element 16' may be formed.

In some embodiments, the manufacturing method 50 may include step S55 of forming a first mask line between the second dielectric element and the third dielectric element. For example, as shown in FIG. 4K , a mask line 14 b is formed between the dielectric element 13 ′ and the dielectric element 16 .

One aspect of the present disclosure provides a semiconductor device. The semiconductor element includes: a base with a surface; a first signal line disposed on the surface of the base; and a second signal line disposed on the surface of the base and spaced from the first signal line open. The semiconductor device also includes a first shielding line between the first signal line and the second signal line. A minimum distance between the first signal line and the second signal line is equal to or less than about 90 nanometers (nm).

Another aspect of the present disclosure provides a semiconductor device. The semiconductor element includes: a base with a surface; a first signal line disposed on the surface of the base; and a second signal line disposed on the surface of the base and spaced from the first signal line open. The semiconductor device also includes a first shielding line between the first signal line and the second signal line. A minimum distance between the first signal line and the first mask line is equal to or less than about 40 nm.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device. The preparation method includes: disposing a mandrel layer on a dielectric layer, and patterning the mandrel layer to form a first mandrel and a second mandrel spaced apart from the first mandrel. A minimum distance between the first mandrel and the second mandrel is equal to or less than about 90 nanometers. The manufacturing method also includes: forming a first spacer adjacent to a first side of the first mandrel, a second spacer adjacent to a second side of the first mandrel, and forming a second spacer adjacent to the first mandrel. A third spacer adjacent to a first side of the two mandrels, and a fourth spacer adjacent to a second side of the second mandrel. The preparation method further includes: using the first spacer, the second spacer, the third spacer and the fourth spacer as an etching mask to etch the dielectric layer to form a first dielectric element , a second dielectric element, a third dielectric element and a fourth dielectric element. The manufacturing method further includes: forming a first mask line between the second dielectric element and the third dielectric element.

By forming a dummy line between two signal lines (such as an aggressive (aggressor) line and a static (victim) line), and connecting the dummy line to power or ground, the gap between signal lines can be reduced or prevented. electromagnetic noise or crosstalk.

In addition, the manufacturing technique of dummy lines and signal lines may include a pitch doubling process, such as a self-aligned pitch doubling technique or a self-aligned double patterning technique. The disclosed process overcomes scaling-related lithography problems and creates denser memory arrays than conventional lithography techniques. Therefore, the performance of the element can be improved.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of this application.

1: Semiconductor components 2: Semiconductor components 3: Semiconductor components 10: Base 11: Conductive element 12: Signal line 13: Dielectric components 13': Dielectric element 14: Mask structure 14a: Mask line 14b: Mask line 14c: Mask line 15: Signal line 16: Dielectric components 16': Dielectric element 40: Dielectric layer 41: etch stop layer 42: mandrel layer 42a: mandrel 42b: mandrel 43: mask layer 43p: mask pattern 44: Conformal Gap Sublayer 44a: spacer 44a': spacer 44b: spacer 44b': spacer 50: Preparation method 101: surface 121: side 122: side 151: side 152: side 421: side 422: side 423: side 424: side S51: step S52: step S53: step S54: step S55: step w1: width w2: width w3: width w4: width w5: width

The disclosure content of the present application can be understood more comprehensively when referring to the embodiments and the patent scope of the application for combined consideration of the drawings, and the same reference numerals in the drawings refer to the same components. FIG. 1A is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 1B is a schematic top view illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 2 is a schematic cross-sectional view illustrating semiconductor devices according to some embodiments of the present disclosure. FIG. 3 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 4A illustrates one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 4B illustrates one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 4C illustrates one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 4D illustrates one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 4E illustrates one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 4F illustrates one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 4G illustrates one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 4H illustrates one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 4I illustrates one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 4J illustrates one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 4K illustrates one or more stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 5 is a flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of the present disclosure.

1: Semiconductor components

10: Base

11: Conductive element

12: Signal line

13: Dielectric components

13': Dielectric element

14: Mask structure

14a: Mask line

14b: Mask line

14c: Mask line

15: Signal line

16: Dielectric components

16': Dielectric element

101: surface

121: side

122: side

151: side

152: side

w1: width

w2: width

w3: width

w4: width

w5: width

Claims (18)

A method of manufacturing a semiconductor element, comprising: disposing a mandrel layer on a dielectric layer; patterning the mandrel layer to form a first mandrel and a second mandrel spaced apart from the first mandrel mandrels, wherein the minimum distance between the first mandrel and the second mandrel is equal to or less than about 90 nanometers; forming a first spacer adjacent a first side of the first mandrel, and A second spacer adjacent to a second side of the first mandrel, a third spacer adjacent to a first side of the second mandrel, and a second spacer adjacent to a second side of the second mandrel A fourth spacer adjacent to the side; use the first spacer, the second spacer, the third spacer and the fourth spacer as an etching mask to etch the dielectric layer to form a first spacer a dielectric element, a second dielectric element, a third dielectric element, and a fourth dielectric element; and a first mask line formed between the second dielectric element and the third dielectric element . The manufacturing method as claimed in claim 1, further comprising: disposing an etching stop layer on the dielectric layer. The manufacturing method as claimed in claim 1, further comprising: disposing a conformal gap sublayer to cover the first mandrel and the second mandrel. The preparation method as described in claim item 3, further comprising: The conformal spacer sublayer is partially removed to form the first spacer, the second spacer, the third spacer, and the fourth spacer. The preparation method according to claim 1, wherein the minimum width of each of the first spacer, the second spacer, the third spacer and the fourth spacer is between about 10 nanometers and about 40 nanometers between meters. The manufacturing method as claimed in claim 1, further comprising: removing the first mandrel and the second mandrel from the dielectric layer before etching the dielectric layer. The manufacturing method according to claim 1, wherein each of the first dielectric element, the second dielectric element, the third dielectric element, and the fourth dielectric element has a minimum width of about 10 nanometers and between about 40 nm. The manufacturing method according to claim 1, further comprising: disposing a conductive layer to cover the first dielectric element, the second dielectric element, the third dielectric element, and the fourth dielectric element. The preparation method as claimed in item 8 further includes: partially removing the conductive layer to form a first signal line and a second signal line. The preparation method as claimed in item 1, wherein the minimum width of the first mask line is about 10 nanometers meters to about 70 nm. The manufacturing method according to claim 9, further comprising: forming a second mask line, wherein the first signal line is disposed between the first mask line and the second mask line. The manufacturing method as claimed in claim 11, wherein the first mask wire is electrically connected to the second mask wire. The manufacturing method according to claim 11 further includes: forming a third mask line, wherein the second signal line is disposed between the first mask line and the third mask line. The manufacturing method as claimed in claim 13, wherein the first mask wire is electrically connected to the third mask wire. The manufacturing method according to claim 13, wherein the first mask line, the second mask line and the third mask line are substantially parallel. The manufacturing method as claimed in item 11, further comprising: forming a first dielectric element in contact with a first side of the first signal line; and a first dielectric element in contact with a second side of the first signal line Two dielectric elements, the second side is opposite to the first side. The method of claim 16, wherein the minimum width of the first dielectric element is substantially equal to the minimum width of the second dielectric element. The manufacturing method as claimed in claim 16, wherein the first side and the second side of the first signal line are substantially perpendicular to the surface of the substrate.

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