TWI809742B - Semiconductor device - Google Patents

Abstract

A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate having a surface. The surface has a first portion and a second portion protruding from the first portion. The semiconductor device also includes a dielectric layer disposed on the second portion and a gate conductive layer disposed on the dielectric layer.

Description

semiconductor element

This application claims priority from U.S. Patent Application Nos. 17/541,845 and 17/543,914 (i.e., with priority dates of "December 3, 2021" and "December 7, 2021"), the content of which is It is incorporated herein by reference in its entirety.

The disclosure relates to a semiconductor device and a method for preparing the semiconductor device. In particular it relates to a semiconductor device with a low gate height.

Metal oxide semiconductor field effect transistors (MOSFETs) are commonly used in memory devices, including dynamic random access memory (DRAM) devices. Fabrication techniques for a MOSFET generally include providing a gate structure on a semiconductor substrate to define a channel region; and forming source and drain regions on opposite sides of the channel region.

As DRAM device dimensions shrink, parasitic capacitances (eg, peripheral capacitance, gate-to-plug capacitance, plug-to-plug capacitance) and parasitic resistance become significant, thereby reducing device performance.

In addition, short channel effects (such as a punch through phenomenon) may occur when the channel length is reduced. Due to the short channel effect, a DRAM device may experience problems with the gate not being able to adequately control the on and off states of the channel region, and variations in electrical characteristics may occur.

The above "prior art" description only provides background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" is It should not be part of this case.

An embodiment of the present disclosure provides a semiconductor device. The semiconductor element includes a base with a surface. The surface has a first portion and a second portion protruding from the first portion. The semiconductor element also includes a dielectric layer disposed on the second portion; and a gate conductive layer disposed on the dielectric layer.

Another embodiment of the disclosure provides a semiconductor device. The semiconductor element includes a base with a first surface and a second surface, and the second surface protrudes from the first surface of the base. The semiconductor device also includes a gate oxide layer disposed on the second surface of the substrate; and a first spacer disposed on the first surface of the substrate. The first spacer contacts the substrate and the gate oxide layer.

Yet another embodiment of the present disclosure provides a method for manufacturing a semiconductor device. The method includes arranging a dielectric layer on a substrate; arranging a gate conductive layer on the dielectric layer; The surfaces on one side are approximately coplanar.

The gate conductive layer can be reduced by forming a gate structure (comprising a gate conductive layer and a dielectric layer) on an elevated portion of a substrate, then raising the gate conductive layer The height of the gate structure remains substantially constant. The reduced height of the gate conductive layer can avoid or reduce unnecessary parasitic capacitance compared to a conventional structure (eg, the gate structure is not raised and the height of the gate conductive layer is larger). In addition, since the substrate has a raised portion and raises the gate conductive layer, the effective channel length is increased and can reduce short channel effect.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

1: Semiconductor components

1': semiconductor element

1": semiconductor components

10: Base

10a: Doped area

10b: Doped area

10c: Lifting part

11: Dielectric layer

11': dielectric layer

12: Gate conductive layer

12': gate conductive layer

12a: Sublayer

12b: sublayer

13: cover layer

14': dielectric layer

14: spacer

15: spacer

20': Hard mask

20: Hard mask pattern

30: Preparation method

101: surface

101a: part

101b: part

101c: part

102: surface

111: surface

121: surface

131: surface

H1: height

H2: height

S31: step

S32: step

S33: step

S34: step

S35: step

S36: step

S37: step

The disclosure content of the present application can be understood more fully when the drawings are considered together with the embodiments and the patent scope of the application. The same reference numerals in the drawings refer to the same components.

FIG. 1A is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

FIG. 1B is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

FIG. 1C is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

FIG. 2A is a schematic cross-sectional view illustrating one or more stages in the method for fabricating a semiconductor device according to some embodiments of the present disclosure.

FIG. 2B is a schematic cross-sectional view illustrating one or more stages in the method of fabricating a semiconductor device according to some embodiments of the present disclosure.

2C is a schematic cross-sectional view illustrating one or more stages in the method of fabricating a semiconductor device according to some embodiments of the present disclosure.

FIG. 2D is a schematic cross-sectional view illustrating one or more stages in the method for fabricating a semiconductor device according to some embodiments of the present disclosure.

FIG. 2E is a schematic cross-sectional view illustrating the fabrication method of semiconductor devices according to some embodiments of the present disclosure. one or more stages in the law.

FIG. 2F is a schematic cross-sectional view illustrating one or more stages in the method for fabricating a semiconductor device according to some embodiments of the present disclosure.

FIG. 2G is a schematic cross-sectional view illustrating one or more stages in the method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

FIG. 2H is a schematic cross-sectional view illustrating one or more stages in the method for fabricating a semiconductor device according to some embodiments of the present disclosure.

FIG. 2I is a schematic cross-sectional view illustrating one or more stages in the method of fabricating a semiconductor device according to some embodiments of the present disclosure.

FIG. 2J is a schematic cross-sectional view illustrating one or more stages in the method of fabricating a semiconductor device according to some embodiments of the present disclosure.

FIG. 3 is a schematic flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of the present disclosure.

The various embodiments (or examples) of the disclosure depicted in the drawings are now described using specific language. It should be understood that no limitation of the scope of the present disclosure is meant here. Any changes or modifications of the described embodiments, and any further application of the principles described in this document, are considered to be within the ordinary skill of the art to which this disclosure pertains. Element numbers may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another, even if they share the same element number.

It will be understood that although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not constrained by these terms. limits. Instead, these terms are used only to refer to a An element, component, region, layer or section is distinguished from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the presently advanced concepts.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that when the terms "comprises" and/or "comprising" are used in this specification, these terms specify the stated features, integers, steps, operations, elements, and/or components. Presence, but not excluding the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups of the above.

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device 1 according to some embodiments of the present disclosure. In some embodiments, the semiconductor device 1 may include a circuit, such as a memory cell. In some embodiments, the memory cell may include a dynamic random access memory cell (DRAM cell).

In some embodiments, the semiconductor element 1 can be or comprise part of an integrated circuit (IC) wafer comprising various passive or active microelectronic elements such as resistors, capacitors, inductors, diodes, p-type Field effect transistors (pFETs), n-type field effect transistors (nFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (complementary metal-oxide semiconductor, CMOS) transistors, bipolar junction Bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, fin field effect transistors (FinFETs), other suitable IC components or combinations thereof.

While two MOSFETs are shown in the figures, it should be understood that the semiconductor element 1 can be or include any suitable number of passive and active microelectronic elements as described.

As shown in FIG. 1 , in some embodiments, a semiconductor device 1 may include a substrate 10 , a dielectric layer 11 , a gate conductive layer 12 , a capping layer 13 and spacers 14 , 15 .

In some embodiments, for example, substrate 10 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), arsenide Gallium (GaAs), Indium (In), Indium Arsenide (InAs), Indium Phosphide (InP) or other Group IV-IV, III-V or II-VI semiconductor materials. In some other embodiments, the substrate 10 may include a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a silicon-on-insulator substrate. An overlying germanium (DOI) substrate.

Depending on the stage of IC fabrication, substrate 10 may include layers of different materials (eg, multiple dielectric layers, multiple semiconductor layers, and/or multiple conductive layers) configured to form IC features (eg, multiple doped regions, multiple isolation features, gate features, source/drain features, interconnect features, other features, or combinations thereof).

The substrate 10 of FIG. 1A has been simplified for clarity. It should be understood that additional features may be added to substrate 10, and in other embodiments, some of the features described below may be substituted, modified, or eliminated.

In the illustrated embodiment, the substrate 10 may include a surface 101 and a surface 102 , and the surface 102 is disposed opposite to the surface 101 . In some embodiments, the surface 101 can be an active surface, and the surface 101 can be a rear surface of the substrate 10 .

In some embodiments, surface 101 may include a portion 101a, a portion 101b, and a portion 101c. In some embodiments, portion 101a may not be coplanar with portion 101c. In some embodiments, portion 101a may protrude from portion 101c. In some embodiments, portion 101c may be recessed from portion 101a. In some embodiments, the portion 101a and the portion 101c may be substantially parallel. In some embodiments, portion 101b may extend between portion 101a and portion between 101c and 101c. In some embodiments, portion 101b may be connected between portion 101a and portion 101c. In some embodiments, portion 101b may be disposed at an angle relative to portion 101a and/or portion 101c. In some embodiments, portion 101b may be substantially perpendicular to portions 101a and/or 101c.

In some embodiments, the surface 101 may define a stepped structure. For example, the portion 101 a , the portion 101 b , and the portion 101 c may define a stepped structure of the substrate 10 .

In some embodiments, portion 101a , portion 101b , and portion 101c may define a raised or raised portion 10c of base 10 . In some embodiments, the raised portion 10c may be configured to lift or raise the gate structure (including the dielectric layer 11 , the gate conductive layer 12 and the capping layer 13 ). For example, the gate structure (including the dielectric layer 11 , the gate conductive layer 12 and the capping layer 13 ) can be separated from the portion 101c of the surface 101 by the raised portion 10c.

In some embodiments, a channel region (not shown) may be formed in the substrate 10 below the dielectric layer 11 , such as formed in the raised portion 10c. In some embodiments, the channel region in substrate 10 may be doped. In some embodiments, the gate conductive layer 12 can be configured to affect or control the number of charge carriers in the channel region.

In some embodiments, the substrate 10 may have a doped region 10 a and a doped region 10 b disposed on or in the substrate 10 . In some embodiments, the doped region 10 a and the doped region 10 b may be disposed on or close to the surface 101 of the substrate 10 .

In some embodiments, the doped region 10a may include a lightly doped region, such as a lightly doped drain (LDD) region. The doped region 10a may be adjacent to the channel region under the dielectric layer 11 and extend laterally away from the channel region. In some embodiments, for an NMOS device, the doped region 10a is doped with N-type dopants (such as phosphorus (P), arsenic (As) or antimony (Sb)), and the channel region can be Doped with P-type dopants. In some other embodiments, for a PMOS device, the doped region 10a is doped with a P-type dopant (such as boron (B) or indium (In)), and the channel region may be doped with an N-type dopant. thing.

In some embodiments, the doped region 10a may have a doping concentration which is lower than a doping concentration of the doped region 10b. In some embodiments, the doped region 10 a may be wider than the channel region under the dielectric layer 11 . In some embodiments, the doped region 10a can reduce the electric field between the doped region 10b and the channel region and help minimize hot carrier effects.

In some embodiments, the doped region 10 a may be at least partially exposed from the raised portion 10 c of the substrate 10 . For example, doped region 10 a may be at least partially exposed from portion 101 a , portion 101 b and/or portion 101 c of surface 101 of substrate 10 .

In some embodiments, the doped region 10b includes a heavily doped region. In some embodiments, the doped region 10b may include a source region and/or a drain region. In some embodiments, the doped region 10b may be disposed in the doped region 10a. In some embodiments, the doped region 10b may be surrounded by the doped region 10a. In some embodiments, the doped region 10b may be adjacent to the doped region 10a. In some embodiments, the fabrication technique of the doped region 10b may include implanting N-type (for NMOS devices) into the substrate 10 at a doping level significantly higher than the ion implantation dose used to form the doped region 10a. words) or P-type dopants (for PMOS devices). The doped region 10 a and the doped region 10 b may have the same doping type. In regions where doped region 10b overlaps with doped region 10a, the more heavily doped level of doped region 10b can overcome the lighter doped level of doped region 10a. Therefore, a source region and/or a drain region may be formed in overlapping these regions.

In some embodiments, the doped region 10b may not be exposed from the raised portion 10c of the substrate 10, as shown in FIG. 1A. However, in some other embodiments, the doped region 10b may be at least partially exposed from the raised portion 10c of the substrate 10 . For example, the doped region 10b can be formed from the substrate 10 Portions 101a, 101b and/or 101c of the surface 101 are at least partially exposed.

In some embodiments, the dielectric layer 11 may be disposed on the portion 101 a of the surface 101 of the substrate 10 . For example, the dielectric layer 11 may contact a portion 101 a of the surface 101 of the substrate 10 . For example, the dielectric layer 11 may overlap a portion 101 a of the surface 101 of the substrate 10 . In some embodiments, the dielectric layer 11 may be separated from the portion 101c of the surface 101 of the substrate 10 . For example, the dielectric layer 11 may not be in contact with the portion 101c of the surface 101 of the substrate 10 .

In some embodiments, the dielectric layer 11 may have a surface (or a side surface) substantially coplanar with the portion 101b of the surface 101 of the substrate 10 .

In some embodiments, the dielectric layer 11 may include a gate oxide layer. In some embodiments, for example, the dielectric layer 11 may include hafnium silicate (HfSiO _x ), hafnium oxide (HfO ₂ ), zirconium silicate (ZrSiO _x ), zirconium oxide (zirconium oxide, ZrO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), or silicon oxide (SiO ₂ ). In some embodiments, the dielectric layer 11 may have a single-layer structure. In some embodiments, the dielectric layer 11 may have a plurality of layers stacked on top of each other.

In some embodiments, the gate conductive layer 12 may be disposed on the dielectric layer 11 . For example, the gate conductive layer 12 can contact the dielectric layer 11 . In some embodiments, the gate conductive layer 12 , the dielectric layer 11 and the portion 101a of the surface 101 of the substrate 10 may overlap. In some embodiments, the dielectric layer 11 may be disposed between the gate conductive layer 12 and the portion 101 a of the surface 101 of the substrate 10 . In some embodiments, the gate conductive layer 12 may be separated from the portion 101c of the surface 101 of the substrate 10 . For example, the gate conductive layer 12 may not contact the portion 101 c of the surface 101 of the substrate 10 .

In some embodiments, the gate conductive layer 12 may have a surface (or one side The surface 121 is substantially coplanar with the portion 101b of the surface 101 of the substrate 10 and/or the surface 111 of the dielectric layer 11 .

In some embodiments, the gate conductive layer 12 may include a gate electrode, a gate metal or a gate conductor. In some embodiments, for example, the gate conductive layer 12 may include polysilicon (poly-Si), metal (such as aluminum (Al), magnesium (Mg), tungsten (W), lanthanum (La), etc.) or metal alloy. In some embodiments, for example, the gate conductive layer 12 may include titanium-based materials (such as titanium nitride (TiN) or titanium aluminum nitride (TiAlN)), tantalum-based materials (such as tantalum nitride (TaN), tantalum aluminum nitride (TaAlN) or tantalum carbide (Ta ₂ C)) or silicides (such as PtSi, TiSi ₂ , CoSi, NiSi, MoSi ₂ , TaSi, WSi ₂ , etc.). In some embodiments, the gate conductive layer 12 may include a single-layer structure as shown in FIG. 1A or a multi-layer structure (which will be described below with respect to FIG. 1B ).

In some embodiments, the cap layer 13 may be disposed on the gate conductive layer 12 . For example, the cap layer 13 can contact the gate conductive layer 12 . In some embodiments, the capping layer 12 , the dielectric layer 11 , and the portion 101 a of the surface 101 of the substrate 10 may overlap. In some embodiments, the gate conductive layer 12 may be disposed between the dielectric layer 11 and the capping layer 13 . In some examples, the capping layer 13 may be separated from the portion 101c of the surface 101 of the substrate 10 . For example, the capping layer 13 may not contact the portion 101 c of the surface 101 of the substrate 10 .

In some embodiments, the cover layer 13 may have a surface (or one side surface) 131 substantially in line with the portion 101b of the surface 101 of the substrate 10, the surface 111 of the dielectric layer 11 and/or the surface of the gate conductive layer 12. The surfaces 121 are coplanar.

In some embodiments, the capping layer 13 may include an insulator-on-gate. In some embodiments, for example, the capping layer 13 may include Si ₃ N ₄ , SiON or SiO ₂ . In some embodiments, for example, the capping layer 13 may include titanium-based materials such as titanium nitride (TiN) or titanium aluminum nitride (TiAlN), tantalum-based materials such as tantalum nitride (TaN), nitrogen tantalum aluminum (TaAlN) or tantalum carbide (Ta ₂ C)) or silicides (such as PtSi, TiSi ₂ , CoSi, NiSi, MoSi ₂ , TaSi, WSi ₂ , etc.).

In some embodiments, the spacer 14 may be disposed on the portion 101 c of the surface 101 of the substrate 10 . In some embodiments, the spacer 14 may contact the portion 101c of the surface 101 of the substrate 10, the portion 101b of the surface 101 of the substrate 10, the surface 111 of the dielectric layer 11, the surface 121 of the gate conductive layer 12, and/or the cover. surface 131 of layer 13 . In some embodiments, the spacers 14 may not contact the portion 101 a of the surface 101 of the substrate 10 .

In some embodiments, the spacer 14 can cover, seal or encapsulate the gate structure (including the dielectric layer 11 , the gate conductive layer 12 and the capping layer 13 ) on the substrate 10 . In some embodiments, the spacer 14 may extend between the cap layer 13 and the portion 101 c of the surface 101 of the substrate 10 .

In some embodiments, the spacer 15 may be disposed on the portion 101 c of the surface 101 of the substrate 10 . In some embodiments, the spacer 15 may contact a portion 101 c of the surface 101 of the substrate 10 . In some embodiments, spacer 15 may contact spacer 14 .

In some embodiments, the spacer 14 may be disposed between the spacer 15 and the portion 101 b of the surface 101 of the substrate 10 . In some embodiments, the spacer 14 may be disposed between the spacer 15 and the portion 101 a of the surface 101 of the substrate 10 . In some embodiments, the spacer 14 may be disposed between the spacer 15 and the surface 111 of the dielectric layer 11 . In some embodiments, the spacer 14 may be disposed between the spacer 15 and the surface 121 of the gate conductive layer 12 . In some embodiments, the spacer 14 may be disposed between the spacer 15 and the surface 131 of the cover layer 13 .

In some embodiments, for example, the spacers 14 and 15 may include nitride, oxide or oxynitride. Exemplary interstitial materials may include silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), silicon oxide (SiO ₂ ), tetraethylorthosilicate (TEOS), carbon-doped nitride, or doped A carbonitride element without an oxide, but not limited thereto.

In some embodiments, the gate conductive layer 12 may have a height H1. The height H1 can be measured in a direction that is substantially perpendicular to the portion 101 a of the surface 101 of the substrate 10 . The height H1 can be defined between an upper surface of the gate conductive layer 12 (contacting the capping layer 13 ) and a lower surface of the gate conductive layer 12 (contacting the dielectric layer 11 ). The height H1 may be defined by the surface 12 of the gate conductive layer 12 .

In some embodiments, the raised portion 10c of the base 10 may have a height H2. The height H2 can be measured in a direction that is substantially perpendicular to the portion 101 a of the surface 101 of the substrate 10 . Height H2 may be defined between portion 101 a of surface 101 of substrate 10 and portion 101 c of surface 101 of substrate 10 . The height H2 may be defined by the portion 101b of the surface 101 of the substrate 10 .

In some embodiments, the height H1 of the gate conductive layer 12 may be different from the height H2 of the raised portion 10 c of the substrate 10 . In some embodiments, the height H1 of the gate conductive layer 12 may be greater than the height H2 of the raised portion 10 c of the substrate 10 . In some embodiments, the height H1 of the gate conductive layer 12 may be smaller than the height H2 of the raised portion 10 c of the substrate 10 . In some embodiments, a ratio of height H1 to height H2 may be between about 3:2 and about 9:1.

As the size of DRAM devices (such as the semiconductor device 1 ) shrinks, parasitic capacitances (such as fringe capacitance, gate-to-plug capacitance, plug-to-plug capacitance) and parasitic resistance become significant, thereby reducing device performance. In addition, short channel effects (such as a punch through phenomenon) may occur when the channel length is reduced. Due to the short channel effect, a DRAM device (such as a DRAM device) may encounter a problem that the gate (such as the gate conductive layer 12) cannot sufficiently control the on and off states of the channel region, and variations in electronic characteristics may occur .

According to some embodiments of the present disclosure, the gate structure (including the dielectric layer 11 , the gate conductive layer 12 and the cover layer 13 ) is disposed on the raised portion 10 c of the substrate 10 . Therefore, the gate conductive layer 12 is raised, and the height H1 of the gate conductive layer 12 can be reduced, while the overall height of the gate structure (eg, the total height measured from the portion 101c of the surface 101 to the uppermost surface of the gate structure) remain largely unchanged.

Compared with a conventional structure (eg, the gate conductive layer is not raised and the height of the gate conductive layer is larger), the reduced height of the gate conductive layer 12 can avoid or reduce unnecessary parasitic capacitance.

In addition, since the substrate 10 has the raised portion 10c and the gate conductive layer 12 is raised, the effective channel length in the channel region under the dielectric layer 11 is increased and the short channel effect can be eliminated.

FIG. 1B is a schematic cross-sectional view illustrating a semiconductor device 1 ′ according to some embodiments of the present disclosure. The semiconductor component 1' of FIG. 1B is similar to the semiconductor component 1 of FIG. 1A except for the differences described below.

In FIG. 1B , the gate conductive layer 12 of the semiconductor device 1 ′ may include a multi-layer structure. For example, the gate conductive layer 12 of the semiconductor device 1' may include a sub-layer 12a and a sub-layer 12b.

In some embodiments, sub-layer 12a may be disposed on sub-layer 12b. For example, sub-layer 12a may contact sub-layer 12b. In some embodiments, sub-layer 12a may be disposed between sub-layer 12b and cover layer 13 . In some embodiments, sub-layer 12a may include polysilicon, for example.

In some embodiments, sub-layer 12b may be disposed on dielectric layer 11 . In some embodiments, the sub-layer 12b may contact the dielectric layer 11 . In some embodiments, sub-layer 12b can be provided Between the dielectric layer 11 and the sublayer 12a. In some embodiments, for example, sub-layer 12b may include a metal (eg, Al, Mg, W, La, etc.) or a metal alloy.

In some embodiments, the height H1 of the gate conductive layer 12 (including the sub-layers 12 a and 12 b ) may be different from the height H2 of the raised portion 10 c of the substrate 10 . In some embodiments, the height H1 of the gate conductive layer 12 (including the sub-layers 12 a and 12 b ) may be greater than the height H2 of the raised portion 10 c of the substrate 10 . In some embodiments, the height H1 of the gate conductive layer 12 (including the sub-layers 12 a and 12 b ) may be smaller than the height H2 of the raised portion 10 c of the substrate 10 . In some embodiments, the ratio of height H1 to height H2 may be between about 3:2 and about 9:1.

FIG. 1C is a schematic cross-sectional view illustrating a semiconductor device 1 ″ of some embodiments of the present disclosure. The semiconductor device 1 ″ of FIG. 1C is similar to the semiconductor device 1 of FIG. 1A except for the differences described below.

In FIG. 1C, the doped region 10a of the semiconductor element 1" is separated from the raised portion 10c of the substrate 10. For example, the doped region 10a of the semiconductor element 1" is not separated from the portion 101a of the surface 101 of the substrate 10 And/or part 101b is exposed.

Figure 2A, Figure 2B, Figure 2C, Figure 2D, Figure 2E, Figure 2F, Figure 2G, Figure 2H, Figure 2I, and Figure 2J are schematic cross-sectional views illustrating various stages in the manufacturing method of semiconductor devices according to some embodiments of the present disclosure . At least some of these diagrams have been simplified to better understand the purpose of this disclosure. In some embodiments, the semiconductor device 1 in FIG. 1A, the semiconductor device 1' in FIG. 1B and the semiconductor device 1" in FIG. 2C, 2D, 2E, 2F, 2G, 2H, 2I, 2J.

Referring to FIG. 2A , a substrate 10 is provided. In some embodiments, a plurality of shallow trench isolation (STI) regions (not shown) may be formed in substrate 10, for example, using lithography, etching, deposition, and chemical mechanical planarization (CMP) processes. , with the next formed MOSFETs are electrically isolated.

In some embodiments, a dielectric layer 11 ′ can be disposed on the surface 101 of the substrate 10 . In some embodiments, the fabrication technique of the dielectric layer 11' may include a thermal oxidation operation. In some other embodiments, for example, the dielectric layer 11' can be deposited by chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or other possible operations. or a combination thereof.

In some embodiments, a gate conductive layer 12' can be disposed on the dielectric layer 11'. In some embodiments, the gate conductive layer 12' may be a polysilicon layer, and its fabrication technique includes depositing undoped polysilicon and then doping impurities by ion implantation. In some other embodiments, the gate conductive layer 12' may include a multi-layer structure. For example, the fabrication technique of the gate conductive layer 12 ′ may include atomic layer deposition (ALD), physical vapor deposition (PVD), CVD, a silicidation process, other feasible operations or combinations thereof.

In some embodiments, a hard mask 20' may be deposited on the gate conductive layer 12'. In some embodiments, hard mask 20 ′ may include Si3N4, SiON, SiO2, or TiN, for example. In some embodiments, for example, the hard mask 20' may be formed by CVD, LPCVD, PECVD, other possible operations, or combinations thereof.

Referring to FIG. 2B , the hard mask 20 ′ can be patterned using lithography and etching processes to form a hard mask pattern 20 . The dielectric layer 11' and the gate conductive layer 12' can be sequentially patterned by etching using the hard mask pattern 20 as an etch mask. Therefore, the dielectric layer 11 and the gate conductive layer 12 can be formed.

In some embodiments, the dielectric layer 11' and the gate conductive layer 12' can be etched anisotropically. In some embodiments, the dielectric layer 11 ′ and the gate conductive layer 12 ′ can be etched in the same operation. In some embodiments, the dielectric layer 11' and the gate conductive layer 12' may be performed differently. etch. For example, the dielectric layer 11' and the gate conductive layer 12' can be etched by using, for example, reactive ion etching (RIE) with different chemistries.

In some embodiments, after the dielectric layer 11 and the gate conductive layer 12 are formed, the surface (or one side surface) 111 of the dielectric layer 11 can be sequentially connected with the gate conductive layer 12 surface (or one side surface). surface) 121 and are coplanar.

Referring to FIG. 2C , the substrate 10 can be patterned by etching using the hard mask pattern 20 as an etching mask. Accordingly, the raised portion 10c can be formed.

In some embodiments, substrate 10 may be anisotropically etched. In some embodiments, the substrate 10 may be etched in a different operation than the dielectric layer 11' and the gate conductive layer 12' in FIG. 2A. For example, the substrate 10 may be etched using, for example, RIE having a different chemistry than the dielectric layer 11' and the gate conductive layer 12'.

In some embodiments, the portion 101a of the surface 101 of the substrate 10 may protrude from the portion 101c of the surface 101 of the substrate 10 after the raised portion 10c is formed.

In some embodiments, the portion 101 b of the surface 101 of the substrate 10 may be substantially coplanar with the surface 111 of the dielectric layer 11 and/or the surface 121 of the gate conductive layer 12 .

Referring to FIG. 2D, for example, the hard mask pattern 20 can be removed by an etching process.

Referring to FIG. 2E , a cap layer 13 may be deposited on the gate conductive layer 12 . In some other embodiments, the manufacturing technique of the capping layer 13 may include ALD, PVD, CVD, a siliconization process, other feasible operations or combinations thereof. In some embodiments, for example, the capping layer 12 may be partially removed by an etching process.

In some embodiments, the surface (or one side surface) 131 of the cover layer 13 may be substantially conductive to the portion 101b of the surface 101 of the substrate 10, the surface 111 of the dielectric layer 11, and/or the gate. Surfaces 121 of layer 12 are coplanar.

Referring to FIG. 2F , a dielectric layer 14 ′ can be disposed on the gate structure (including the dielectric layer 11 , the gate conductive layer 12 and the capping layer 13 ) on the substrate 10 . In some embodiments, for example, the dielectric layer 14 may be formed by CVD, LPCVD, PECVD, other possible operations, or combinations thereof. In some embodiments, the dielectric layer 14 ′ may cover the portion 101 b and the portion 101 c of the surface 101 of the substrate 10 . In some embodiments, the dielectric layer 14 ′ can cover the surface 111 of the dielectric layer 11 , the surface 121 of the gate conductive layer 12 , and the surface 131 of the capping layer 13 .

Referring to FIG. 2G , a doped region 10 a may be formed in the substrate 10 . In some embodiments, for example, the fabrication technique of the doped region 10 a may include an ion implantation operation, such as plasma-immersion ion implantation, solid-state diffusion, and the like. In some embodiments, an annealing process may be performed to remove implant-induced damage and/or lattice defects. In some embodiments, the dielectric layer 14 ′ prevents a plurality of dopants from penetrating into the substrate 10 . Therefore, the doped region 10a may have a doping concentration lower than a doping concentration of the subsequently formed doped region 10b.

In some other embodiments, before the dielectric layer 14' is formed, a blanket light ion implantation operation may be performed to form the doped region 10a.

Referring to FIG. 2H , the dielectric layer 14 ′ can be anisotropically etched to form spacers 14 . After the etching operation, the cap layer 13 and a portion 101c of the surface 101 of the substrate 10 may be exposed.

Referring to FIG. 2I , the spacer 15 may be disposed on the portion 101c of the surface 101 of the substrate 10 . In some embodiments, for example, the fabrication techniques of the spacers 15 may include CVD, LPCVD, PECVD, other possible operations or combinations thereof. An etching operation (such as RIE) may then be performed to remove a portion of the spacer 15 and expose a portion of the surface 101 of the substrate 10. Part of MIN 101c.

Referring to FIG. 2J , a doped region 10 b may be formed in the substrate 10 . In some embodiments, for example, the fabrication technique of the doped region 10b may include an ion implantation operation, such as plasma-immersion ion implantation, solid-state diffusion, and the like. In some embodiments, the doped region 10b can be formed by etching using the spacer 15 as an ion implantation mask.

In some embodiments, the fabrication technique of the doped region 10b may include implanting N-type (for NMOS devices) into the substrate 10 at a doping level significantly higher than the ion implantation dose used to form the doped region 10a. words) or P-type dopants (for PMOS devices). In regions where doped region 10b overlaps with doped region 10a, the more heavily doped level of doped region 10b can overcome the lighter doped level of doped region 10a. Therefore, a source region and/or a drain region may be formed in overlapping these regions.

FIG. 3 is a schematic flow diagram illustrating a method 30 for fabricating a semiconductor device according to some embodiments of the present disclosure.

In some embodiments, the manufacturing method 30 may include a step S31 of disposing a dielectric layer on a substrate. For example, as shown in FIG. 2A , a dielectric layer 11 ′ can be disposed on the surface 101 of the substrate 10 .

In some embodiments, the manufacturing method 30 may include a step S32 of disposing a gate conductive layer on the dielectric layer. For example, as shown in FIG. 2A , the gate conductive layer 12 ′ can be disposed on the dielectric layer 11 ′.

In some embodiments, the manufacturing method 30 may include a step S33 of forming a surface of the substrate to be coplanar with one side surface of the dielectric layer and one side surface of the gate conductive layer. For example, as shown in FIG. 2C, a portion 101b of the surface 101 of the substrate 10 may be approximately the same as the dielectric Surface 111 of layer 11 and/or surface 121 of gate conductive layer 12 are coplanar.

In some embodiments, the manufacturing method 30 may include a step S34 of disposing a first spacer on the surface of the substrate, the side surface of the dielectric layer, and the side surface of the gate conductive layer. For example, as shown in FIG. 2H , the spacers 14 may be disposed on the surface 111 of the dielectric layer 11 , the surface 121 of the gate conductive layer 12 , and the surface 131 of the capping layer 13 .

In some embodiments, the manufacturing method 30 may include a step S35 of forming a lightly doped region in the substrate. For example, as shown in FIG. 2G , a doped region 10 a may be formed in the substrate 10 .

In some embodiments, the manufacturing method 30 may include a step S36 of disposing a second spacer on the surface of the substrate. For example, as shown in FIG. 2I , the spacer 15 may be disposed on the portion 101 c of the surface 101 of the substrate 10 .

In some embodiments, the manufacturing method 30 may include a step S37 of forming a heavily doped region in the substrate. For example, as shown in FIG. 2J , a doped region 10 b may be formed in the substrate 10 .

An embodiment of the present disclosure provides a semiconductor device. The semiconductor element includes a base with a surface. The surface has a first portion and a second portion protruding from the first portion. The semiconductor element also includes a dielectric layer disposed on the second portion; and a gate conductive layer disposed on the dielectric layer.

Another embodiment of the disclosure provides a semiconductor device. The semiconductor element includes a base with a first surface and a second surface, and the second surface protrudes from the first surface of the base. The semiconductor device also includes a gate oxide layer disposed on the second surface of the substrate; and a first spacer disposed on the first surface of the substrate. The first spacer contacts the substrate and the gate oxide layer.

Yet another embodiment of the present disclosure provides a method for manufacturing a semiconductor device. The method includes arranging a dielectric layer on a substrate; arranging a gate conductive layer on the dielectric layer; The surfaces on one side are approximately coplanar.

The gate conductive layer can be reduced by forming a gate structure (comprising a gate conductive layer and a dielectric layer) on an elevated portion of a substrate, then raising the gate conductive layer The height of the gate structure remains substantially constant. The reduced height of the gate conductive layer can avoid or reduce unnecessary parasitic capacitance compared to a conventional structure (eg, the gate structure is not raised and the height of the gate conductive layer is larger). In addition, since the substrate has a raised portion and raises the gate conductive layer, the effective channel length is increased and short channel effects can be reduced.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such process, machinery, manufacture, material composition, means, method, or steps are included in the patent scope of this application.

1: Semiconductor components

10: Base

10a: Doped area

10b: Doped area

10c: Lifting part

11: Dielectric layer

12: Gate conductive layer

13: cover layer

14: spacer

15: spacer

101: surface

101a: part

101b: part

101c: part

102: surface

111: surface

121: surface

131: surface

H1: height

H2: height

Claims (13)

A semiconductor element, comprising: a base with a surface, wherein the surface has a first portion, a second portion and a third portion, the second portion protrudes from the first portion, the third portion extends over the first portion between a part and the second part; a dielectric layer disposed on the second part; and a gate conductive layer disposed on the dielectric layer; a first spacer contacting the surface of the substrate The third part. The semiconductor device as claimed in claim 1, wherein the first portion is substantially parallel to the second portion. The semiconductor device as claimed in claim 1, wherein one side surface of the dielectric layer is substantially coplanar with one side surface of the gate conductive layer. The semiconductor device as claimed in claim 3, wherein the third portion is substantially coplanar with the side surface of the dielectric layer and the side surface of the gate conductive layer. The semiconductor device as claimed in claim 1, wherein the first spacer also contacts the side surface of the dielectric layer and the side surface of the gate conductive layer. The semiconductor device as claimed in claim 1, wherein the first spacer also contacts the substrate of the the first part of the surface. The semiconductor device according to claim 1, further comprising a second spacer contacting the first spacer. The semiconductor device as claimed in claim 7, wherein the second spacer also contacts the first portion of the surface of the substrate. The semiconductor device as claimed in claim 7, wherein the first spacer is disposed between the third portion of the surface of the substrate and the second spacer. The semiconductor device as claimed in claim 1, further comprising a cover layer disposed on the gate conductive layer. The semiconductor device of claim 10, wherein the first spacer extends between the cap layer and the first portion of the surface of the substrate. The semiconductor device as claimed in claim 1, further comprising a lightly doped region partially exposed from the first portion of the surface of the substrate. The semiconductor device as claimed in claim 12, further comprising a heavily doped region disposed in the lightly doped region and partially exposed from the first portion of the surface of the substrate.