JP2006220452A - Device for evaluating electronic component - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To preclude a know-how of a using component and circuit constitution in a device for evaluating an electronic component from being leaked to a user side, in a state of generating a signal for evaluating the electronic component to evaluate an electronic component, and to prevent the electronic component from being affected by an unnecessary noise when evaluating it. <P>SOLUTION: A programmable logic circuit 42 is constituted in the first circuit board 40 to generate the signal for evaluating the electronic components PA, PB, PC etc, for the evaluation, a control circuit (design changing controller 32, memory 33 and interface 31) is constituted in the second circuit board 30 to program the programmable logic circuit 42, and the signal between the first/second circuit boards 40, 30 is connected or separated by connectors 41, 34. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an electronic component evaluation apparatus that gives an evaluation signal to an electronic component in order to evaluate the characteristics of the electronic component.

  For example, programmable logic circuits such as FPGA and CPLD can be used in a wide variety of embedded devices because a desired logic circuit and signal processing circuit can be configured by rewriting the hardware design from the outside. In addition, as an evaluation device used at the time of development by an electronic component manufacturer that manufactures an electronic component, not as a product for an end user, an electronic component evaluation device incorporating the programmable logic circuit is used.

  Conventionally, Non-Patent Document 1 is disclosed as a general-purpose electronic component evaluation apparatus using such a programmable logic circuit. A configuration example of an evaluation apparatus using a programmable logic circuit as shown in Non-Patent Document 1 is shown in FIG.

In the figure, the electronic component evaluation apparatus 10 has a programmable logic circuit 14 composed of a field programmable gate array (FPGA) or a complex programmable logic device (CPLD) incorporating a signal generation circuit, and the hardware design of the programmable logic circuit 14 is changed. A design change controller 12, a memory 13 for writing the firmware, and an interface 11 with the outside. An external personal computer 20 is connected to the interface 11. The evaluation signal output from the programmable logic circuit 14 is output to an external electronic component or device via the connector 15.
Japan Altera Corporation, “Altera Development Kit”, [online], [Search January 21, 2005], Internet <http://www.altera.co.jp/products/devkits/altera/kit-niosii- 2S30.html>

  However, since a commercially available general-purpose FPGA evaluation board as shown in Non-Patent Document 1 is expensive and its functions are limited, electronic component manufacturers generally create their own evaluation boards. there were.

  On the other hand, such an electronic component evaluation apparatus should be used not only by an electronic component manufacturer but also by an assembly manufacturer that manufactures a predetermined device by incorporating the electronic component. However, if the electronic component evaluation apparatus with the above unique design is provided to the outside, information on the parts and circuit configuration used in the apparatus becomes clear, and there is a problem in terms of maintenance of know-how.

  In addition, a general-purpose electronic component evaluation apparatus using a programmable logic circuit generates some noise from peripheral circuits provided in addition to the programmable logic circuit that generates an evaluation signal. There was another problem that it was difficult to evaluate purely.

  Therefore, an object of the present invention is to prevent information on the components used and circuit configuration of the electronic component evaluation apparatus from leaking to the user side in a state in which the electronic component evaluation signal is generated and the electronic component is evaluated. An object of the present invention is to provide an electronic component evaluation apparatus that is not adversely affected by unnecessary noise during evaluation of electronic components.

  In order to achieve the above object, an electronic component evaluation apparatus according to the present invention is configured as follows.

(1) A programmable logic circuit that generates a signal for evaluation is configured on a first circuit board,
A control circuit for programming the programmable logic circuit is configured on the second circuit board, and a detachable connector for performing signal connection or separation between the first circuit board and the second circuit board is provided.

  (2) The programmable logic circuit includes a writable memory in which stored contents are held by a power supply voltage, and is configured as a gate array that performs configuration by writing hardware design data to the memory. Is provided with a ROM in which the hardware design data is written in advance.

  (3) The programmable logic circuit in a state where a power supply system of a programmable logic circuit that generates a signal for evaluation and a control circuit that programs the programmable logic circuit is separated and power supply voltage supply to the control circuit is cut off A means for supplying a power supply voltage is provided.

  (1) A first circuit board that configures a programmable logic circuit that generates a signal for evaluation and a second circuit board that configures a control circuit that programs the programmable logic circuit are configured to be detachable via a connector. Thus, the programmable logic circuit is programmed in a state where the first and second circuit boards are connected, and then both are separated, so that only the first circuit board constituting the programmable logic circuit is used for evaluation electronics. An evaluation signal can be given to the component. As a result, information such as the components used and circuit configuration (hardware design data) contained in the second circuit board that constitutes the control circuit does not flow out to the first circuit board provider, thus maintaining know-how. Can be achieved.

  In addition, since the evaluation signal is given to the evaluation electronic component only by the first circuit board, it is not affected by the noise generated from the circuit configured on the second circuit board, and the electronic component is accurate. Evaluation is possible.

  (2) The programmable logic circuit is configured as a gate array that performs configuration by writing hardware design data to the built-in memory, and the ROM in which the hardware design data is written in advance is used to control the second circuit board. By providing on the circuit side, the hardware design data is not read in a state where the first circuit board is separated from the second circuit board, and the know-how can be maintained.

  (3) The power supply system of the programmable logic circuit that generates the signal for evaluation and the control circuit that programs the programmable logic circuit is separated, and the supply of the power supply voltage to the control circuit is cut off. Therefore, the evaluation electronic component can be accurately evaluated without being affected by noise generated by the control circuit.

The electronic component evaluation apparatus according to the first embodiment will be described with reference to FIGS.
FIG. 2 is a block diagram showing a configuration of the entire electronic component evaluation apparatus. In FIG. 2, the first circuit board 40 is provided with a programmable logic circuit 42 that generates an evaluation signal for the evaluation electronic component. The second circuit board 30 communicates with the design change controller 32 that changes (configures) the hardware design of the programmable logic circuit 42, the memory 33 in which the firmware of the design change controller 32 is written, and the outside. An interface 31 is provided. The first circuit board 40 is provided with a connector 41, and the second circuit board 30 is provided with a connector 34. The connector 41-34 allows the first circuit board 40 to be connected to the second circuit board 30. It is configured to be detachable. In this manner, signals are connected or separated between the first circuit board 40 and the second circuit board 30 by the connectors 41-34.

  The first circuit board 40 is provided with a region for mounting the two-terminal evaluation electronic components PA, PB, PC... So that signals at both ends of each evaluation electronic component can be measured with a measuring instrument. Are provided with terminals 43Ai, 43Ao, 43Bi, 43Bo. The first circuit board 40 is also provided with a power supply circuit and a clock signal generation circuit so as to operate independently while being separated from the second circuit board 30.

  The programmable logic circuit 42 is constituted by a CPLD. Therefore, in a state where the first circuit board 40 and the second circuit board 30 are connected by the connectors 41-34, the design change controller 32 writes the circuit data to the EEPROM cell in the CPLD, thereby making the hardware Design (program). After this program is completed, the first circuit board 40 is separated from the second circuit board 30 and operates independently. That is, in a state where the connectors 41-34 are separated, the programmable logic circuit 42 operates as the programmed hardware and gives an evaluation signal to the evaluation electronic components PA, PB, PC. In that state, the measuring device having the probe connected to the terminal 43 measures the voltage signal, thereby evaluating the characteristics of the electronic component for evaluation.

  The design change controller 32 provided on the second circuit board 30 reads the hardware design data from the personal computer 20 through an interface such as RS-232C, Ethernet (registered trademark), or JTAG, for example, and stores it in the internal SRAM. Configure by writing hardware design data. Further, the firmware is rewritten by writing the firmware design data read from the personal computer 20 into the memory 33 formed of a flash memory.

  3 and 4 show an example of a state in which an evaluation signal is given to the evaluation component from the programmable logic circuit 42 shown in FIG. 2 and the evaluation is performed.

  In FIG. 3A, the evaluation electronic component PA is a high-frequency filter inserted serially with respect to the signal line, and an evaluation signal is output from the output part OUT of the programmable logic circuit 42, from the terminal 43Ai. The signal before filtering and the signal after passing through the filter are measured from the terminal 43Ao.

  In FIG. 3B, the evaluation electronic component PB is an electronic component such as a noise filter inserted in parallel with the signal line, and the evaluation signal is output from the output unit OUT of the programmable logic circuit 42. The noise filter characteristic of the evaluation electronic component PB is evaluated by measuring the signal at the terminal 43Bi.

  In FIG. 4A, the evaluation electronic component PC is a noise filter inserted in parallel to the power supply line, and by measuring the signal at the terminal 43Ci while a DC power supply voltage is applied to the power supply terminal Vcc. The noise filter characteristics of the evaluation electronic component PC are evaluated.

  In FIG. 4B, the evaluation electronic component PD is a noise filter that enters the power supply line serially. In this case, the noise filter characteristic is evaluated by measuring each voltage signal of the terminals 43Di and 43Do in a state where the power supply voltage is applied to the terminal 43Do.

Next, an electronic component evaluation apparatus according to a second embodiment will be described with reference to FIG.
Differences from the configuration shown in FIG. 1 are as follows.
The programmable logic circuit 42 provided on the first circuit board 40 is composed of an FPGA.

The second circuit board 30 includes a ROM (flash memory) 35 for configuring the programmable logic circuit 42. The design change controller 32 has a function of writing hardware design data to the configuration ROM 35.
Other configurations are the same as those shown in FIG. 2 as the first embodiment.

  The operation of the electronic component evaluation apparatus shown in FIG. 5 is as follows. First, the personal computer 20 gives a command for writing the hardware design data of the programmable logic circuit 42 to the configuration ROM 35 to the design change controller 32 and sequentially transfers the hardware design data. As a result, the design change controller 32 writes the hardware design data to the configuration ROM 35. The design change controller 32 configures the programmable logic circuit 42 by writing the hardware design data once written in the configuration ROM 35 to the SRAM in the programmable logic circuit 42.

  Note that the writing of the firmware of the design change controller 32 is the same as in the first embodiment.

  When the programmable logic circuit 42 that generates the signal for evaluation is configured as an FPGA in this way, the first circuit board 40 is used for backup in order to back up the hardware design data written in the internal SRAM. It is equipped with a battery. Therefore, the programmable logic circuit 42 can operate even when separated from the second circuit board 30.

Next, an electronic component evaluation apparatus according to a third embodiment will be described with reference to FIG.
The electronic component evaluation apparatus 50 includes a programmable logic circuit 52 that gives an evaluation signal to the evaluation electronic components PA, PB, PC,..., And a design change controller that changes the hardware design of the programmable logic circuit 52. 32, a memory 33 for writing the firmware, and an interface 31 for communicating with the outside. The electronic component evaluation apparatus 50 includes a design change controller 32, a memory 33, and a control circuit 51 including an interface 31 that operates on the power supply system B. On the other hand, the evaluation signal generation circuit 53 including the programmable logic circuit 52 operates in the power supply system A. In this way, the power source is separated into the power source system A and the power source system B. Therefore, the power supply voltage supply of the power supply system A can be maintained in a state where the power supply voltage supply of the power supply system B is cut off.

  When programming the programmable logic circuit 52, both the power supply system A and the power supply system B are in a power supply voltage supply state, and the control circuit 51 programs the programmable logic circuit 52. For example, if the programmable logic circuit 52 is CPLD, the hardware design data is written. In the case of an FPGA, hardware design data is configured for an internal SRAM.

  After that, the programmable logic circuit 52 gives an evaluation signal to the evaluation electronic components PA, PB, PC,. Therefore, no noise is generated from the control circuit 51 and the control circuit 51 is not affected by the noise. Therefore, the measuring instrument connected to the terminals 43Ai, 43Ao, 43Bi, 43Bo,... Can accurately evaluate the evaluation electronic components PA, PB, PC,.

  In addition, in each embodiment shown above, although shown about the case where it applies to the electronic component for evaluation provided with two terminals, it is applicable similarly to the electronic component for evaluation more than 3 terminals.

It is a block diagram which shows the structure of the conventional apparatus for evaluation. It is a block diagram which shows the structure of the apparatus for electronic component evaluation which concerns on 1st Embodiment. It is a figure which shows the structure in the evaluation state of the electronic component for evaluation of the apparatus. It is a figure which shows the structure in the evaluation state of the electronic component for evaluation of the apparatus. It is a block diagram which shows the structure of the apparatus for electronic component evaluation which concerns on 2nd Embodiment. It is a block diagram which shows the structure of the electronic component evaluation apparatus which concerns on 3rd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,10,50-Electronic component evaluation apparatus 11-Interface 15-Connector 30-Second circuit board 40-First circuit board 34,41-Connector 43-Terminal PA, PB, PC ...- Electronic component 14, 42, 52-programmable logic circuit 51-control circuit 53-signal generation circuit for evaluation

Claims (3)

In an electronic component evaluation apparatus that gives an evaluation signal to an evaluation electronic component,
A programmable logic circuit that generates the signal for evaluation is configured on a first circuit board,
A control circuit for programming the programmable logic circuit is configured on a second circuit board, and a detachable connector for performing signal connection or separation between the first circuit board and the second circuit board is provided. An electronic component evaluation device.   The programmable logic circuit includes a writable memory in which stored contents are held by a power supply voltage, and is a gate array that performs configuration by writing hardware design data to the memory. The electronic component evaluation apparatus according to claim 1, further comprising a ROM in which the hardware design data is written in advance. In an electronic component evaluation apparatus that gives an evaluation signal to an evaluation electronic component,
The power supply system of the programmable logic circuit that generates the signal for evaluation and the control circuit that programs the programmable logic circuit is separated, and the supply of the power supply voltage to the control circuit is cut off with respect to the programmable logic circuit An apparatus for evaluating an electronic component, characterized in that means for supplying a power supply voltage is provided.

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