CN100444123C - An interface test response equipment - Google Patents
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- CN100444123C CN100444123C CNB2004101029770A CN200410102977A CN100444123C CN 100444123 C CN100444123 C CN 100444123C CN B2004101029770 A CNB2004101029770 A CN B2004101029770A CN 200410102977 A CN200410102977 A CN 200410102977A CN 100444123 C CN100444123 C CN 100444123C
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Abstract
The present invention relates to interface test response equipment which comprises various block structures with limited numbers, wherein each block structure stores a fixed form, and is provided with a variable data part. Then, the block structures are instantiate to form an instantiation block. The output signals of the instantiation block are outputted to a bus at different time by a control device to form the response signals of the test response equipment. The present invention has the advantages that the interface test response equipment can reduce the buying cost of interface equipment, and saves time. Meanwhile, the present invention can conveniently generate abnormal response signals, and is used for testing the abnormal state of an interface module.
Description
Technical field
The present invention relates to a kind of interface test response equipment, relate in particular to a kind of interface test response equipment of the working method based on ROM.
Background technology
Digit chip or digital circuit often comprise a variety of interfaces, and the design of these interfaces is often very complicated.Interface comprises processing module, time-sequence control module of analysis and processing module, the output signal of the register module that links to each other with controller and input signal or the like at least.The collaborative work of these modules has realized the function of interface, and under the effect of controller, the interfacing equipment of interface and chip exterior can be communicated by letter, and realizes the mutual of data and control signal.
For the function of checking interface whether correct, comprehensively test, the interface of standard is often by the definition of the standardization body of the world, so the present invention can obtain the normalized illustration of these interfaces, that is to say that the interface of the present invention's design will meet these standards.The test of docking port is also carried out according to these standards.For example, whether interface sequence satisfies, and correctly whether the various command of input response, and whether the data of input can correctly be received or the like.The order of an interface definition, data, response format often have multiple, and order, the combination of data, response is just more.On the other hand, the present invention also wants test interface can return to form under error status.For example in the interface specification of SD card, defined the order more than 120 kinds, 6 kinds of responses and the data packet format more than 10 kinds are arranged, if test such interface, the order that may occur, response, data layout just all will be tested.In the process of test interface, interface need be linked to each other with corresponding apparatus, equipment of the present invention meets interface specification and can provide correct response to correct input, and can whether the present invention just can meet the operation of interface specification by test interface, and the response of the equipment that receives that correct.
In known solution, test an interface if desired, just go to buy on the market corresponding apparatus, for example need to debug the SPI interface, just purchase has EEPROM, single-chip microcomputer or the processor of SPI interface, just needs to buy corresponding USB interface equipment and debug USB interface if desired.These equipment are more complicated often, some in addition relatively more expensive, and after having bought, to write the corresponding driving program and could work.Some equipment may be because temporarily out of stock and can't obtain immediately on market on the other hand.Generally speaking, the design time of digit chip or digital circuit is limited, and existing solution has extended the design cycle inevitably, has influenced the Time To Market of product.
From the method for designing of interface module as can be seen, the test of an interface module mainly contains two aspects, and an aspect is interface module transmission operation under normal operation, is the response under error situation on the other hand.This just needs interfacing equipment to possess response under the normal operating conditions, also wants to be given in the response under the abnormal operation simultaneously.And for the equipment of a standard, as SPI storer or USB device, allowing their produce exception response is very difficult with the operation of the interface module of test the present invention design, because produce the bad control of exception response itself, even under some specific situation, can't make standard device produce exception response, otherwise can cause the irreversible damage of standard device at all.
Summary of the invention
The problem to be solved in the present invention is exactly, and designs a kind of interface test response equipment, and by the mode that the user is provided with, this test response equipment can provide the response signal that needs, i.e. response under the normal operating conditions and exception response is used for the debugging of interface module.Simultaneously, the user can allow this test response equipment change into another interfacing equipment of adaptation from being suitable for a kind of interfacing equipment through simple configuration.
According to the present invention proposes a kind of interface test response equipment, the multiple block structure that contains limited number, every kind of block structure all stores set form, and has variable data division, block structure is carried out instantiation, to form sample module, interface test response equipment also comprises control device, the output signal of sample module by control device on the bus that the different moment outputs to interface test response equipment is connected, form the response signal of test response equipment, the process that wherein generates sample module is, to each part of block structured, according to the signal that will produce, determine the process of concrete numerical value.
In addition, device of the present invention also has some following improvement:
Each block structure all has a length.
Block structure is made of a plurality of parts with different implications.
Contain a kind of command block structure, described command block structure has command header, command number, command parameter and check word.
The present invention also provides a kind of response method of interface testing in addition, disposes the multiple block structure of limited number, makes all to store set form in every kind of block structure, and all have variable data structure in each block structure; Block structure is carried out instantiation and handles to obtain sample module, the output signal of sample module is outputed on the bus in the different moment by control device, these output signals make up on output bus, to form the signal of response interface test, wherein block structure is carried out instantiation and handles and to comprise to obtain sample module, to each part of block structured,, thereby determine that concrete numerical value realizes the process of sample module according to the signal that will produce.
Response method of the present invention also has following improvement:
Each block structure all has a length.
Constitute block structure by a plurality of parts with different implications.
Contain a kind of command block structure, described command block structure has command header, command number, command parameter and check word.
The content of piece instantiation is to determine as required, can just can produce the signal that makes that interface is made mistakes so that the piece instantiation does not meet the standard of interface as required.
By block structured configuration, test different buses and only need revise block structured and define and realize.
Described bus is spi bus, Sd bus or I2C bus.
Theory diagram of the present invention is seen Fig. 2, and block structured length defined by the user then obtains several piece examples in the mode of filling in a form, and under the control of the counter of time control, different piece examples outputed on the data bus in the different time.Because block structure is user-defined, for bus signals not of the same race, the present invention can define different block structures, and the present invention just can realize the not test of bus of the same race by configuration.
Core of the present invention considers, any one equipment that is used to test can be simplified to one being input as the response apparatus of independent variable, and different bus apparatus is different aspect the form (comprising length and data content) of response signal.By introducing the block structured mode, what make that the user faces is to the configuration of block structure and piece example, that is to say, by the modification of block structure and piece example, can produce the waveform that any hope obtains on bus.Like this, expect in the present invention under the situation of output signal, the output of fixing can be exported to interface module in the specific time.
Because always bus signals can be generalized into limited multiple block structure, so-called block structure, exactly the data structure that defines, the block structured parameter has: the content of length, each part representative of block structured.Wherein length is represented with the position number usually, and the implication difference that each part of block structured may be represented.
For example the CMD of SD bus (order) just can be defined as a kind of block structure, and its length is 48 positions, and Fig. 6 is the inner definition of CMD block structured, is used for representing that every kind of block structure all stores set form, also comprises variable data division certainly.The present invention has preset multiple block structure for user definition, and the user can define different block structures according to the difference of equipment, comprises the basic format of variable part in the set form of length, piece of piece and the piece.
The present invention handles by block structure being carried out instantiation, and every kind of piece is carried out instantiation according to the vector that will test, obtains the piece instantiation.For example above-mentioned SD card CMD block structure can define several following instantiations, realizes CMD3 and CMD10.
0-1-03(3)-ffffffff-0000101-1
0-1-0a(10)-0002ffff-0110110-1
User's work is exactly according to the CMD that will test, and defines different piece instantiations, for example wants to realize CMD3 and CMD10, has just defined two kinds of piece instantiations of front.These sample modules were outputed on the output bus in the different moment, and this just needs a timer units to come the generation time output signal, and the digit of this timer units is the minimum time section of test response equipment output, is a clk cycle.
According to the output of timer units, the multiselect switch is delivered to the output of different sample modules on the output bus, is used for the output of emulation bus.
For example CMD3 need be sent, CMD10 need be sent, just CMD3 and CMD10 be delivered on the output bus at the 100th and the 300th rising edge clock at the 300th rising edge clock at the 100th rising edge clock.
The user just defines block structured length and content by the configuration block structure, structure that can the definition bus signal.That is to say that the present invention can adapt to the needs of multiple Bus simulator by simple configuration.
The user passes through the content of configuration block example, and outputs on the bus timing waveform of emulation bus signal according to the value of timer.Compare with the testing apparatus of reality, use this test response equipment to reduce workload and design cycle greatly.
Because the content of configuration block example easily, the user can provide the output of bus signals in abnormality easily.
For example, wish that test SD is stuck in the state that CRC (CRC) verification of a CMD makes mistakes and whether can responds, just define a following piece example:
0-1-0a(10)-0002ffff-1111111-1
Benefit of the present invention is reduce to buy the expense of interfacing equipment, save time, and can produce the exception response signal easily simultaneously, is used for the test of interface module abnormality.
Accompanying drawing is described
Can be well understood to content of the present invention more by detailed description of the present invention in conjunction with the accompanying drawings.
Fig. 1 is a kind of structural drawing of traditional ROM (read-only memory);
Fig. 2 is the structure principle chart according to equipment of the present invention;
Fig. 3 reads timing waveform to the SPI interface of a master mode;
Fig. 4 is the oscillogram of SPI test reading signal;
Fig. 5 is the basic composition block diagram of an interface;
Fig. 6 is the inner definition of CMD block structured;
Fig. 7 is the operating process of steering logic of the present invention;
Fig. 8 A-F shows circuit structure of the present invention.
Concrete form of implementation
As shown in Figure 1, the ROM in the title of the present invention (Read Only Memory) is the abbreviation of ROM (read-only memory), the principal character of ROM be its output only depend on input read address and read control signal, and can not carry out rewriting operation to its content.Wherein CS is a chip selection signal, and RD is a read signal, and ADDR is an address signal, and DATA is the data-signal of output, and when the CS signal was effective, address signal had determined the value of output signal DATA.
The example of realizing a SPI (serial data interface) equipment below by the present invention describes embodiments of the present invention in detail.Fig. 5 shows the common version of interface.The SPI interface is a kind of serial line interface, and interface signal is defined as:
Pin title SPI function
The input of TDI serial data
The output of TDO serial data
TCK clock (TDI data latching rising edge)
The C-S chip is selected (the SPI transmission enables)
Fig. 3 shows the SPI interface of a master mode is read timing waveform.From the waveform of front as can be seen, the SPI interface can represent that so in external interface signals of the present invention A1 is defined as CS, A2 is defined as SCLK with 3 signal line, and A3 is defined as the SO signal.With the token_start conditional definition be the CS signal by high step-down, whenever the CS signal is uprised by low, token_counter adds 1.The conditional definition of token_end is that the CS signal is uprised by low, and then along with each rising edge of SCK, the present invention can deliver to the data of a position on the SO, and process_counter adds 1.
Shown in the waveform of following Fig. 4, if the SPI interface is wanted the correctness of test reading signal, need do a read operation, then 7 deposit data in to the address: 0 * 00 0 * ff0 * 00 0 * ff 0 * 00 0 * ff 0 * 00 0 * ff in the address 0 of EEPROM, a read operation that just can be achieved as follows, the data of reading are 01010101.
Fig. 7 shows steering logic of the present invention inside and comprises two registers, be mark (token) counter and output register, wherein the blip counting device is used for the order number that record interface sends, or the number of significant mark, for example order beginning, reply and begin etc., the present invention is with blip counting device called after token_counter. and output counter is subjected to the control of blip counting device and clk, be used for writing down a process that mark carried out, this counter produces the address signal of ROM, drive the specific waveform signal of ROM output, with process counter called after process_counter.
The course of work of steering logic is as follows:
1. electrification reset, token_counter=0, process_counter=0.
User definition the condition of mark triggers, wait for that the mark triggers condition satisfies, then token_counter adds 1.The while token_start effective clock period of signal.Wait the condition of end to be marked to satisfy simultaneously, send out a token_end signal.
3.token_start signal effectively after, process_counter begins each clock period and adds 1.Till the token_end signal effectively.Because each clock period of process_counter all changes, the output of ROM also each clock period all change, the signal on the bus of the present invention just changes along with the output of ROM, the response signal waveform of needs of generation.
4. repeat 2,3.
5. finish.
The present invention can circuit form realize that on a printed circuit board as shown in Figure 8, what circuit was realized is described below.In circuit is realized, comprise following components:
1. power supply is worked under 5V owing to circuit form of the present invention, consider the condition of laboratory applications, adopt the outside mode that the 9V DC voltage is provided, this 9V DC voltage realizes with D.C. regulated power supply (TD3310) commonly used, adopts 1 LM2940-5.0 to obtain stable 5V DC voltage output on the circuit board.
2.CLK stay the socket of a DIP crystal oscillator on the circuit board, can select the crystal oscillator of different frequency to be inserted on this socket flexibly, provide CLK signal to circuit board, acquiescence is plugged the crystal oscillator that a slice frequency is 2MHz on the plate.
3. the input and output of filtering LM2940 two electric capacity of respectively burn-oning, capacitance is respectively 1 μ and 0.1 μ, all will add the filter capacitor of one 0.1 μ simultaneously between the power supply of each logic chip and the ground.
4. reset circuit is formed an electrify restoration circuit with the electric capacity of a 100K and the electric capacity of one 100 μ, after system powers on, provides the reset pulse of a high level.
5. signaling interface is because the present invention will adapt to the needs of different interface signals, so need to stay some signaling interfaces more, be to adopt the 50 double contact pins that are spaced apart 2.54mm on circuit board, external interface is plugged this connector and has just been realized linking to each other of signal, and these 100 interface lines are defined as A[1:100].
6.Jtag interface need stay a jtag interface that links to each other with the PC printer interface to be used for program and download owing on the plate CPLD is arranged.The Jtag interface has general connected mode.
Adopt 68 EEPROM 7.ROM module is used to store the ROM module of test vector, model is 2164, and its capacity is 512KB, the disposable like this test vector that can store 512 clock period.
8. the timer of control module inside, logic control realize that with the CPLD chip of a slice Xilinx company its model is XC95288, and the modification of logic of the present invention just can realize by the mode of upgrading internal netlist.The power supply of XC95288, CLK, RESET pin are wanted to link to each other with previously described power supply, CLK, RESET.XC95288 has 100 pins to link to each other with outside connector simultaneously.
9.CPLD this part code of hardware description program controlled the course of work of circuit.The data of specimen, these data produce in advance with the form of 16 systems, download in the eeprom chip then.
Claims (11)
1. interface test response equipment, it is characterized in that, the multiple block structure that contains limited number, every kind of block structure all stores set form, and has variable data division, block structure is carried out instantiation, to form sample module, interface test response equipment also comprises control device, and the output signal of sample module on the bus that the different moment outputs to interface test response equipment is connected, forms the response signal of test response equipment by control device, the process that wherein generates sample module is, to each part of block structured,, determine the process of concrete numerical value according to the signal that will produce.
2. response apparatus as claimed in claim 1 is characterized in that each block structure all has a data length.
3. response apparatus as claimed in claim 1 is characterized in that, block structure is made of a plurality of data divisions with different implications.
4. response apparatus as claimed in claim 1 is characterized in that, contains a kind of command block structure, and described command block structure has command header, command number, command parameter and check word.
5. the response method of an interface testing is characterized in that,
Dispose the multiple block structure of limited number, make all to store set form in every kind of block structure, and in each block structure, all have variable data structure;
Block structure is carried out instantiation and handles obtaining sample module, and the output signal of sample module is outputed on the bus in the different moment by control device, and these output signals make up on output bus, forming the signal of response interface test,
Wherein block structure is carried out instantiation and handles and to comprise to obtain sample module, to each part of block structured, according to the signal that will produce, thereby determines that concrete numerical value realizes the process of sample module.
6. response method as claimed in claim 5 is characterized in that each block structure all has a length.
7. response method as claimed in claim 5 is characterized in that, constitutes block structure by a plurality of parts with different implications.
8. response method as claimed in claim 5 is characterized in that, contains a kind of command block structure, and described command block structure has command header, command number, command parameter and check word.
9. response method as claimed in claim 5 is characterized in that, the content of piece instantiation is to determine as required, can just can produce the signal that makes that interface is made mistakes so that the piece instantiation does not meet the standard of interface as required.
10. response method as claimed in claim 5 is characterized in that, by block structured configuration, test different buses and only need revise block structured and define and realize.
11. response method as claimed in claim 10 is characterized in that, described bus is spi bus, Sd bus or I2C bus.
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| CNB2004101029770A CN100444123C (en) | 2004-12-31 | 2004-12-31 | An interface test response equipment |
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| CNB2004101029770A CN100444123C (en) | 2004-12-31 | 2004-12-31 | An interface test response equipment |
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| CN1632758A CN1632758A (en) | 2005-06-29 |
| CN100444123C true CN100444123C (en) | 2008-12-17 |
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| CN102103536B (en) * | 2009-12-18 | 2015-04-15 | 安徽冠东电子科技有限公司 | Board test device and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1311477A (en) * | 2000-03-03 | 2001-09-05 | 英业达股份有限公司 | Method and its device for display BIOS error code |
| US20040088604A1 (en) * | 2002-10-30 | 2004-05-06 | International Business Machines Corporation | Methods and arrangements to enhance a bus |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1311477A (en) * | 2000-03-03 | 2001-09-05 | 英业达股份有限公司 | Method and its device for display BIOS error code |
| US20040088604A1 (en) * | 2002-10-30 | 2004-05-06 | International Business Machines Corporation | Methods and arrangements to enhance a bus |
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