CN2869989Y - Interface detection corresponding apparatus - Google Patents
Interface detection corresponding apparatus Download PDFInfo
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- CN2869989Y CN2869989Y CN 200420122253 CN200420122253U CN2869989Y CN 2869989 Y CN2869989 Y CN 2869989Y CN 200420122253 CN200420122253 CN 200420122253 CN 200420122253 U CN200420122253 U CN 200420122253U CN 2869989 Y CN2869989 Y CN 2869989Y
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Abstract
This utility model relates to a response device for interface tests, which comprises limited number of block architecture in a plurality of varieties. Each variety of block architecture stores fixed format and has variable data section. Perform instantiation of the block architecture to form instantiated blocks. The output signals of the instantiated blocks are loaded to different time output buses via control to form the response signal of the response device for tests. This utility model has the advantages that the cost for purchasing the interface device is reduced, time saved, and abnormal response signal easily generated for the test of the abnormal state of the interface module.
Description
Technical field
The utility model relates to a kind of interface test response equipment, relates in particular to a kind of interface test response equipment of the working method based on ROM.
Background technology
Digit chip or digital circuit often comprise a variety of interfaces, and the design of these interfaces is often very complicated.Interface comprises processing module, time-sequence control module of analysis and processing module, the output signal of the register module that links to each other with controller and input signal or the like at least.The collaborative work of these modules has realized the function of interface, and under the effect of controller, the interfacing equipment of interface and chip exterior can be communicated by letter, and realizes the mutual of data and control signal.
For the function of checking interface whether correct, comprehensively test, the interface of standard is often by the definition of the standardization body of the world, so the utility model can obtain the normalized illustration of these interfaces, that is to say that the interface of the utility model design will meet these standards.The test of docking port is also carried out according to these standards.For example, whether interface sequence satisfies, and correctly whether the various command of input response, and whether the data of input can correctly be received or the like.The order of an interface definition, data, response format often have multiple, and order, the combination of data, response is just more.On the other hand, the utility model also wants test interface can return to form under error status.For example in the interface specification of SD card, defined 120 kinds with last order, 6 kinds of responses and the data packet format more than 10 kinds are arranged, if test such interface, the order that may occur, response, data layout just all will be tested.In the process of test interface, interface need be linked to each other with corresponding apparatus, equipment of the present utility model meets interface specification and can provide correct response to correct input, can whether the utility model just can meet the operation of interface specification by test interface, and the response of the equipment that receives that correct.
In known solution, test an interface if desired, just go to buy on the market corresponding apparatus, for example need to debug the SPI interface, just buy EEPROM, single-chip microcomputer or processor with SPI interface.Just need to buy corresponding USB interface equipment and debug USB interface if desired.These equipment are more complicated often, some in addition relatively more expensive, and after having bought, to write the corresponding driving program and could work.Some equipment may can't obtain immediately because of temporary transient short supply on market on the other hand.Generally speaking, the design time of digit chip or digital circuit is limited, and existing solution has extended the design cycle inevitably, has influenced the Time To Market of product.
From the method for designing of interface module as can be seen, the test of an interface module mainly contains two aspects, and an aspect is the transmission operation under normal operation of interface module, is the response under error situation on the other hand.This just needs interfacing equipment to possess response under the normal operating conditions, also wants to be given in the response under the abnormal operation simultaneously.And for the equipment of a standard, as SPI storer or USB device, allowing their produce exception response is very difficult with the operation of the interface module of test the utility model design, because produce the bad control of exception response itself, even under some specific situation, can't produce exception response by making standard device, otherwise can cause the irreversible damage of standard device at all.
Summary of the invention
Problem to be solved in the utility model is exactly, design a kind of interface test response equipment, by the mode that the user is provided with, this test relevant device can provide the response signal that needs, be response and the exception response under the normal operating conditions, be used for the debugging of interface module.Simultaneously, the user can allow this test response equipment change into another interfacing equipment of adaptation from being suitable for a kind of interfacing equipment through simple configuration.
According to the utility model proposes a kind of interface test response equipment, the multiple block structure that contains limited number, every kind of block structure all stores set form, and has variable data division, described block structure is carried out instantiation, to form sample module, the output signal of sample module outputs on the bus in the different moment by control device, forms the response signal of test response equipment.
In addition, device of the present utility model also has some following improvement:
Block structure is made of a plurality of parts with different implications.
Contain a kind of command block structure, described command block structure has command header, command number, command parameter and check word.
According to the signal that will produce, each part of described sample module all has concrete numerical value separately.
Theory diagram of the present utility model is seen Fig. 2, and block structured length defined by the user obtains several piece examples in the mode of filling in a form thereafter, and under the control of the counter of time control, different piece examples outputed on the data bus in the different time.Because block structure is user-defined, for bus signals not of the same race, the utility model can define different block structures, and the utility model just can be realized the not test of bus of the same race by configuration.
Core of the present utility model considers, any one equipment that is used to test can be simplified to one being input as the response apparatus of independent variable, and different bus apparatus is different aspect the form (comprising length and data content) of response signal.By introducing the block structured mode, what make that the user faces is to the configuration of block structure and piece example, that is to say, by the modification of block structure and piece example, can produce the waveform that any hope obtains on bus.Expect under the situation of output signal at the utility model like this, the output of fixing can be exported to interface module in the specific time.
Because always bus signals can be generalized into limited multiple block structure, so-called block structure, exactly the data structure that defines, the block structured parameter has: the content of length, each part representative of block structured.Wherein length is represented with the position number usually, and the implication difference that each part of block structured may be represented.
For example the CMD of SD bus (order) just can be defined as a kind of block structure, and its length is 48 positions, and Fig. 6 is the inner definition of CMD block structured, is used for representing that every kind of block structure all stores set form, also comprises variable data division certainly.The utility model has been preset multiple block structure for user definition, and the user can define different block structures according to the difference of equipment, comprises the length of piece, the set form of piece, and the basic format of variable part in the piece.
The utility model is handled by block structure being carried out instantiation, and every kind of piece is carried out instantiation according to the vector that will test, obtains the piece instantiation.For example above-mentioned SD card CMD block structure can define several following instantiations, realizes CMD3 and CMD10.
0-1-03(3)-ffffffff-0000101-1
0-1-0a(10)-0002ffff-0110110-1
User's work is exactly according to the CMD that will test, and defines different piece instantiations, for example wants to realize CMD3 and CMD10, has just defined two kinds of piece instantiations of front.These sample modules were outputed on the output bus in the different moment, and this just needs a timer units to come the generation time output signal, and the digit of this timer units is doing minor time slice of test response equipment output, is a clk cycle.
According to the output of timer units, the multiselect switch is delivered to the output of different sample modules on the output bus, is used for the output of emulation bus.
For example CMD3 need be sent, CMD10 need be sent, just CMD3 and CMD10 be delivered on the output bus at 100 and 300 rising edge clock at the 300th rising edge clock at the 100th rising edge clock.
The user just defines block structured length and content by the configuration block structure, can define the structure of bus signals.That is to say that the utility model can adapt to the needs of multiple Bus simulator by simple configuration.
The user passes through the content of configuration block example, and outputs on the bus timing waveform of emulation bus signal according to the value of timer.Compare with the testing apparatus of reality, use this test response equipment to reduce workload and design cycle greatly.
Because the content of configuration block example easily, the user can provide the output of bus signals in abnormality easily.
For example, wish that test SD is stuck in the state that CRC (CRC) verification of a CMD makes mistakes whether can be corresponding, just define a following piece example:
0-1-0a(10)-0002ffff-1111111-1
Benefit of the present utility model is reduce to buy the expense of interfacing equipment, save time, and can produce the exception response signal easily simultaneously, is used for the test of interface module abnormality.
Accompanying drawing is described
In conjunction with the accompanying drawings by being well understood to content of the present utility model more to detailed description of the present utility model.
Fig. 1 is a kind of structural drawing of traditional ROM (read-only memory);
Fig. 2 is the structure principle chart according to the utility model equipment;
Fig. 3 reads timing waveform to the SPI interface of a master mode;
Fig. 4 is the oscillogram of SPI test reading signal;
Fig. 5 is the basic composition block diagram of an interface;
Fig. 6 is the inner definition of CMD block structured;
Fig. 7 is the operating process of steering logic of the present utility model;
Fig. 8 shows circuit structure of the present utility model.
Concrete form of implementation
As shown in Figure 1, the ROM in the utility model title (Read Only Memory) is the abbreviation of ROM (read-only memory), the principal character of ROM be its output only depend on input read address and read control signal, and can not carry out rewriting operation to its content.Wherein CS is a chip selection signal, and RD is a read signal, and ADDR is an address signal, and DATA is the data-signal of output, and when the CS signal was effective, address signal had determined the value of output signal DATA.
The example of realizing a SPI (serial data interface) equipment below by the utility model describes embodiment of the present utility model in detail.Fig. 5 shows the common version of interface.The SPI interface is a kind of serial line interface, and interface signal is defined as
Pin title SPI function
The input of TDI serial data
The output of TDO serial data
TCK clock (the TDI data latching is at rising edge)
C ~ S chip is selected (the SPI transmission enables)
Fig. 3 shows the SPI interface of a master mode is read timing waveform.From the waveform of front as can be seen, the SPI interface can represent that so definition A1 is defined as CS in external interface signals of the present utility model, A1 is defined as SCLK with 3 signal line, and A3 is defined as the S0 signal.With the token_start conditional definition be the CS signal by high step-down, whenever the CS signal is uprised by low, token_counter adds 1.The conditional definition of token_end is that the CS signal is uprised by low, and then along with each rising edge of SCK, the utility model can be delivered to the data of a position above the S0, and process_counter adds 1.
Shown in the waveform of following Fig. 4, if the SPI interface is wanted the correctness of test reading signal, need do a read operation, then 7 deposit data in to the address: 0x00 0xff 0x000xff 0x00 0xff 0x00 0xff in the address 0 of EEPROM, a read operation that just can be achieved as follows, the data of reading are 01010101.
Fig. 7 shows steering logic of the present utility model inside and comprises two registers, be mark (token) counter and output register, wherein the blip counting device is used for the order number that record interface sends, or the number of significant mark, for example order beginning, reply and begin etc., the utility model is with blip counting device called after token_counter. and output counter is subjected to the control of blip counting device and clk, be used for writing down a process that mark carried out, this counter produces the address signal of ROM, drive the specific waveform signal of ROM output, with process counter called after process_counter.
The course of work of steering logic is as follows
1. electrification reset, token_counter=0, process_counter=0.
User definition the condition of mark triggers, wait for that the mark triggers condition satisfies, then token_counter adds 1.The while token_start effective clock period of signal.Wait the condition of end to be marked to satisfy simultaneously, send out a token_end signal.
3.Token_start signal effectively after, process_counter begins each clock period and adds 1.Till the token_end signal effectively.Because each clock period of process_counter all changes, the output of ROM also each clock period all change, the signal on the bus of the present utility model just changes along with the output of ROM, the response signal waveform of needs of generation.
4. repeat 2,3
5. finish.
The utility model can circuit form realize that on a printed circuit board as shown in Figure 8, what circuit was realized is described below.In circuit is realized, comprise following components:
1. power supply is worked below 5V owing to circuit form of the present utility model, consider the condition of laboratory applications, adopt the outside mode that the 9V DC voltage is provided, this 9V DC voltage realizes with D.C. regulated power supply (TD3310) commonly used, adopts 1 LM2940-5.0 to obtain stable 5V DC voltage output on the circuit board.
2.CLK stay the socket of a DIP crystal oscillator on the circuit board, can select the crystal oscillator of different frequency to be inserted on this socket flexibly, provide CLK signal to circuit board, acquiescence is plugged the crystal oscillator that a slice frequency is 2MHz on the plate.
3. the input and output of filtering LM2940 two electric capacity of respectively burn-oning, capacitance is 1u and 0.1u, all will add the filter capacitor of a 0.1u simultaneously between the power supply of each logic chip and the ground.
4. reset circuit is formed an electrify restoration circuit with the electric capacity of a 100K and the electric capacity of a 100u, after system powers on, provides the reset pulse of a high level.
5. signaling interface is because the utility model will adapt to the needs of different interface signals, so need to stay some signals more, be to adopt the 50 Shuangpai County's contact pins that are spaced apart 2.54mm on circuit board, external interface is plugged this connector and has just been realized linking to each other of signal, these 100 interface lines is defined as A[1: 100].
6.Jtag interface need stay a jtag interface that links to each other with the PC printer interface to be used for program and download owing on the plate CPLD is arranged.The Jtag interface has general connected mode.
Adopt 68 EEPROM 7.ROM module is used to store the ROM module of test vector, model is 2164, and its capacity is 512KB, the disposable like this test vector that can store 512 clock period.
8. the timer of control module inside, logic control realize that with the CPLD chip of a slice Xilinx company its model is XC95188, and the modification of the utility model logic just can realize by the mode of upgrading internal netlist.The power supply of XC95288, CLK, RESET pin are wanted to link to each other with previously described power supply, CLK, RESET.XC95288 has 100 pins to link to each other with outside connector simultaneously.
9.CPLD the hardware description program, the code of this part has been controlled the course of work of circuit.The data of specimen, these data produce in advance with the form of 16 systems, download to then in the EEPEOM chip.
Claims (1)
1. interface test response equipment, it is characterized in that, the multiple block structure that contains limited number, every kind of block structure all stores set form, and have variable data division, described block structure is carried out instantiation, to form sample module, the output signal of sample module outputs on the bus in the different moment by control device, forms the response signal of test response equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420122253 CN2869989Y (en) | 2004-12-31 | 2004-12-31 | Interface detection corresponding apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420122253 CN2869989Y (en) | 2004-12-31 | 2004-12-31 | Interface detection corresponding apparatus |
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| Publication Number | Publication Date |
|---|---|
| CN2869989Y true CN2869989Y (en) | 2007-02-14 |
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| CN 200420122253 Expired - Fee Related CN2869989Y (en) | 2004-12-31 | 2004-12-31 | Interface detection corresponding apparatus |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105635814A (en) * | 2015-12-31 | 2016-06-01 | 深圳市九洲电器有限公司 | Detection method and device of TS signal port |
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2004
- 2004-12-31 CN CN 200420122253 patent/CN2869989Y/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105635814A (en) * | 2015-12-31 | 2016-06-01 | 深圳市九洲电器有限公司 | Detection method and device of TS signal port |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070214 Termination date: 20111231 |