JP2009031933A - Scalable reconfigurable prototype system and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a system and a method for use in the design and emulation of user design via a reconfigurable platform. <P>SOLUTION: A system and a method are provided for use in the design and emulation of user designs via a reconfigurable platform. The system and the method enable user design of a system-on-chip type to be designed and emulated more easily. A netlist in the user design uses a platform including a plurality of field programmable gate array devices and can be included in a netlist of customized or optimized third-party circuits. Various customized circuits are configured to interact with the user design to provide functions such as debugging, performance analysis, connection to a simulator, etc. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to circuit design automation and validation techniques, and in particular, the present invention relates to system on-chip (SoC) circuit design automation and validation techniques.

  With increasing integration, many complex logic systems are currently implemented on a single integrated circuit. Such an integrated circuit is called a system on chip (SoC). The SoC generally includes several complex units such as a microprocessor, peripheral equipment, and a memory controller. Many SoCs employ existing circuit designs from several other manufacturers, and these circuit designs are referred to in the industry as “IP cores”.

  In current technology, it is very difficult to debug into a system that integrates one or more third party IP cores, including user designs, which is often the user interface between user designs and IP cores. This is because the timing and logic operation of the IP core cannot be completely controlled via the network. For example, an incorrect output signal of the user design causes an unexpected operation in the IP core, and the operation of the IP core is fed back to the user design to make the user design in an unpredictable state. Such errors are extremely difficult to diagnose and position. For this reason, there is a need for a design tool that allows the designer to control the interface between the user design and the IP core.

  It is an object of the present invention to provide a system and method for use in user design design and emulation via a reconfigurable platform.

  The method of the present invention is particularly applicable to IP-based design methodology, for example, a user design self-designed by a user and a SoC type design capable of executing a third party IP core. The present invention can be implemented on a platform composed of a memory and a certain number of field programmable logic devices. The field programmable logic device herein can be a programmable gate array. Various customized circuits can be configured to interact with the user design to provide functions such as debugging, performance analysis, and simulator connection.

  In a specific embodiment of the present invention, a system used for designing and emulating a user design includes (1) a system controller having an interface connected to a user workstation and a data communication interface, and (2) the data communication. Including a simulated platform connected to an interface, wherein the simulated platform includes a plurality of field programmable logic devices and memory devices and is used to implement a user design and a third party IP core, the platform further connected to a target system Interface that interacts with the user design at runtime. The data communication interface includes a set of configuration buses, a set of system access buses, and a set of clock buses. The interface connected to the target system includes signals from the input / output ports of a set of programmable devices.

  In accordance with a specific embodiment of the present invention, using the system used for user design design and emulation, the user generates a top-level module that includes the user design and one or more third-party IP cores. The user can then integrate the user design. The user design and the third party IP core are reasonably partitioned into multiple blocks, each block being implemented with one or more programmable logic devices. In addition, each programmable logic device and each IP core are all assigned one interface module. Any of the blocks in any one of the same programmable logic devices to the IP core implemented in any of the programmable logic devices via the interface module, or in any of the other programmable logic devices You can also communicate with the block. These blocks and interface modules are later wired and physically implemented in the programmable logic device.

  In accordance with a specific embodiment of the present invention, the interface module allocated within each IP core or each programmable logic device includes a control circuit and a set of variable quantity input / output units, each unit comprising: Provides a 1-bit interconnect port. In the embodiment, each input / output unit includes a dynamically reconfigurable memory module, a multipath selector for selecting an output signal to be output to a 1-bit interconnection port, and a certain number of latches. Can selectively capture signals received from a 1-bit interconnect port. The multi-pass selector and the latch can be controlled by numerical values stored in the memory of the dynamically reconfigurable memory module. The dynamically reconfigurable memory module may be composed of one or more dynamically reconfigurable memory units and accesses an address generated by a state machine (eg, a counter). A dynamically reconfigurable memory module can be operated using a clock that is higher than the clock frequency normally used in the user design.

  The interface module can be used to implement an output port, an input port, a bidirectional port, or a three-state port. Also, the type of port implemented in the interface module can be dynamically changed. Based on a definitive test or debug situation (such as during a boundary scan operation), the interface module may isolate an IP core in one programmable logic device from another in the same or different programmable logic device. It can also be configured and used.

  In accordance with a specific embodiment of the present invention, one or more programmable logic devices can be assigned to a verification IP core and used for functional verification of a user circuit. For example, such a verification IP core can include industry standard bus simulation operations.

  In accordance with another specific embodiment of the present invention, one or more programmable logic devices can be assigned to a performance analysis IP core. For example, the performance analysis IP core can include an IP core used to analyze bus bandwidth.

  In accordance with a specific embodiment of the present invention, the system provides a configuration tool for use in dynamic reconfiguration of logic circuits in selected programmable logic devices. The configuration tool may include a backplane configuration tool used to dynamically reconfigure a bus on a circuit board with a plurality of programmable logic devices.

  In accordance with a specific embodiment of the present invention, the system provides a system debug tool that monitors and measures signals between multiple programmable logic devices as they progress. The system debug tools may include an FPGA (Field Programmable Gate Array) readback tool, a system access bus operation tool, an internal logic analyzer tool, a bandwidth analysis tool, a code / event extraction tool, and a simulator connection tool. . The internal logic analyzer tool inserts a logic analyzer circuit in one or more programmable logic devices. The code / event extraction tool can associate one or more signals with a user, set one code name, or set one event composed of multiple signals. One event can be set by a set of signal waveforms within a certain period of time. The debug tool can detect the occurrence of an event and report it to the user in a code name manner. The simulator connection tool allows the user to interact with a simulation program executed on the user workstation and jointly construct a software / hardware co-verification environment.

  The system and method of the present invention allows system on chip type user designs to be designed and emulated more easily. Netlists in user designs can be included in customized or optimized third-party circuit netlists using platforms that include multiple field programmable gate array devices, and can be customized The circuit can be configured by interacting with the user design, and functions such as debugging, performance analysis, and simulator connection can be provided.

  FIG. 1 shows an electrically reconfigurable prototype system 100 according to a specific embodiment of the present invention. As shown in this figure, an electrically reconfigurable prototype system 100 includes a scalable reconfigurable prototype platform 103 and can be constructed from the prototype platform 1031 or a plurality of FPGA circuits. The scalable reconfigurable prototype platform 103 can interact with the target system 104 via programmable input / output ports 105. These input / output ports can be driven by an FPGA. The scalable reconfigurable prototype platform 103 is controlled by the system controller 102 via one or more sets of data buses. In this embodiment, these data buses include a system configuration bus 108, a system access bus (SUB) 107, and a clock bus (pulse bus) 106. The system configuration bus 108 is used for configuration of the FPGA circuit. A system access bus (SUB) 107 is used for data communication between the system controller 102 and the scalable reconfigurable prototype platform 103. The pulse bus 106 provides one or more time references for the operation of the scalable reconfigurable prototype platform 103.

  User workstation 101 provides a user with a graphical user interface and controls the operation of electrically reconfigurable prototype system 100. Through this graphical interface, the user of the user workstation 101 accesses the user design, operates a compiler that converts the user design into a configuration signal that is applied to the scalable reconfigurable prototype platform 103, and performs various operations. Using an IP library, electronic design automation software and runtime software can be used. User workstation 101 may be an engineering workstation or a personal computer. In this embodiment, the user workstation 101 and the system controller 102 communicate via an industry standard communication interface 109. The interface 109 may be USB, PCI, IEEE-1394 (also referred to as “firewire”) or any other industry standard communication bus.

  In this embodiment, the user design is input or edited through a general circuit diagram tool, or expressed using an operation (Behavior) or a hardware description language (eg, SystemC, Verilog, System Verilog, VHDL, etc.). Can then be integrated into a logic gate level circuit diagram. The present invention can provide emulation and verification of a circuit integrated within a hardware prototype system, ie, an electrically reconfigurable prototype system 100.

  FIG. 2 shows a diagram of the system controller 102. The system controller 102 includes a communication interface 204, a system access bus controller 202, a pulse generator (clock generator) 203, and a configuration controller 201. The configuration controller 201 processes the configuration signal protocol and transmits configuration data from the user workstation 101 to the scalable reconfigurable prototype platform 103 via the configuration bus 108. This allows the configuration controller 201 to configure or download a defined form of user design to the FPGA in the scalable reconfigurable prototype platform 103. The system configuration bus 108 can also be used to read back and verify the design in each FPGA, or to obtain status information and data in the runtime user design. The readback operation usually uses a protocol provided by the supplier, such as a general technique, or SelectMap or JTAG (boundary scan). In this embodiment, the system configuration bus 108 can be used to test the programmable gate array of the scalable reconfigurable prototype platform 103 in the electrically reconfigurable prototype system 100.

  The system access bus controller 202 is a state and other state unit such as a register in the design and system specific components, FIFO (first in first out queue), memory, and special logic units inserted into the user design from the compiler via the transit system access bus (SUB). To access. The system access bus 107 can also be used to return or initialize the FPGA in the scalable reconfigurable prototype platform 103 to a specific operating state.

  The pulse generator 203 drives the pulse bus 106 and provides various clock signals to the FPGA. The frequency and duty cycle of these clock signals are all programmable. These clocks are downloaded to the user design in the scalable reconfigurable prototype platform 103 and used.

  As described above, the scalable reconfigurable prototype platform 103 can be composed of one or more scalable panels (or circuit boards), FPGAs, and dynamically reconfigurable switches. The scalable reconfigurable prototype platform 103 can include any number of FPGAs and switches. FIG. 3 shows the configuration of the scalable reconfigurable prototype platform 103. As shown in FIG. 3, the scalable reconfigurable prototype platform comprises FPGAs 304-1 to 304-n. Each FPGA in 304-1 to 304-n has at least one set of connection lines, and is interconnected with other FPGAs. In this embodiment, one or a plurality of buses (for example, buses 301-303) are used to connect the FPGAs 304-1 to 304-n. In such a scheme, the signal can be connected from any FPGA to any other FPGA. The buses 301-303 can be installed as "universal buses" (i.e., buses that can be accessed by all FPGAs). Alternatively, buses 301-303 can be assigned to various configurations, in which case each bus can be dedicated to a set of specific FPGAs. These buses can also be connected to each other through dynamically reconfigurable circuit switches. These circuit switches can be provided by special switch circuits or can be configured in FPGAs 304-1 to 304-n. These FPGAs can be configured in a layered structure. In this structure, FPGAs can be grouped. In this case, the FPGAs in each group are interconnected by “local” interconnection buses, which are interconnected by one or more layers of dynamically reconfigurable switches. In addition, each FPGA can have one or more input or output signals connected to the input / output port 105 to communicate with the target system 104. These input / output signals can also be interconnected by a single layer or multiple layer dynamically reconfigurable switch to allow signals to be interconnected between FPGAs. In any case, as the technology evolves and improves, the number of these interconnects is not limited. These interconnection buses and switches are usually preferably implemented on one or more panels or circuit boards. Also, any interconnect bus (eg, any of bus 301-303, system configuration bus 108, SUB bus 107 or pulse bus 106) can be implemented with cables, optical fibers, or other interconnect methods.

  One complex number system (eg, one SoC or one dedicated circuit) typically includes multiple subsystems. For example, one SoC design can include a multimedia subsystem, a signal processing subsystem, an external control system, a central processing unit, and the like. Each subsystem can be configured into a set of FPGAs connected by a single shared local bus. The local bus is then connected to the other buses of the system with a dynamically reconfigurable switch. When this shared local bus is set as a universal bus in the “off” mode (disconnected), it becomes a local bus dedicated to the subsystem. When the switches between the local buses of each book are set to the “on” mode, communication between subsystems can be performed. The universal bus can be used for communication between subsystems or point-to-point communication between FPGAs.

  To implement a single user design in the scalable reconfigurable prototype platform 103, the user uses a compiler on the user workstation 101. FIG. 4 is a flowchart of the compiler program according to the embodiment of the present invention. As shown in FIG. 4, in step 401, the system designer can use the top module generator to generate one top module for the user design. User designs can include special design units and third party IP cores. This top-level module generator is used to describe and assemble various designs and IP cores from the user's own library and third party suppliers. The generator automatically connects the user design unit and the third party IP core based on the standard bus definition and the user-defined bus and signal interconnection relationship. Also, the system designer does not need to manually build the top module and use an automatic top module generator.

  In step 402, the system or circuit designer uses a compiler to install each design unit in the top module (eg, using a “design install” command). This design is usually written in some hardware description language or netlist. The compiler checks the wording, integrity, and completeness of the design (for example, whether all logical units in the design source code are available in a pre-defined library or logical database or can be obtained by connecting) . If there is an error in the installed design, or if a certain logic block is not available, the compiler software will report an installation error. If necessary, procedure 402 can be repeated any number of times until all input source code is verified to be correct and accepted by the compiler.

  After the design has been introduced, in step 403, all the hardware descriptions (hardware description language) that the designer is designing, such as through the use of an “integration” command in the compiler or a third-party integration tool used by the compiler. Or other formats). In an embodiment, the compiler integrates third-party IP cores in a bottom-to-top manner, maintains the third-party IP core boundary signals, and maintains runtime performance. The integrated design includes a netlist (eg, EDIF file) that can be used to configure within the FPGA in the scalable reconfigurable prototype platform 103. In an embodiment, the compiler merges all EDIF files into one EDIF document to represent the user design.

  In this embodiment, after one design is integrated in step 404, the designer can start the code definition process using the "code definition" command in the compiler. In the code definition process, the user can define any one single signal or set of signals as a defined code. Any number of signals can be defined as one code. Alternatively, the user can define a single event, ie, a set of specific codes or signal sequences, or a set of arbitrary length waveforms. The event is considered to have occurred when the state of the signal or code changes to match a certain length of waveform specified in the event. For example, FIG. 5 shows a typical “write operation” event waveform for one storage device. As shown in FIG. 5, this “write operation” event includes five code waveforms: a single signal “pulse”, “write”, “chip select”, and a bus signal “ Address (address) "and" data (data) ". In this example, this event is two pulse period lengths. As shown in FIG. 5, period 1 and period 2 are between 0 nanoseconds and 100 nanoseconds. Within this time, the “chip select” and “write” control signals are placed at the period length of one valid “clk” signal. The signal waveform within these two pulse periods defines this event. To test for the occurrence of an event, the electrically reconfigurable prototype system 100 may be configured to check a specified signal at run time and compare the change in signal with the change in signal during a predetermined event. Unlike current technology, when an event occurrence is detected, the software reports the occurrence of the event to the user and does not cause the user to decode many signal states. In this way, events are reported to the user in a high level abstract way and used to explain debugging. In one embodiment, the signal state is sampled and stored in a memory on the board, or stored in a memory or document on the user workstation 101 and used to perform further analysis. Code and events are particularly useful under debug mode, and the signal comparison and event detection mechanisms under the debug model are all exactly the same as described above. Circuit designers define an arbitrary number of codes and events as needed, so that signal information at the time of mass execution is defined in a high level abstraction layer, which is useful for debugging. Code and events defined under debug mode are converted and can be used and observed at runtime.

  In step 405, the user can divide the design into multiple blocks with a “split” command in the compiler, each block being implemented in one single FPGA. Third-party IP cores are also split and implemented in each FPGA. A large IP core can be divided into multiple FPGAs. In one embodiment, the split command uses a third party split tool. Due to the “TAI-IP unit” interconnection method described below, the split tool in the electrically reconfigurable prototype system 100 maximizes the capacity utilization of the FPGA and does not need to be restricted to the FPGA pins. Can be optimized and divided. The split tool generates a single netlist for each FPGA in the scalable FPGA. Split procedure 405 maintains all user-designed information and functions. Alternatively, third party dividers or manual divisions can also be used for design division. The divider can accept the setting of the limiting condition and can be used to instruct the divider to generate a netlist for the scalable reconfigurable prototype platform 103 hardware.

  In step 406, after the user design is split, the compiler inserts a custom circuit structure into each FPGA block to provide "measurable", "analysable", and "interconnect" functions. This special circuit structure called “TAI-IP” is also inserted in each part of one IP divided into each IP or multiple FPGAs. FIG. 6A shows a logic diagram of the circuit topology structure after division. As shown in FIG. 6 (a), in one embodiment of the present invention, a system-on-chip design 620 including a user design circuit and a third party IP is divided into circuits 625-1 to 625-n. , TAI-IP626-1 to 626-n, respectively. Each circuit in 625-1 to 625-n is one block of user design, one IP, or one part of one IP, each implemented in one FPGA. In some embodiments, one user-designed block is assigned to the same FPGA. The circuits of each block in 625-1 to 625-n are associated with TAI-IP 626-1 to 626-n and one or more communication buses or paths (buses 630-1 to 630-02 shown in the figure). Etc.) to communicate with other parts. (Only two buses are shown in FIG. 6 (a), but one communication path may include one or a plurality of signal buses based on the user selection and the interconnection relationship between the circuits. it can.)

  FIG. 6B shows a structural block diagram. In this figure, TAI-IPs 602-1 to 601-n are implemented in the scalable reconfigurable prototype platform 103 and serve as an interface between the FPGAs 602-1 to 602-n. As shown in FIG. 6 (b), the TAI-IP in each FPGA and the TAI-IP in the other FPGA are connected to each other to provide interconnection between the FPGAs in the scalable reconfigurable prototype platform 103. Each IP in one FPGA also communicates with its associated TAI-IP via other circuits assigned in the FPGA and other circuits in the FPGA. In such a structure, the input and output of one IP is controlled via TAI-IP. For example, each IP output signal can be isolated from the user design, and the signal state can be converted to a fixed value for convenience in debugging. In addition, the input and output signals of the IP are monitored and measured independently, so that the measurement possibility can be improved.

  FIG. 7 shows a diagram of a TAI-IP 700 according to an embodiment of the present invention. As shown in FIG. 7, the TAI-IP 700 includes a control circuit 701 and is used to control the TAI-IP structural block circuits (“TAI-IP units”) 702-1 to 702-n. The number of TAI-IP units in each TAI-IP is one programmable design parameter, usually based on the number of FPGAs that need to be interconnected on the FPGA circuit board, user design input / output requirements, and user specifications. Determined. Each TAI-IP unit is a single bus on the scalable reconfigurable prototype platform 103 circuit board via one 1-bit interconnect port (eg, any of interconnect ports 703-1 through 703-n). Connected to. Based on these requirements, the compiler determines the required number of TAI-IP units and generates the TAI-IP units and control circuits in the TAI-IP in each required FPGA.

  FIG. 8 shows a TAI-IP unit 800 according to an embodiment of the present invention. As shown in FIG. 8, the TAI-IP unit 800 includes dynamically reconfigurable tag memories 801 and 802, a multipath signal selector 803, a bidirectional buffer 806 (including an output buffer 806a and an input buffer 806b), and a signal latch 807. including. This is multipath selection of the data output signal 808 controlled by the dynamically reconfigurable tag memory 801 and the output enable signal 805 corresponding thereto. The output enable signal 805 corresponding to the data output signal 809 includes a user-designed output signal configured in the FPGA and a designated internal logic node signal. In addition, a fixed signal 810 (including one fixed “0” and one fixed “1”) can be selected by the signal output multipath selector and transmitted via the interconnection port 703. In such a structure, one output signal can be output on the interconnect port 703 at any time. Unassigned signals in the data output signal 809 can be linked to any value. As described below, such a configuration does not require a complete recompilation for incremental signal configuration at runtime. Unused output enable signals are assigned a “disabled” signal state, thereby preventing unintentional output of values to interconnect port 703.

  The dynamically reconfigurable tag memory 802 controls a set of signal latches, each of which can be selected to latch the input signal on the interconnect port 703. As described above, interconnect port 703 receives signals from other FPGAs via a 1-bit interconnect bus. The output signal of signal latch 807 drives data output signal 808, which is connected to the input port of the device under user design. Unassigned signals in the data output signal 808 can be left empty.

  The dynamically reconfigurable tag memories 801 and 802 are addressed by a control counter, so that the dynamically reconfigurable tag memories 801 and 802 can be loaded from the SUB bus 107 at the time of execution. Multipath selector 804 controls the direction of bi-directional buffer 806, which determines whether interconnect port 703 is an input port, output port or bi-directional port. The dynamic allocation port type of the selection signal of the multipath selector 804 is changed during execution. In the embodiment shown in FIG. 8, the multipath signal selector 803 and the multipath selector 804 are simultaneously controlled by control signals generated by the dynamically reconfigurable tag memory 801, and the same number of signals are selected. Under such a configuration, the input signals of the corresponding multipath signal selector 803 and multipath selector 804 are selected. Such a structure is naturally not essential. A plurality of multipath selectors can also be controlled by different fields in the output character string of the dynamically reconfigurable tag memory 801, and can be used for design selection of the data output signal 809 and the output enable signal 805.

  A three-state output port can be implemented with a data output signal as one of the data output signals 809 and a corresponding output enable signal as one of the corresponding output enable signals 805. A high impedance state is obtained when the corresponding output enable signal is disabled. Similarly, the bidirectional signal can be realized by simultaneously using the data output signal 809 and the data output signal 808 and the corresponding output enable signal as one of the output enable signals 805. The compiler ensures that the bidirectional port is mapped correctly, so that the corresponding address in the corresponding dynamically reconfigurable tag memory is always selected simultaneously. In one embodiment, the bi-directional signal is mapped to the same address in the dynamically reconfigurable tag memory 801, 802.

  One TAI-IP (eg, any of TAI-IP 601-1 to 601-n) can operate with faster pulses than the user design. The increase / decrease of the counter is controlled by this fast pulse, and the counter generates an address used for accessing the dynamically reconfigurable tag memories 801 and 802. Each counter has a programmable maximum and minimum count. Normally, when the maximum or minimum count value is selected for the counter, the counter returns and counts. When the upper limit is selected, the counter is reset to zero. The counter is reset to 0 at least once within one user-designed pulse period, and both the user-designed input output signal and the latched signal have already been correctly transmitted. In this embodiment, the maximum or minimum count value in each counter can be programmed at run time through SUB 107. This can dynamically change the signals that are interacted within each period of the fast pulse. The dynamically reconfigurable tag memory 801, 802 can be written via the SUB 107 by the user or real-time software, and the input or output signal of the interconnect port 703 can be dynamically adjusted based on the user's pulse. it can. With this capability, the signal value or connection can be changed under test or debug mode.

  After the TAI-IP is inserted, in step 407, the compiler processes the netlist of each FPGA using a wiring program. The wiring program is usually a program determined by the FPGA supplier, and is used to convert each netlist into a binary file or a text file. This output file can be downloaded to the FPGA in the scalable reconfigurable prototype platform 103. In one embodiment, the wiring program can be executed on one or more user workstations or processors to process FPGA wiring in parallel. The wired binary or text file can be saved on the user workstation 101 and awaiting further processing of the real-time software.

  One IP library can include TAI-IP as well as other provided IP for circuit verification, circuit debugging, and performance analysis functions. The system designer can add one or more such IPs to the user design. Such addition of IP to the user design can be performed by instructing the compiler by the system designer or by instantiating these IPs in the source code of the user design.

  The IP used for circuit verification (verification IP) includes a circuit that simulates a USB bus or a PCI bus, and can be used for verification of user-designed operations that interact with the USB bus or the PCI bus. The verification IP used in the electrically reconfigurable prototype system 100 allows a user or real-time software to access operation information provided by the creator or supplier of the verification IP via the SUB 107. Typically, the verification IP detects the user design operation and checks the compatibility of the user design with standard communication or signal protocol, or compares the user design operation with a specific operation mode (exact mode). The verification IP can provide analysis reports and error or warning information to the user or real-time software.

  For example, an IP core used for debugging (debug IP core) includes an IP core having an internal logic analyzer function (internal logic analyzer IP core) or a data flow / state analyzer. These IP cores allow system designers to debug systems that have already been configured at runtime. For example, the internal logic analyzer IP core can sample a signal value in the user design at a specified trigger point and store it in a memory unit for subsequent analysis. Execution software can access and manipulate these debug IP cores at runtime.

  The IP core used for performance analysis (performance analysis IP core) may include an IP core used for bandwidth analysis. These IP cores can be used for performance information collection and user design performance analysis. Like other IP cores, the performance analysis IP core can communicate with the user or runtime software via the SUB 107 to collaborate to complete the performance analysis.

  Execution software in the electrically reconfigurable prototype system 100 can include a dynamic configuration kit and a system debug kit. Dynamic configuration kit accepts user commands to configure FPGA, backplane and TAI-IP in scalable reconfigurable prototype platform 103 to modify operating mode, interaction, and real-time design functions . In one embodiment, after responding to the FPGA command, the FPGA configuration tool reads the binary or ASCII FPGA configuration file and transmits the file to the configuration controller 201 in the system controller 102. The FPGA configuration tool can independently configure the FPGA in one or more scalable reconfigurable prototype platforms 103, as well as the parts in the required FPGA. For example, the user can modify a logic block in the FPGA. The logic block modified using the FPGA configuration tool can be downloaded into the FPGA without the need to reconfigure another FPGA.

  In response to the circuit board configuration command, the panel configuration tool configures programmable switches on the circuit board or on the backplane in the scalable reconfigurable prototype platform 103. Typically, any switch can be placed in the “on” or “off” state. When the switch is in the “on” state, the switch is conductive. When the switch is in the “off” state, the switch is open. The panel configuration tool can selectively configure some interconnect buses to local buses, and the like.

  In response to the TAI-IP configuration command, the TAI-IP configuration tool generates data in one or more dynamically reconfigurable tag memories that are stored in the TAI-IP unit via the SUB 107. These data represent interrelationships between FPGAs or user special requirements. For example, a user may wish to provide a value of “1” for certain input signals of a specified FPGA and not recompile. In order to be able to select such an effect, the TAI-IP configuration tool recalculates the required value in the tag memory to generate this input value, and at the same time changes the value in the modified tag memory to a specific action. Write to dynamically reconfigurable tag memory.

  The system debug kit collects and analyzes design and debug information, and sets special conditions and signals to control the operation of the user design in real time. In one embodiment, the system debug kit includes (a) an FPGA readback tool, (b) a SUB access tool, (c) an internal logic analyzer tool, (d) a bandwidth analysis tool, (e) a code / event extraction tool, ( f) Includes simulator connection tool.

  The FPGA readback tool reads the contents of the FPGA specified at the time of execution or the state of the specified signal in the user design. The FPGA readback tool can be obtained from the supplier, and can read the contents of the specified FPGA using a protocol specified by the supplier, such as JTAG or SelectMAP. Many FPGA suppliers provide tools to read the contents of every register or memory unit in the FPGA. In this embodiment, after data is read back from the FPGA, the FPGA readback tool converts these information into signal values and maps them to signal names and codes in the user design. Through such a method, full observability of any signal in the FPGA can be obtained.

  The SUB access tool is used to access devices in the user design interconnected with the SUB 107 or in the electrically reconfigurable prototype system 100. All devices are mapped into the address space, thereby accessing the device using a SUB access tool, i.e. issuing commands, addresses and data to the SUB controller 202 in the system controller 102 to read or write device data. . In one embodiment, the SUB 107 extends to any device in the read / write scalable reconfigurable prototype platform 103 circuit board.

  The internal logic analyzer tool sets trigger conditions on the logic analyzer incorporated in the electrically reconfigurable prototype system 100. This logic analyzer is a special IP (internal logic analyzer IP) in one or more FPGAs downloaded into the scalable reconfigurable prototype platform 103. This logic analyzer IP can provide the same function as a conventional logic analyzer. Working with TAI-IP in an FPGA, this logic analyzer IP can provide a large amount of signal sampling and handle a large amount of trigger conditions. In one embodiment, the internal logic analyzer tool sets a trigger condition in the embedded logic analyzer IP, waits for the trigger condition or event to occur, and is then sampled from the sampling memory embedded in the logic analyzer IP. Read the signal data and convert the associated sampling data into a user-defined code format. In one embodiment, this internal logic analyzer tool installs a complex event state machine embedded in the logic analyzer IP. This event state machine describes debugging based on the acquired signal data behavior. The internal logic analyzer tool and the logic analyzer IP jointly provide the user with a real-time signal monitoring function (eg, in an online execution mode) and do not interfere with the execution status of the user design.

  The code / event extraction tool interprets signal data obtained by sampling into code and event level information. The code / event extraction tool maps signal data obtained by sampling to codes and events, and expresses them to the user in the form of codes. For example, in the “write operation” event of the bus described in the previous sentence, when the code / event extraction tool finds an example of one “write operation” event, one piece of information is created and the “write operation” event of the user bus is created. Provides the time of occurrence, the address and data of the write operation during the "write operation" event. Such a capability is very valuable, for example, when a firmware designer designs and debugs a firmware program.

  The simulator connection tool connects the simulator executed on the user workstation 101 and the configured user design in the scalable reconfigurable prototype platform 103 to complete the hardware / software emphasis verification. The simulator connection tool can access the simulator in various existing ways. For example, in one embodiment, a PLI or VPI interface is used to provide communication with a Verilog simulator, a FLI interface is used to provide communication with a VHDL simulator, and a SCEMI interface is used to provide a simulator having an SCEMI interface. Provide communication. The simulator connection tool can also support other standard interfaces or user-defined interfaces.

  While the above detailed description depicts several specific embodiments of the invention, the invention is not limited to these embodiments. Many variations and substitutions are possible within the scope of the present invention, all of which are deemed not to depart from the disclosure and protection scope of the present invention.

1 is an electrically reconfigurable prototype system 100 of one specific embodiment of the present invention. 1 is a diagram of a system controller 102 of an electrically reconfigurable prototype system 100 of the present invention. It is a block diagram of the scalable reconfigurable prototype platform 103 of this invention. It is an example of the compilation flow of one specific Example of this invention. 4 is an event waveform of a “write operation” often found in the memory device of the present invention. (A) is a block diagram of a SoC design 620 according to a specific embodiment of the present invention, where the SoC design includes a user design circuit and IP, and the user design and IP are circuits 625-1 to 625-n. It is divided in the upper part and connected to TAI-IP 626-1 to 626-n, respectively. (B) is a diagram of the present invention, where TAI-IPs 601-1 to 601-n are implemented in the scalable reconfigurable prototype platform 103 and used as interfaces of FPGAs 602-1 to 602-n. Show. 6 is a diagram of a TAI-IP 700 according to a specific embodiment of the present invention. 6 is a diagram of a TAI-IP unit 800 according to an exemplary embodiment of the present invention.

Explanation of symbols

100 Electrically Reconfigurable Prototype System 101 User Workstation 102 System Controller 103 Scalable Reconfigurable Prototype Platform
104 Target system 105 Programmable input / output port 106 Pulse bus 107 System access bus (SUB)
108 system configuration bus 109 industry standard communication interface 201 configuration controller 202 system access bus controller 203 pulse generator 204 communication interface 301, 302, 303 bus 304-1 to 304-n FPGA
601-1 to 601-n TAI-IP
602-1 to 602-n FPGA
620 system on chip design 625-1 to 625 -n circuit 626-1 to 626 -n TAI-IP
630-1 to 630-2 Bus 700 TAI IP
701 Control circuit 702-1 / 702-n TAI-IP structure block circuit 703 Interconnection port 703-703-n Interconnection port 801, 802 Dynamically reconfigurable tag memory 803 Multipath signal selector 804 Multipath selector 805 Output Enable signal 806 Bidirectional buffer 806a Bidirectional buffer 806b Input buffer 807 Signal latch 808 Data output signal 809 Data output signal 810 Fixed signal

Claims (64)

A system for user design and emulation, including a system controller and simulation platform,
The system controller is
(A) an interface interconnected with a user workstation;
(B) a data communication interface;
The simulation platform is interconnected with the data communication interface; and
(A) a plurality of field programmable logic devices capable of implementing a user design and a third party IP core;
(B) an interface that interacts with the user design at runtime and connected to the target system;
A system used for design and emulation of user designs, characterized in that   The system of claim 1, wherein the data communication interface includes a configuration bus.   The system of claim 1, wherein the data communication interface includes a system access bus.   The system of claim 1, wherein the data communication interface includes a pulse signal bus.   The system of claim 1, wherein the interface connected to the target system comprises a programmable input / output terminal signal sourced from a programmable logic device.   The system of claim 1, wherein the field programmable logic device comprises a field programmable logic gate array.   Each programmable logic device is assigned one interface module, and between the user design assigned to the other part of the programmable logic device and the other user design assigned to the programmable logic device via the interface module The system according to claim 1, wherein the communication is realized. The interface module is
(A) a control circuit;
(B) a plurality of input / output units;
The system of claim 1, wherein each input / output unit provides a 1-bit interconnect port. Each of the input / output units is
(A) a dynamically reconfigurable memory module;
(B) a first multi which is controlled by the dynamically reconfigurable memory module and selects one output signal to be output to the 1-bit interconnect port from among a plurality of programmable logic device configuration signals; With a path selector;
(C) a latch that is selected by a plurality of dynamically reconfigurable memory modules and receives a signal of a 1-bit interconnect port;
The system of claim 8, comprising:   The system of claim 9, wherein the dynamically reconfigurable memory module includes one or more dynamically reconfigurable memory units.   The dynamically reconfigurable memory module further includes a second multipath selector controlled by the dynamically reconfigurable memory module, wherein the second multipath selector has one output enable from among a plurality of output enable signals. The system of claim 9, wherein the signal is selected and the buffer is controlled to output the signal to a 1-bit interconnect port.   The system of claim 11, wherein the buffer exhibits a high impedance state.   The system of claim 11, wherein each output signal corresponds to one output enable signal.   The system of claim 11, wherein the output signal comprises a fixed signal.   The system of claim 1, wherein a plurality of selected programmable logic devices are assigned to a third party IP core.   The system of claim 1, wherein one or more programmable logic devices are assigned to a verification IP core that verifies one user circuit function.   The system of claim 16, wherein the verification IP core includes circuitry for simulating industry standard data bus operations.   The system of claim 1, wherein one or more programmable logic devices are assigned to one performance analysis IP core.   The system of claim 18, wherein the performance analysis IP core comprises a bandwidth analysis IP core.   The system of claim 1, further comprising a configuration tool capable of assigning a dynamically reconfigurable logic circuit to one selected programmable logic device.   The system of claim 1, further comprising a panel configuration tool capable of dynamically reconfiguring a bus on a circuit board on which a plurality of programmable logic devices are installed. .   The system further includes a system debug tool, wherein the system debug tool monitors and analyzes signals within the programmable logic device and between the plurality of programmable logic devices at run time. The system described in.   The system of claim 22, wherein the system debug tool comprises a field programmable gate array (FPGA) readback tool.   The system of claim 22, wherein the system debug tool comprises a system access bus access tool.   The system of claim 22, wherein the system debug tool includes an internal logic analyzer tool.   26. The system of claim 25, wherein the internal logic analyzer tool inserts a logic analyzer circuit into one or more programmable logic devices.   23. The system of claim 22, wherein the system debug tool includes a bandwidth analysis tool.   23. The system of claim 22, wherein the system debug tool includes a code / event extraction tool.   29. The system of claim 28, wherein the code / event extraction tool allows a user to associate one or more signals with a code name.   30. The system of claim 29, wherein the code / event extraction tool allows a user to set an event including multiple signals in a signal waveform via a method for setting a signal event. .   31. The system of claim 30, wherein the code / event extraction tool reports a configuration event detection result via an associated code name.   The system of claim 22, wherein the system debug tool includes a simulator connection tool.   33. The system of claim 32, wherein the simulator connection tool allows user design to interact with a simulator program executed on a user workstation in a collaborative verification environment. A method for emulating a user design, which includes the following steps:
Providing a system controller, the system controller comprising:
(A) an interface interconnected with the user workstation;
(B) a data communication interface;
Providing a simulation platform interconnected with the data communication interface, the simulation platform comprising:
(A) a plurality of field programmable logic devices capable of realizing a user design;
(B) an interface connected to the target system and interacting with the user design at runtime;
Generate a top-level module containing the user design and one or more third-party IP cores;
Integrate user design,
Dividing user design and third party IP core into several blocks, each block is realized by one programmable logic device,
One interface module is allocated to each programmable logic device, and a block realized in the programmable logic device via the interface module is allowed to communicate with other blocks in the other programmable logic device.
Wiring the block and the interface module;
Implements a wired block in a programmable logic device.   The method of claim 34, wherein the data communication interface includes a configuration bus.   The method of claim 34, wherein the data communication interface includes a system access bus.   The method of claim 34, wherein the data communication interface includes a pulse signal bus.   35. The method of claim 34, wherein the interface connected to the target system comprises a programmable input / output terminal signal sourced from a programmable logic device.   The method of claim 34, wherein the field programmable logic device comprises a field programmable logic gate array. The interface module is
(A) a control circuit;
35. The method of claim 34, comprising: (b) a plurality of input / output units; each unit providing one 1-bit interconnect port. Each of the input / output units is
(A) a dynamically reconfigurable memory module;
(B) a first multipath selector that is controlled by the dynamically reconfigurable memory module and selects an output signal to be output to a 1-bit interconnect port from a configuration signal of a plurality of programmable logic devices;
(C) a latch selected for a plurality of dynamically reconfigurable memory modules;
41. The method of claim 40, comprising receiving a signal of a 1-bit interconnect port.   42. The method of claim 41, wherein the dynamically reconfigurable memory module includes one or more dynamically reconfigurable memory units.   The dynamically reconfigurable memory module further includes a second multipath selector controlled by the dynamically reconfigurable memory module, and the second multipath selector includes one of a plurality of output enable signals. 42. The method of claim 41, wherein the output enable signal is selected and the buffer is controlled to output the signal to a 1-bit interconnect port.   44. The method of claim 43, wherein the buffer exhibits a high impedance state.   44. The method of claim 43, wherein each output signal corresponds to an output enable signal.   42. The method of claim 41, wherein the output signal comprises a fixed signal.   35. The method of claim 34, further comprising the step of assigning a verification IP core having one user circuit verification function to one or more programmable logic devices.   48. The method of claim 47, wherein the verification IP core includes circuitry that simulates industry standard data bus operations.   35. The method of claim 34, wherein the method further comprises the step of assigning a performance analysis IP core to one or more programmable logic devices.   50. The method of claim 49, wherein the performance analysis IP core comprises a bandwidth analysis IP core.   35. The method of claim 34, further comprising providing a configuration tool that can assign a dynamically reconfigurable logic circuit to a selected programmable logic device. Method.   The method further comprises providing a panel configuration tool capable of dynamically reconfiguring a bus on a circuit board on which a plurality of programmable logic devices are installed. Item 35. The method according to Item 34.   The method further includes the step of providing a system debug tool, wherein the system debug tool monitors and analyzes signals within the programmable logic device and between the plurality of programmable logic devices at runtime. 35. The method of claim 34.   54. The method of claim 53, wherein the system debug tool comprises a field programmable gate array readback tool.   54. The method of claim 53, wherein the system debug tool comprises a system access bus access tool.   54. The method of claim 53, wherein the system debug tool includes an internal logic analyzer tool.   57. The method of claim 56, comprising one or more programmable logic devices in the logic analyzer circuit.   54. The method of claim 53, wherein the system debug tool includes a bandwidth analysis tool.   54. The method of claim 53, wherein the system debug tool includes a code / event extraction tool.   60. The method of claim 59, wherein the code / event extraction tool allows a user to associate one or more signals with a code name.   60. The code / event extraction tool of claim 59, wherein the code / event extraction tool allows a user to set an event that includes a plurality of signals in a signal waveform in a manner that sets a set signal event to a user. Method.   60. The method of claim 59, wherein the code / event extraction tool reports a configuration event detection result via an associated code name.   54. The method of claim 53, wherein the system debug tool includes a simulator connection tool.   64. The method of claim 63, wherein the simulator connection tool allows a user design to interact with a simulator program executed on a user workstation in a collaborative verification environment.

Images