JP2006215330A - Method for manufacturing semiconductor device and semiconductor device manufactured by the manufacture method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device for forming a desired resist pattern on a semiconductor wafer having a step, and to provide a semiconductor device manufactured by the manufacture method. <P>SOLUTION: A resist coating is applied on a semiconductor wafer having first and second step faces with different heights and an inclined step portion 1b on the surface. The wafer is exposed to light focused on the first step face 1a or the inclined step portion 1b through a mask 2 comprising: a first mask portion having a pattern in the same width as a predetermined width corresponding to a resist pattern having the predetermined width to be formed on the first step face 1a or the inclined step portion 1b; and a second mask portion connected to the first mask portion and having a mask pattern 2a with the width larger than the predetermined width. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device for forming a resist pattern connecting a first step surface and a second step surface on a semiconductor wafer having a step composed of first and second step surfaces having different heights on the surface. The present invention relates to a manufacturing method and a semiconductor device manufactured by the manufacturing method.

  Conventionally, as a method for manufacturing this type of semiconductor device, there is one disclosed in Japanese Patent Laid-Open No. 2003-133226 (Patent Document 1).

The semiconductor device manufacturing method disclosed in this publication enables patterning of a resist pattern by performing exposure twice while changing the height of the focal plane when the wafer has a large level difference and the focal depth is insufficient. By using and aligning two photomasks for low and high steps in each exposure, the upper and lower patterns are connected to each other at the middle of the step.
JP 2003-133226 A

However, the above-described conventional example has the following problems.
(1) A plurality of masks and exposures are required.
(2) Positioning is required during one photolithography process. (Work increases and misalignment may occur.
(3) The resolution of the pattern that can be created is determined by the relationship between the height of the step and the number of masks used in one photolithography process. (If the idea is to route a pattern with the same line width from the top to the bottom of the step, there may be a compromise between the resolution of the pattern or the height of the step.)

  In view of the above-described conventional problems, the present invention provides a method for manufacturing a semiconductor device capable of forming a desired resist pattern on a semiconductor wafer having a step, and a semiconductor device manufactured by the manufacturing method. It is aimed.

  According to a first aspect of the present invention, a belt-like resist pattern is formed on a semiconductor wafer having first and second step surfaces having different heights on the surface and an inclined step portion connecting the first and second step surfaces. A method of manufacturing a semiconductor device comprising: applying a resist coating to the semiconductor wafer; and exposing the semiconductor wafer having the resist coating focused on the first step surface or the inclined step portion, When focusing on the first step surface, the first mask portion facing a part of the first step surface and the remaining portion of the first step surface connected to the first mask portion A mask having a mask pattern including the inclined step portion and a second mask portion facing the second step surface, wherein the first mask portion is formed on the first step surface. Specified width In the case where the second mask portion is focused on the mask having the same width as the predetermined width corresponding to the resist pattern and the width of the second mask portion is larger than the predetermined width, or the inclined step portion, the inclined portion. A first mask part facing a part of the step part and a second mask part connected to the first mask part and facing the remaining part of the inclined step part, the first step surface and the second step surface A mask having a mask pattern comprising a mask portion, wherein the first mask portion has the same width as the predetermined width corresponding to a resist pattern having a predetermined width to be formed on the inclined step portion. The second mask portion is formed through a mask having a width larger than the predetermined width.

  According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the second mask portion is tapered and widened at an angle from a connecting portion with the first mask portion. And the connecting portion has an R shape.

  According to a third aspect of the present invention, a strip-shaped resist pattern is formed on a semiconductor wafer having first and second stepped surfaces having different heights on the surface and an inclined stepped portion connecting the first and second stepped surfaces. A method of manufacturing a semiconductor device, comprising: applying a resist coating to the semiconductor wafer; and applying the resist coating to the semiconductor wafer, the first step surface, the inclined step portion, and the second step surface. The first exposure focused on any one of them is performed through the mask corresponding to the first stepped surface, the inclined stepped portion or the second stepped surface to be focused, and then the resist The coated semiconductor wafer is focused on one of the first step surface, the inclined step surface, and the second step surface that are not focused in the first exposure. And the second step exposure is performed through the mask corresponding to the first step surface, the inclined step portion or the second step surface to be focused, and the mask corresponding to the first step surface is: A first mask portion facing a part of the first step surface, and a second mask portion connected to the first mask portion and facing a remaining portion of the first step surface and a part of the inclined step portion. And a mask pattern comprising a third mask portion connected to the second mask portion and facing the second step surface and the remaining portion of the inclined step portion. A portion having the same width as the predetermined width corresponding to a resist pattern having a predetermined width to be formed on the first step surface, and the second mask portion having a width larger than the predetermined width, A third mask portion is a remaining portion of the inclined step portion and the second step. The mask corresponding to the second step surface has a fourth mask portion facing a part of the second step surface, and the fourth mask portion. A fifth mask portion that is connected to the remaining portion of the second step surface and a part of the inclined step portion, and is connected to the fifth mask portion, and the remaining portion of the inclined step portion and the first And a fourth mask portion corresponding to a resist pattern having a predetermined width to be formed on the second step surface. The fifth mask portion has a width larger than the predetermined width, and the sixth mask portion entirely shields the remaining portion of the inclined step portion and the first step surface. The mask corresponding to the inclined stepped portion is formed as described above. A mask pattern comprising a seventh mask portion facing a part of the inclined step portion and an eighth mask portion connected to the seventh mask portion and facing the remaining portion of the inclined step portion; The seventh mask portion has the same width as the predetermined width corresponding to the resist pattern having a predetermined width to be formed in the inclined step portion, and the eighth mask portion has a width larger than the predetermined width. It is said that it is said.

  The invention described in claim 4 uses the manufacturing method described in claim 3 to form a plurality of strip-like thermopiles extending between the surface of the semiconductor wafer and the diaphragm formed in the recess of the semiconductor wafer. It is characterized by.

  According to the first aspect of the present invention, a desired resist pattern is formed on a semiconductor wafer having first and second step surfaces having different heights on the surface and inclined step portions connecting the first and second step surfaces. Thus, a desired semiconductor device can be manufactured by a simpler process than in the prior art. In addition, even if manufacturing variations of semiconductor wafers and masks, misalignment of masks during exposure, misalignment of inclined step portions due to variations during step processing, etc. occur, the narrow first mask portion is on the inclined step portion. Therefore, a good resist pattern can be formed from the first step surface to the second step surface through the inclined step portion.

  According to invention of Claim 2, it can comprise so that a width | variety may not become narrow also in the connection part with the 1st mask part of a 2nd mask part.

  According to the invention of claim 3, a small number of semiconductor wafers having a first step surface and a second step surface having different heights on the surface and an inclined step portion connecting the first and second step surfaces. A desired resist pattern can be formed by a small number of exposures using a mask. In addition, even if manufacturing variations of semiconductor wafers and masks, misalignment of masks during exposure, misalignment of inclined step portions due to variations during step processing, etc. occur, the narrow first mask portion is on the inclined step portion. Thus, a desired resist pattern can be formed from the first step surface to the second step surface through the inclined step portion.

  According to the fourth aspect of the present invention, it is possible to provide a semiconductor device having a plurality of strip-like thermopiles that are well formed across the surface of the semiconductor wafer and the diaphragm formed in the recess of the semiconductor wafer. .

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, the principle of the semiconductor device manufacturing method of the present invention will be described with reference to FIGS.

  When a strip-shaped resist pattern having a predetermined width (d1) is formed by exposure / development processing on a semiconductor wafer having a large step of several tens to several hundred μm, the depth of focus of the optical system of the exposure apparatus used is ∞. Then, ideal patterning as shown in FIG. 1 is possible.

  That is, the surface has a step composed of step surfaces 1a and 1c having different heights, and an inclined step portion 1b connecting the step surface 1a and the step surface 1c, and resist coating (not shown) is applied. As shown in FIG. 2, a mask 2 having a mask pattern (shaded portion) 2a having the same width as a predetermined width (d1) of a desired resist pattern is used for the semiconductor wafer 1, and the depth of focus of the optical system is increased. When exposure is performed using an exposure apparatus (not shown) that is ∞, a strip-shaped portion having a predetermined width (d1) according to the mask pattern 2a is patterned as the non-exposed portion 3 in the resist coated on the semiconductor wafer 1.

  However, in practice, there is no exposure apparatus having a focal depth of ∞, and the patterning result obtained is as shown in FIG. Note that FIG. 3 shows a case where a positive resist is used and exposure is performed with an exposure apparatus (equal magnification projection exposure apparatus) focused on the stepped surface 1a.

  As can be seen from FIG. 3, the non-exposure portion 3 has a predetermined width (d1) at a portion corresponding to the step surface 1a, but the line width increases toward the upper portion of the inclined step portion 1b that is a slope. d1) It becomes thinner and becomes the thinnest at the portion corresponding to the step surface 1c. This is because the image of the mask becomes blurred (the light diffuses) as the distance from the in-focus surface increases. Therefore, as the width of the band-shaped resist pattern to be formed becomes narrower or the step becomes larger, it becomes more difficult to form a resist pattern that straddles the step surface 1a and the step surface 1c.

  FIG. 4 is a view similar to FIG. 3, but showing a case where a resist pattern having a predetermined width (d2) narrower than that of FIG. 3 is formed. In FIG. 4, as shown in FIG. 5, when a mask 2 having a mask pattern 2a having a narrower predetermined width (d2) than that of FIG. If the desired width (d2) is thin and the step is too large, the non-exposed portion 3 patterned in the resist coated on the wafer 1 disappears in the middle of the inclined step portion 1b and does not reach the step surface 1c. Sometimes.

  Therefore, in the present invention, a resist coating is applied to a semiconductor wafer having first and second step surfaces having different heights on the surface and an inclined step portion connecting the first and second step surfaces. A first mask portion facing a part of the first step surface, and a remaining portion of the first step surface, an inclined step portion, and a second portion are connected to the first semiconductor wafer 1 and the first mask portion. A mask having a mask pattern comprising a second mask portion facing the step surface of the first mask portion, the first mask portion corresponding to a resist pattern having a predetermined width to be formed on the first step surface 1a. The first mask has the same width as the predetermined width, and the second mask portion performs exposure focused on the first step surface 1a through the mask 2 having a width larger than the predetermined width. Through the stepped part of the slope Be possible to form a resist pattern that spans up to 2 of the stepped surface to provide a method of manufacturing a semiconductor device capable.

  (First Embodiment) FIG. 6 is a diagram for explaining a method of manufacturing a semiconductor device according to a first embodiment of the present invention. In the first embodiment, for example, the stepped surface 1a as the first stepped surface, the stepped surface 1c as the second stepped surface, and the inclined stepped portions connecting the stepped surfaces 1a and 1c, which have different heights on the surface. When it is necessary to form a high-resolution resist pattern on the stepped surface 1a side of the semiconductor wafer 1 having 1b, the stepped surface 1a is focused using an equal magnification projection exposure apparatus (not shown). Patterning is performed by one exposure. At this time, for the mask portion corresponding to the step surface 1a, the desired resist pattern is designed with a pattern width that provides the necessary resolution, and the portion that crosses the step surface (inclined step portion 1b) or the pattern portion of the step surface 1c is Use a mask that is designed to be wide enough to exceed the step (in the case of a positive resist).

  In FIG. 6, for a semiconductor wafer 1 having a large step of several tens to several hundreds μm composed of a step surface 1a, an inclined step portion 1b, and a step surface 1c and having a resist coating (not shown) on the surface. Then, using the mask 2 shown in FIG. 7, exposure is performed with an exposure apparatus focused on the stepped surface 1 a, and patterning is performed as the non-exposed portion 3.

  As shown in FIG. 7, the mask 2 is connected to the first mask portion 2a1 having the same width as the width (d3) of the desired resist pattern and the first mask portion 2a1, and the width (d3). It has a mask pattern 2a composed of a strip-shaped second mask portion 2a2 having a larger width (d4). The first mask portion 2a1 is formed on the portion of the mask 2 facing a part of the step surface 1a, and the second mask portion 2a2 is formed on the step surface 1a except for a portion facing the first mask portion 2a1. The remaining portion is formed on the portion of the mask 2 facing the inclined step portion 1b and the step surface 1c.

  When such a mask 2 is used and exposure is performed by an exposure apparatus, the non-exposure portion 3 goes above the inclined step portion 1b having a slope corresponding to the second mask portion 2a2 having the width (d4). The line width becomes narrower and becomes the thinnest at the portion corresponding to the second step surface 1c.

  FIG. 8 is a perspective view of a semiconductor device completed by further developing the semiconductor device exposed as described above. As shown in FIG. 8, a resist pattern 4 having a shape corresponding to the non-exposed portion 3 shown in FIG. 6 is formed. That is, the resist pattern 4 includes a resist pattern portion 4a corresponding to the step surface 1a, a resist pattern portion 4b corresponding to the inclined step portion 1b, and a resist pattern portion 4c corresponding to the step surface 1c.

  Accordingly, when the mask 2 is designed, the mask portion 2a2 according to the height difference of the step surface so that the line width of the non-exposed portion 3 when it becomes the thinnest on the step surface 1c substantially matches the predetermined width (d3). By setting the width (d4) to be thick in advance, the width of the resist pattern 4c on the step surface 1c formed by the development processing performed after the exposure processing is substantially equal to the predetermined width of the resist pattern 4a on the step surface 1a. become. Therefore, even with a high-resolution resist pattern, it is possible to satisfactorily form the resist pattern 4 having a desired pattern width (d3) across the step from the step surface 1a to the step surface 1c.

  (Second Embodiment) FIG. 9 is a diagram for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention. 9, a mask 2 shown in FIG. 10 is used for a semiconductor wafer 1 similar to that shown in FIG. Exposure is performed by an exposure apparatus focused on 1a, and patterning is performed as the non-exposed portion 3.

  As shown in FIG. 10, the mask 2 has two mask patterns 2a arranged side by side. Each mask pattern 2a has the same shape as that shown in FIG. Each mask pattern 2a is formed such that the interval between the mask portions 2a1 is (d5) and the interval between the mask portions 2a2 is (d6) (<d5). The width (d4) of the mask portion 2a2 and the interval (d6) between the mask portions 2a2 are determined depending on the size of the step and the resolution determined by the optical system.

  When such a mask 2 is used and exposure is performed with an exposure apparatus, the non-exposure portion 3 has a line width that increases as it goes above the inclined step portion 1b having a slope corresponding to the mask portion having the width (d4). It becomes thinner and becomes the thinnest at the portion corresponding to the second step surface 1c.

  FIG. 11 is a perspective view of a semiconductor device completed by further developing the semiconductor device exposed as described above. As shown in FIG. 11, two resist patterns 4 having a shape corresponding to the non-exposed portion 3 shown in FIG. 9 are formed. In the two resist patterns 4 formed, the line widths of the resist pattern portion 4a corresponding to the step surface 1a and the resist pattern portion 4c corresponding to the step surface 1c are each a desired pattern width (d3). The space between the resist pattern portions 4a and the space between the resist pattern portions 4c corresponding to the stepped surface 1c are respectively spaced (d5).

  It should be noted that the line width of the resist pattern and the space between the resist patterns do not necessarily have the same dimensions, as long as the conditions are such that a plurality of resist patterns can be successfully formed. This condition varies depending on the resist and optical system used, the size of the step, and the like.

  In the first and second embodiments described above, the width (d4) of the second mask portion 2a2 is constant. However, the present invention is not limited to this, and as shown in the modification of FIG. The portion 2a2 may have a tapered shape with a gradually increasing width. However, in order to increase the degree of integration, the width becomes a constant width of a certain limit dimension (that is, a dimension that cannot be patterned when the thickness is further reduced).

  (Third Embodiment) FIG. 13 is a diagram for explaining a method of manufacturing a semiconductor device according to a third embodiment of the present invention. In FIG. 13, a mask 2 shown in FIG. 14 is used for a semiconductor wafer 1 similar to that in FIG. Exposure is performed by an exposure apparatus focused on 1a, and patterning is performed as the non-exposed portion 3.

  As shown in FIG. 14, the mask 2 has three mask patterns 2a arranged side by side. Each mask pattern 2a is connected to a first strip-shaped mask portion 2a1 having the same width as the width (d3) of the desired resist pattern, and is connected to the first mask portion 2a1, and widens from the width (d3) in a tapered shape. And has a mask pattern 2a composed of a strip-shaped second mask portion 2a2 having a constant width (d4) from the middle. The first mask portion 2a1 is formed on the portion of the mask 2 facing a part of the step surface 1a, and the second mask portion 2a2 is formed on the step surface 1a except for a portion facing the first mask portion 2a1. The remaining portion is formed on the portion of the mask 2 facing the inclined step portion 1b and the step surface 1c.

  When such a mask 2 is used and exposure is performed with an exposure apparatus, the non-exposure portion 3 has a line width that increases as it goes above the inclined step portion 1b having a slope corresponding to the mask portion having the width (d4). It becomes thinner and becomes the thinnest at the portion corresponding to the second step surface 1c.

  By further developing the semiconductor device exposed as described above, a semiconductor device (not shown) in which three resist patterns having a shape corresponding to the non-exposed portion 3 shown in FIG. 13 are formed is completed. .

  In the third embodiment described above, the second mask portion 2a2 is tapered and wide at an angle from the connecting portion with the first mask portion 2a1, and therefore, out of the plurality of mask patterns 2a. There is a mask pattern (for example, two upper and lower mask patterns 2a) in which the width of the connecting portion is narrow. In such a case, the modification of FIG. 15 (including a partially enlarged view) is used. As shown, the shape of the portion connected to the first mask portion 2a1 is an R shape, so that the width of the connection portion can be prevented from becoming narrow.

  Thus, according to the above-described first to third embodiments, a strip shape having a width of, for example, about 1 to 2 μm on the stepped surface 1 a can be obtained by performing only one exposure using one mask 2. The resist pattern can be drawn out to the step surface 1c with a slightly thick pattern of about 20 to 30 μm through the inclined step portion 1b.

  (Fourth Embodiment) FIGS. 16 to 20 are views for explaining a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention. In the fourth embodiment, two first masks shown in FIGS. 17 and 19 are formed on a semiconductor wafer 1 similar to that shown in FIG. 6 in order to manufacture a semiconductor device having a plurality of resist patterns corresponding to steps. Using the exposure mask 2A and the second mask 2B, exposure is performed twice with the exposure device focused on the stepped surfaces 1a and 1c, respectively, and patterning is performed as the non-exposed portion 3.

  As shown in FIG. 17, the first mask 2A includes a plurality of (three in this example) strip-shaped first mask portions in which the mask pattern 2a has the same width as the width (d3) of the desired resist pattern. 2a1, a strip-shaped second mask portion 2a2 connected to the first mask portion 2a1, tapering from the width (d3) to a constant width (d4) in the middle, and a second mask portion 2a2, and has a mask pattern 2a including a part of the inclined step portion 1b and a third mask portion 2a3 that shields the entire step surface 1c from light. The first mask portion 2a1 is formed on the portion of the mask 2A facing a part of the step surface 1a, and the second mask portion 2a2 is formed on the step surface 1a except for a portion facing the first mask portion 2a1. The remaining mask and the mask 2A are formed on a portion of the inclined step portion 1b facing the remaining portion, and the third mask portion 2a3 is formed on the mask 2A facing the remaining portion of the tilted step portion 1b and the step surface 1c.

  In addition, as shown in FIG. 19, the second mask 2B includes a plurality of (three in this example) strip-shaped fourth mask patterns 2b having the same width as the width (d3) of the desired resist pattern. A mask-like fifth mask portion 2b2 connected to the mask portion 2b1 and the fourth mask portion 2b1, which is tapered from the width (d3) and has a constant width (d4) from the middle, The mask pattern 2b is connected to the mask portion 2b2 and includes a part of the inclined step portion 1b and a sixth mask portion 2b3 that shields the entire step surface 1a from light. The fourth mask portion 2b1 is formed on the portion of the mask 2B that faces a part of the step surface 1c, and the fifth mask portion 2b2 is formed on the step surface 1c except for a portion that the fourth mask portion 2b1 faces. The sixth mask portion 2b3 is formed on the remaining portion of the inclined step portion 1b and the portion of the mask 2B facing the remaining portion of the inclined step portion 1b and the step surface 1a.

  Therefore, as shown in FIG. 16, when exposure is performed using an exposure apparatus that uses a mask 2A and focuses on the stepped surface 1a of the semiconductor wafer 1, the non-exposed portion 3 corresponds to a mask portion having a width (d4). The line width becomes narrower as it goes above the sloped stepped portion 1b having a slope, and the entire surface remains from the middle of the sloped stepped portion 1b to the stepped surface 1c.

  As shown in FIG. 18, when exposure is performed with an exposure apparatus that uses the mask 2B and focuses on the stepped surface 1c of the semiconductor wafer 1, the non-exposed portion 3 corresponds to the mask portion having the width (d4). The line width becomes narrower as it goes below the inclined stepped portion 1b, which is a slope, and remains entirely from the middle of the inclined stepped portion 1b to the stepped surface 1a.

  Therefore, the semiconductor wafer 1 is first exposed by focusing on the stepped surface 1a using the mask 2A, and subsequently exposed by focusing on the stepped surface 1c using the mask 2B. As shown in FIG. 20, a non-exposed portion 3 is formed extending from the step surface 1a to the step surface 1c via the inclined step portion 1b. The non-exposed portion 3 has the same width as the desired resist pattern width (d3) on the stepped surfaces 1a and 1c, and the width on the inclined stepped portion 1b does not become less than the width (d3) due to focus shift. Is done. It should be noted that the stepped surface 1a and the stepped surface 1c may be formed so that the desired resist pattern widths are different.

  By further developing the semiconductor device exposed as described above, a semiconductor device (not shown) in which a resist pattern having a shape corresponding to the non-exposed portion 3 shown in FIG. 20 is formed.

  In this way, according to the fourth embodiment described above, a band-like shape having a width of about 1 to 2 μm, for example, is formed on the stepped surface 1a only by performing exposure twice using the two masks 2A and 2B. It is possible to create a fine resist pattern and draw the resist pattern to the stepped surface 1c with a slightly thick pattern of about 20 to 30 μm through the inclined stepped portion 1b.

  Further, in the first to fourth embodiments described above, the second mask portion 2a2 is the remaining portion of the step surface 1a excluding a part facing the first mask portion 2a1 (that is, a step close to the inclined step portion 1b). Since the first mask portion 2a1 is connected to the surface 1a), even if manufacturing variations of the semiconductor wafer 1 and the mask 2 and the positional deviation of the mask 2 during exposure occur, the first width of the narrow width is reduced. The mask portion 2a1 does not come on the inclined step portion 1b, and a good resist pattern can be formed from the step surface 1a to the step surface 1c through the inclined step portion 1b. If the configuration is such that the narrow first mask portion 2a1 and the wide second mask portion 2a2 are connected at the place where the stepped surface 1a and the inclined stepped portion 1b are just connected, the above manufacturing variations and When misalignment or the like occurs, a part of the narrow first mask portion 1a is positioned on the inclined step portion 1b, and the focus is shifted at the time of exposure focusing on the first step surface 1a. The non-exposed portion 3 to be patterned becomes thinner than the predetermined width (d3), and in the worst case, it may become too thin and disappear, but in the present invention, such a risk is eliminated. Note that the same advantages as those described above can also be obtained in the positional relationship between the connection portion between the fourth mask portion 2b1 and the second mask portion 2b2 of the mask 2B in the fourth embodiment and the semiconductor wafer 1.

  Next, a specific example of a semiconductor device manufactured by using the manufacturing method according to the fourth embodiment of the present invention will be described. 21 and 22 are a schematic perspective view and a partially enlarged view showing a flow sensor manufactured by using the manufacturing method according to the fourth embodiment of the present invention.

  The flow sensor 10 is a sensor that detects the flow velocity of a fluid such as a gas. As shown in FIG. 21, a silicon (Si) substrate 11 as a semiconductor wafer, and a diaphragm 12 formed in a recess 11b of the Si substrate 11 The micro heater 13 made of platinum or the like formed on the diaphragm 12 and power terminals 14A and 14B for supplying a driving current from a power source (not shown) to the micro heater 13 are provided.

  In addition, the flow sensor 10 has a plurality of strip-shaped upstream thermopiles 15 disposed on the upstream side of the microheater 13 in the fluid flow direction (direction from P to Q), and a strip-shaped disposed on the downstream side. A plurality of downstream thermopiles 16, output terminals 17 A and 17 B that output electromotive force generated in the upstream thermopile 15, and output terminals 18 A and 18 B that output electromotive force generated in the downstream thermopile 16.

  The upstream thermopile 15 and the downstream thermopile 16 are each composed of a thermocouple. This thermocouple is composed of, for example, a combination of Poly Si and Pt, has a cold junction and a hot junction, and generates a thermoelectromotive force according to the temperature difference between the cold junction and the hot junction.

  The upstream thermopile 15 is formed by using the manufacturing method according to the fourth embodiment of the present invention. The downstream side thermopile 16 is formed by the same method as the upstream side thermopile 15 and has the same configuration, and thus the description thereof is omitted.

  As shown in FIG. 22, the cold junction 15 </ b> A of the upstream thermopile 15 is provided on the surface 11 a portion of the Si substrate 11 where the diaphragm 12 is not formed, and the hot junction 15 </ b> B is formed in the recess 11 b of the Si substrate 11. It is provided on the diaphragm 12. FIG. 22 shows only the portions necessary for the description of the present invention, and unnecessary portions are omitted.

  The recess 11b is formed to have a step of several hundred μm between the surface 11a and the diaphragm 12. The surface 11 corresponding to the step surface 1c in FIG. 20 and the diaphragm 12 corresponding to the step surface 1a are connected by an inclined step portion 11c corresponding to the inclined step portion 1b.

  The upstream thermopile 15 is formed with the narrowest possible width and interval in an area that can be occupied by the diaphragm 12 on the side of the hot junction 15B formed on the diaphragm 12, but the cold junction 15A side is similar to the hot junction 15B. If the area that can be occupied on the surface 11a is wide, the width and the interval may be wider than those on the hot junction 15B side.

  The resist pattern on the warm contact 15B side of the upstream thermopile 15 is formed by performing focused exposure on the diaphragm 12 using a first mask (not shown) having a corresponding mask pattern. The resist pattern on the cold junction 15A side of the thermopile 15 is formed by performing focused exposure on the surface 11a using a second mask (not shown) having a corresponding mask pattern. A resist pattern is formed across the surface 11a via the inclined step portion 11c. It is not always necessary to perform patterning using only two masks, and a mask having a corresponding mask pattern is added at at least one intermediate position of the inclined step portion 11c, and exposure is focused on the intermediate position. By adding, the resolution of the inclined step portion 11c may be increased.

  In addition, the manufacturing method of parts other than the upstream side thermopile 15 and the downstream side thermopile 16 in the flow sensor 10 can apply the method disclosed by Unexamined-Japanese-Patent No. 2001-44522 which this applicant has proposed, for example. it can.

  According to the flow sensor 10 manufactured in this way, when the microheater 13 starts heating by an external driving current, the heat generated from the microheater 13 is transferred to the upstream side thermopile 15 and the downstream side using a fluid as a medium. It is transmitted to each hot junction of the thermopile 16. Since the cold junction of each thermopile is on the Si substrate 11, it is at the substrate temperature, and since each hot junction is on the diaphragm 12, it is heated by the transferred heat, and the temperature is higher than the Si substrate temperature. To rise. Each thermopile generates an electromotive force from the temperature difference between the hot junction and the cold junction.

  The heat transferred by using the fluid as a medium is transferred to each thermopile by a synergistic effect of the heat diffusion effect of the fluid and the flow velocity of the fluid flowing from P to Q. That is, when there is no flow velocity, the heat is diffused evenly to the upstream thermopile 15 and the downstream thermopile 16, and the thermoelectromotive force generated from the upstream thermopile 15 and the thermoelectromotive force generated from the downstream thermopile 16 are The difference is zero.

  On the other hand, when a flow velocity is generated in the fluid, the amount of heat transferred to the hot junction of the upstream thermopile 15 is reduced by the flow velocity, and the amount of heat transferred to the hot junction of the downstream thermopile 16 is increased. For this reason, the difference between the thermoelectromotive force generated by the upstream thermopile 15 and the thermoelectromotive force generated by the downstream thermopile 16 is a value corresponding to the flow velocity of the fluid.

  Thus, the present invention intends to create a level difference rather than a level difference caused by the fact that the thickness of the film processed by pattern miniaturization can no longer be ignored even though it is desired to be flat. The wiring pattern that is created stepwise and crosses the step (for example, a high step on the order of several tens to several hundreds μm) that does not physically leave the resist after one exposure is made as thin as possible (for example, It is very effective when creating with a line (on the order of several μm). That is, by reducing the resolution in the plane of the focal plane designed with a high resolution and increasing the depth of focus with a low resolution pattern and straddling the step, the request can be satisfied with a small number of masks.

  As described above, the embodiment of the present invention has been described. However, the present invention is not limited to this, and various modifications and applications are possible.

  For example, in the above-described embodiment, the step surface 1a is described as the first step surface and the step surface 1c is described as the second step surface. However, the present invention uses the step surface 1c as the first step surface and the step surface. It is also possible to implement the surface 1a as the second step surface.

  Moreover, although the above-mentioned embodiment demonstrated the case where a fine resist pattern was formed in the 1st level | step difference surface, it does not restrict to this. For example, when a positive resist is used and a fine resist pattern is necessary at the upper part or middle part of the step, the exposure is performed while focusing on the height of the region where the fine pattern is to be created. The mask used at this time is designed with the necessary resolution in the area where the fine pattern is required, and the mask pattern in the area where the fine pattern is unnecessary, such as the part straddling the step or the part away from the focal plane, Adjust the balance to increase the width.

  As the position in the height direction moves away from the focal plane, the light diffuses and spreads, so that even the resist in the region that should be shielded from light is exposed on the mask. Therefore, when using a negative resist, it is sufficient to use a mask designed so that the width of the space portion as a mask pattern of an unnecessary region is narrower than the width of the resist pattern to be formed. That is, for both the positive resist and the negative resist, a mask designed to increase the width of the light shielding portion may be used.

  Further, when it is desired to increase the resolution of the inclined step portions 1b and 11c when the step is very large, it is not always necessary to perform patterning with only two masks in the fourth embodiment. At least one intermediate position, a mask having a corresponding mask pattern, for example, a seventh mask portion facing a part of the inclined step portions 1b and 11c, and the seventh mask portion are connected to the inclined step portion 1b. , 11c, and a mask pattern comprising an eighth mask portion facing the remaining portion, and the seventh mask portion corresponds to the resist pattern having a predetermined width to be formed in the inclined step portions 1b, 11c. A mask whose width is the same as the width and whose eighth mask is larger than the predetermined width is added, and an exposure that focuses on the intermediate position is added. In Rukoto, sloped step 1b, may be higher 11c resolution. According to such a method, a pattern as narrow as possible can be formed with a smaller number of masks than when attempting to draw a pattern with the same width above and below the step. In the fourth embodiment, the mask used for the second and subsequent exposures may be a mask having a mask portion that has the same width as the predetermined width and does not change in width.

It is a figure explaining the principle of the manufacturing method of the semiconductor device of this invention. It is a figure which shows the mask used in FIG. It is a figure explaining the principle of the manufacturing method of the semiconductor device of this invention. It is a figure explaining the principle of the manufacturing method of the semiconductor device of this invention. It is a figure which shows the mask used in FIG. It is a figure explaining the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (First embodiment) It is a figure which shows the mask used in FIG. (First embodiment) FIG. 7 is a perspective view showing a semiconductor device manufactured by the manufacturing method of FIG. 6. (First embodiment) It is a figure explaining the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (Second Embodiment) It is a figure which shows the mask used in FIG. (Second Embodiment) It is a perspective view which shows the semiconductor device manufactured with the manufacturing method of FIG. (Second Embodiment) It is a figure which shows the modification of the mask used in 1st and 2nd embodiment. It is a figure explaining the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. (Third embodiment) It is a figure which shows the mask used in FIG. (Third embodiment) It is a figure which shows the modification of a 14th mask. It is a figure explaining the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention. (Fourth embodiment) It is a figure which shows the mask used in FIG. (Fourth embodiment) It is a figure explaining the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention. (Fourth embodiment) It is a figure which shows the mask used in FIG. (Fourth embodiment) It is a figure explaining the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention. (Fourth embodiment) It is a schematic perspective view which shows the flow sensor manufactured using the manufacturing method of the 4th Embodiment of this invention. It is the elements on larger scale of FIG.

Explanation of symbols

1 Semiconductor wafer 1a Step surface (first step surface)
1b Inclined stepped portion 1c Stepped surface (second stepped surface)
2 mask 2A first mask 2a mask pattern 2a1 first mask part 2a2 second mask part 2a3 third mask part 2B second mask 2b mask pattern 2b1 fourth mask part 2b2 fifth mask part 2b3 second 6 mask part 3 non-exposed part 4 resist pattern 10 flow sensor (semiconductor device)
11 Si substrate (semiconductor wafer)
11b Concave part 11c Inclined step part 12 Diaphragm 15,16 Thermopile

Claims (4)

A method of manufacturing a semiconductor device, wherein a strip-shaped resist pattern is formed on a semiconductor wafer having first and second step surfaces having different heights on the surface and an inclined step portion connecting the first and second step surfaces. And
A resist coating is applied to the semiconductor wafer,
When focusing the exposure on the first stepped surface or the inclined stepped portion on the semiconductor wafer on which the resist coating is applied, the first stepped surface is focused on the first stepped surface. A first mask portion opposed to a part of the first mask portion, and a second mask coupled to the first mask portion and opposed to the remaining portion of the first step surface, the inclined step portion, and the second step surface. The first mask portion has the same width as the predetermined width corresponding to a resist pattern having a predetermined width to be formed on the first step surface. In addition, when the second mask portion is focused on the mask having a width larger than the predetermined width, or the inclined step portion, the first mask portion facing a part of the inclined step portion; Connected to the first mask portion. A mask having a mask pattern comprising a remaining portion of the inclined step portion, a first step surface, and a second mask portion facing the second step surface, wherein the first mask portion is the inclined step portion. Corresponding to a resist pattern having a predetermined width to be formed in the portion, and the second mask portion is performed through a mask having a width larger than the predetermined width. A method of manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
The second mask portion is tapered and wide at an angle from a connecting portion with the first mask portion, and the connecting portion has an R shape. Production method. A method of manufacturing a semiconductor device, wherein a strip-shaped resist pattern is formed on a semiconductor wafer having first and second step surfaces having different heights on the surface and an inclined step portion connecting the first and second step surfaces. And
A resist coating is applied to the semiconductor wafer,
The first exposure focused on any one of the first stepped surface, the inclined stepped portion, and the second stepped surface is focused on the resist-coated semiconductor wafer. Performing through a mask corresponding to the first step surface, the inclined step portion or the second step surface,
Next, the semiconductor wafer on which the resist coating has been applied is focused on any one of the first step surface, the inclined step portion, and the second step surface that are not focused by the first exposure. A second exposure that combines the first step surface, the inclined step portion, or the mask corresponding to the second step surface to be focused,
The mask corresponding to the first step surface is connected to the first mask portion facing a part of the first step surface, the remaining portion of the first step surface, and the first mask portion. From a second mask part facing a part of the inclined step part, and a third mask part connected to the second mask part and facing the remaining part of the inclined step part and the second step surface The first mask portion has the same width as the predetermined width corresponding to a resist pattern having a predetermined width to be formed on the first step surface, and the second mask portion However, the width is larger than the predetermined width, and the third mask portion is formed so as to completely shield the remaining portion of the inclined step portion and the second step surface,
The mask corresponding to the second step surface is connected to the fourth mask portion facing a part of the second step surface, the remaining portion of the second step surface, and the fourth mask portion. A fifth mask portion facing part of the inclined step portion, and a sixth mask portion connected to the fifth mask portion and facing the remaining portion of the inclined step portion and the first step surface. The fourth mask portion has the same width as the predetermined width corresponding to a resist pattern having a predetermined width to be formed on the second stepped surface, and the fifth mask portion. However, the width is larger than the predetermined width, and the sixth mask portion is formed so as to totally shield the remaining portion of the inclined step portion and the first step surface,
The mask corresponding to the inclined step portion is a seventh mask portion facing a part of the inclined step portion, and an eighth mask connected to the seventh mask portion and facing the remaining portion of the inclined step portion. The seventh mask portion has the same width as the predetermined width corresponding to the resist pattern having a predetermined width to be formed on the inclined step portion, and the eighth mask portion The method of manufacturing a semiconductor device, wherein the mask portion has a width larger than the predetermined width. A semiconductor device, wherein a plurality of strip-like thermopiles are formed between the surface of a semiconductor wafer and a diaphragm formed in a recess of the semiconductor wafer using the manufacturing method according to claim 3.

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