JPH02228022A - Hole-pattern forming method - Google Patents

Hole-pattern forming method

Info

Publication number
JPH02228022A
JPH02228022A JP1048104A JP4810489A JPH02228022A JP H02228022 A JPH02228022 A JP H02228022A JP 1048104 A JP1048104 A JP 1048104A JP 4810489 A JP4810489 A JP 4810489A JP H02228022 A JPH02228022 A JP H02228022A
Authority
JP
Japan
Prior art keywords
hole
substrate
mask
hole patterns
lower parts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1048104A
Other languages
Japanese (ja)
Inventor
Fumiaki Ushiyama
文明 牛山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP1048104A priority Critical patent/JPH02228022A/en
Publication of JPH02228022A publication Critical patent/JPH02228022A/en
Pending legal-status Critical Current

Links

Landscapes

  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To form hole patterns having the designed sizes at the same time at the upper part and the lower part of a step by using the different masks whose correcting amounts to be applied for the designed sizes are different when the hole patterns are formed at the upper part and the lower part of the step of a substrate. CONSTITUTION:Hole patterns on masks are transferred on positive resist 21 which is applied on a substrate 31 having a step of 0.5mum by a projection expo sure method, and development is performed. At this time, the designed sizes of the diameters of the holes are both 1.0mum for the upper and lower parts of the step. Since the thicknesses of the resist film at the upper and lower parts of the step are different, the correcting amounts for the masks at the upper and lower parts of the step are made to be 0mum and +0.07mum for the designed values respectively. The masks which are differently corrected at the upper and lower parts of the step are used. In this way, the hole patterns having the designed sizes can be formed at the same time at the upper and lower parts of the step.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、段差を有する基板の段差上部、下部に、それ
ぞれ、ホールパターンを形成する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming hole patterns at the top and bottom of a step, respectively, of a substrate having a step.

[従来の技術] 段差を有する基板上に塗布されたポジレジストへ、マス
ク上のホールパターンを、投影露光法で転写し、現像処
理することにより、前記基板の段差上部、下部に、それ
ぞれ、ホールパターンを形成する際、従来は、設計寸法
に対して加えるマスク寸法の補正量が、前記段差上部と
、下部で同じであるマスクを用いていた。
[Prior Art] A hole pattern on a mask is transferred by a projection exposure method to a positive resist coated on a substrate having steps, and a development process is performed to form holes at the top and bottom of the steps of the substrate, respectively. When forming a pattern, conventionally, a mask has been used in which the amount of mask dimension correction added to the design dimension is the same for the upper and lower portions of the step.

[発明が解決しようとする課題] しかし、前述の従来技術では、以下なる問題点を有する
[Problems to be Solved by the Invention] However, the above-mentioned conventional technology has the following problems.

第3図は、(15μmの段差を有する基板31上に、ポ
ジレジスト32を塗布した時の断面図であるが、段差下
部のレジスト膜厚53に比べ、段差上部のレジスト膜厚
34は薄くなり、段差下部1.2μmに対し、段差上部
はC17μmである。
FIG. 3 is a cross-sectional view when a positive resist 32 is applied on a substrate 31 having a step of 15 μm, and the resist film thickness 34 at the top of the step is thinner than the resist film thickness 53 at the bottom of the step. , while the lower part of the step is 1.2 μm, the upper part of the step is 17 μm.

また、第2図は、第3図と同様に、[lL5μ扉の段差
を有する基板上に塗布されたポジレジストへ、マスク上
のホールパターンを、投影露光法で転写し、現像処理す
ることにより、前記段差の上、下部に、それぞれ、ホー
ルパターンを形成する時の露光時間と、ホール寸法の関
係を示した図であり、基板材質は、前記段差の上、下部
共に二酸化シリコンである。ここで、前記ホールの設計
寸法は、段差上、下部共に、直径1.0μmであり、マ
スク寸法の補正量も同じ(0であるマスクを用いている
。第3図のように、段差上、下部のレジスト膜厚が異な
るために、第2図に示される露光時間と、ホール寸法の
関係は、段差上、下部で太き(異なる。そして、段差上
部のホール径を設計寸法どおり1.0μmにするには、
α19秒の露光が必要で、この時、段差下部のホール径
は、0.93μmと、設計寸法に比べ0.07μm小さ
(なってしまう。
In addition, as in FIG. 3, FIG. , is a diagram showing the relationship between the exposure time and the hole size when forming a hole pattern above and below the step, respectively, and the substrate material is silicon dioxide both above and below the step. Here, the design dimensions of the hole are 1.0 μm in diameter both on the top and bottom of the step, and the mask size correction amount is the same (0).As shown in FIG. Because the resist film thickness at the bottom is different, the relationship between the exposure time and the hole size shown in Figure 2 is thicker (different) at the top and bottom of the step. To make it
Exposure for α19 seconds is required, and at this time, the hole diameter at the bottom of the step is 0.93 μm, which is 0.07 μm smaller than the design dimension.

このように、従来のホールパターン形成方法では、段差
上、下部でレジスト膜厚が異なり、また、マスク寸法の
補正量も同じであるために、段差上、下部に、それぞれ
、設計寸法どおりのホールパターンを同時に形成するこ
とができなかった。
In this way, in the conventional hole pattern formation method, the resist film thickness is different at the top and bottom of the step, and the amount of mask dimension correction is also the same, so holes are formed on the top and bottom of the step, respectively, according to the designed dimensions. Patterns could not be formed simultaneously.

そこで、本発明はこのような問題点を解決するもので、
その目的とするところは、段差の上、下部に、それぞれ
設計寸法どおりのホールパターンを同時に得られるホー
ルパターン形成方法を提供するところにある。
Therefore, the present invention aims to solve these problems.
The objective is to provide a hole pattern forming method that can simultaneously obtain hole patterns having the designed dimensions above and below the step.

[課題を解決するための手段] 本発明のホールパターン形成方法は、段差を有する基板
上に塗布されたポジレジストへ、マスク上のホールパタ
ーンを、投影露光法で転写し、現像処理することにより
、前記基板の段差上部、下部に、それぞれホールパター
ンを形成する際、設計寸法に対して加えるマスク寸法の
補正量が、前記段差上部と、下部で異なるマスクを用い
ることを特徴とする。
[Means for Solving the Problems] The hole pattern forming method of the present invention involves transferring a hole pattern on a mask to a positive resist coated on a substrate having steps by a projection exposure method, and then developing it. , when forming hole patterns at the upper and lower portions of the step of the substrate, the amount of mask dimension correction added to the design dimension is different for the upper and lower portions of the step.

[実施例] 第1図は、α5μmの段差を有する基板上に塗布された
ポジレジストへ、マスク上のホールパターンを投影露光
法で転写し、現像処理する方法により、前記段差の上、
下部にそれぞれ、ホールパターンを形成する時の露光時
間と、ホール寸法の関係を示した図であり、基板材質、
レジスト塗布条件等の諸条件は、従来技術と同様である
。しかし、前記ホールの設計寸法は、段差上、下部共に
、直径1.0μmであるが、段差上部、下部のマスクの
補正量は、それぞれ設計値に対して0μmと十107μ
mであり、段差上、下部で異なる補正をしたマスクを用
いた。
[Example] FIG. 1 shows a method in which a hole pattern on a mask is transferred by a projection exposure method to a positive resist coated on a substrate having a step of α5 μm, and then developed.
The lower part is a diagram showing the relationship between the exposure time and hole dimensions when forming a hole pattern, and shows the relationship between the substrate material,
Conditions such as resist coating conditions are the same as in the prior art. However, the design dimensions of the hole are 1.0 μm in diameter at both the top and bottom of the step, but the mask correction amounts for the top and bottom of the step are 0 μm and 1107 μm, respectively, with respect to the design value.
m, and masks with different corrections were used at the top and bottom of the step.

第1図によると、段差上部のホールを、設計寸法どおり
に形成する露光時間0.19秒の時に、段差上、下部の
レジスト膜厚の相違から生ずる、段差下部のホール寸法
と設計寸法とのズレ(107μm分を、あらかじめマス
ク側に補正しであるために、段差上部のホール径を設計
寸法どおり直径′1.0μmにする露光時間119秒で
、段差下部のホール寸法も同じ(設計寸法どおり直径1
.0μmにすることができる。このように、設計寸法に
対して加えるマスク寸法の補正量が、前記段差上部と、
下部で異なるマスクを用いることにより、段差上部、下
部に、それぞれ設計寸法どおりのホールパターンを同時
に形成することができる。
According to Figure 1, when an exposure time of 0.19 seconds is used to form a hole at the top of the step according to the design dimension, the hole size at the bottom of the step and the design dimension is caused by the difference in resist film thickness on the top and bottom of the step. Since the deviation (107 μm) was corrected in advance on the mask side, the hole diameter at the top of the step was set to 1.0 μm in diameter according to the design dimension.The exposure time was 119 seconds, and the hole diameter at the bottom of the step was also the same (as the design dimension). Diameter 1
.. It can be set to 0 μm. In this way, the amount of mask dimension correction added to the design dimension is
By using different masks at the lower part, hole patterns having the designed dimensions can be simultaneously formed at the upper and lower parts of the step.

以上、本実施例では段差上、下部に位置するホールパタ
ーンの設計寸法が共に直径1.0μmの場合について述
べたが、設計寸法が本実施例以外の寸法であったり、ま
たは段差上、下部で異なる場合においても、本実施例と
同様な考え方で段差上、下部に対してそれぞれ、異なる
マスク寸法補正をすることにより、同様な効果が得られ
ることは言うまでもない。
In this example, we have described the case where the design dimensions of the hole patterns located above and below the step are both 1.0 μm in diameter. It goes without saying that even in different cases, similar effects can be obtained by performing different mask dimension corrections for the upper and lower portions of the step using the same concept as in this embodiment.

[発明の効果コ 以上述べたように本発明によれば、段差を有する基板上
に塗布されたポジレジストへ、マスク上のホールパター
ンを、投影露光法で転写し、現像処理することによ、す
、前記基板の段差上部、下部に、それぞれホールパター
ンを形成する際、設計寸法に対して加えるマスク寸法の
補正量が、前記段差上部と、下部で異なるマスクを用い
ることにより、段差の上部、下部に、それぞれ設計寸法
どおりのホールパターンを同時に形成できるという効果
を有し、更に本発明は、マスクに補正を加えるだけで、
ホールパターン形成時の工程数が増えないことから、製
造効率的にも優れた効果を有するものである。
[Effects of the Invention] As described above, according to the present invention, a hole pattern on a mask is transferred to a positive resist coated on a substrate having steps by a projection exposure method, and then developed. When forming hole patterns at the top and bottom of the step of the substrate, the amount of mask dimension correction applied to the design dimension is different for the top and bottom of the step, thereby making it possible to The present invention has the effect of simultaneously forming hole patterns in accordance with the designed dimensions in the lower part, and furthermore, the present invention enables the hole patterns to be formed at the same time by simply making corrections to the mask.
Since the number of steps during hole pattern formation does not increase, it has an excellent effect in terms of manufacturing efficiency.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明のホールパターン形成方法により、段
差を有する基板上へ、ホールパターンを形成した時の、
露光時間と、ホール寸法の関係を示す図である。 第2図は、従来のホールパターン形成方法により、段差
を有する基板上へ、ホールパターンを形成した時の露光
時間とホール寸法の関係を示す図である。 第3図は、段差を有する基板上へ、ポジレジストを塗布
した時の断面図である。 31・・・・・・・・・基 板 32・・・・・・・・・ポジレジスト 33・・・・・・・・・段差下部のレジスト膜厚註を晴
簡 71咽 (矛yJ ¥21刀 4・・・・・・・・・段差上部のレジスト膜厚
FIG. 1 shows the result when a hole pattern is formed on a substrate having steps by the hole pattern forming method of the present invention.
It is a figure showing the relationship between exposure time and hole size. FIG. 2 is a diagram showing the relationship between exposure time and hole size when a hole pattern is formed on a substrate having steps by a conventional hole pattern forming method. FIG. 3 is a cross-sectional view when a positive resist is applied onto a substrate having steps. 31...Substrate 32...Positive resist 33...Resist film thickness note at the bottom of the step 21 Katana 4...Resist film thickness at the top of the step

Claims (1)

【特許請求の範囲】[Claims] 段差を有する基板上に塗布されたポジレジストへ、マス
ク上のホールパターンを、投影露光法で転写し、現像処
理することにより、前記基板の段差上部、下部に、それ
ぞれ、ホールパターンを形成する際、設計寸法に対して
加えるマスク寸法の補正量が、前記段差上部と、下部で
異なるマスクを用いることを特徴とするホールパターン
の形成方法。
When forming hole patterns at the top and bottom of the step of the substrate by transferring the hole pattern on the mask using a projection exposure method to a positive resist coated on a substrate having a step and developing it. . A method for forming a hole pattern, characterized in that a mask is used in which the amount of mask dimension correction added to the design dimension differs between the upper and lower portions of the step.
JP1048104A 1989-02-28 1989-02-28 Hole-pattern forming method Pending JPH02228022A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1048104A JPH02228022A (en) 1989-02-28 1989-02-28 Hole-pattern forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1048104A JPH02228022A (en) 1989-02-28 1989-02-28 Hole-pattern forming method

Publications (1)

Publication Number Publication Date
JPH02228022A true JPH02228022A (en) 1990-09-11

Family

ID=12794008

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1048104A Pending JPH02228022A (en) 1989-02-28 1989-02-28 Hole-pattern forming method

Country Status (1)

Country Link
JP (1) JPH02228022A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100290588B1 (en) * 1998-07-03 2001-06-01 윤종용 Method for forming conductive film pattern in semiconductor device
JP2002313702A (en) * 2001-04-17 2002-10-25 Mitsubishi Electric Corp Method of manufacturing semiconductor device and the semiconductor device
KR20020097030A (en) * 2001-06-20 2002-12-31 닛뽕덴끼 가부시끼가이샤 Method of manufacturing a semiconductor device and designing a mask pattern
JP2006215330A (en) * 2005-02-04 2006-08-17 Yazaki Corp Method for manufacturing semiconductor device and semiconductor device manufactured by the manufacture method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100290588B1 (en) * 1998-07-03 2001-06-01 윤종용 Method for forming conductive film pattern in semiconductor device
JP2002313702A (en) * 2001-04-17 2002-10-25 Mitsubishi Electric Corp Method of manufacturing semiconductor device and the semiconductor device
KR20020097030A (en) * 2001-06-20 2002-12-31 닛뽕덴끼 가부시끼가이샤 Method of manufacturing a semiconductor device and designing a mask pattern
JP2003005345A (en) * 2001-06-20 2003-01-08 Nec Corp Mask pattern design method
JP4675504B2 (en) * 2001-06-20 2011-04-27 ルネサスエレクトロニクス株式会社 Mask pattern design method
JP2006215330A (en) * 2005-02-04 2006-08-17 Yazaki Corp Method for manufacturing semiconductor device and semiconductor device manufactured by the manufacture method

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