JP2006214892A - Method of testing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To properly perform quality discrimination of a semiconductor device such that a test is performed in order of high temperature test and room temperature test. <P>SOLUTION: Acceptance or rejection discrimination fuse circuits 13a to 13n are provided on memory cell arrays 11a to 11n respectively, and a high temperature test result of the high temperature test of the corresponding memory cell arrays 11a to 11n is written. In the semiconductor device, at first, the high temperature test is performed, and the high temperature test result of the high temperature test of the memory cell arrays 11a to 11n is written on the acceptance or rejection discrimination fuse circuits 13a to 13n provided respectively of the memory cell arrays 11a to 11n. Next, the room temperature test is performed, and a method of testing the semiconductor device accepts or reject the memory cell arrays 11a to 11n on the basis of the high temperature test result written on the memory cell arrays 11a to 11n and the room temperature test result of the room temperature test. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device test method, and more particularly to a semiconductor device test method for testing a semiconductor device in the order of a high temperature test and a normal temperature test.

  Conventionally, in a test for discriminating a semiconductor device into a non-defective product and a defective product, first, a high-temperature test is performed in a harsh environment. In a high temperature test, if a defect occurs in a part of a macro (for example, a memory macro), the part is switched to a redundant circuit to make a normal macro. Then, a normal temperature test is performed to discriminate between good and defective products. In this test, semiconductor devices that proceed to room temperature tests are limited to semiconductor devices that are non-defective after the process of switching to redundant circuits, thereby eliminating semiconductor devices such as poor margins at high temperatures and reducing test time. I was planning. For example, at the initial stage of the normal temperature test, a determination fuse indicating the determination result of the high temperature test is read, and if it is defective, the normal temperature test is not performed (see, for example, Patent Documents 1 to 6).

  On the other hand, in recent years, the circuit scale of semiconductor devices has become larger with higher integration. Therefore, in such a test of a semiconductor device, even if not all the installed macros pass, if a certain number of macros pass the test, they may be used as semi-defective products.

  In a test for discriminating such semi-defective products, the number of passed macros is counted after the normal temperature test to discriminate good products, semi-defective products, and defective products. For example, if all the macros pass, it is determined as a non-defective product, if the macro passes a predetermined number, it is determined as a semi-defective product, and if the macro does not pass a predetermined number, it is determined as a defective product. For this reason, the semiconductor device in which the macro is determined to fail (defective) in the high-temperature test is also subjected to the normal temperature test to determine whether the product is good, semi-good, or defective. As a result, even if the macro is determined to be a failure in the high-temperature test, it may be determined to be a pass in the normal-temperature test, and there is a risk of erroneous quality determination.

  FIG. 9 is a diagram illustrating an example of a test result of a semiconductor device subjected to a high temperature test. In the figure, the high temperature test results in each of the test blocks T / B1 to T / B10 of the semiconductor device are shown. The test block indicates a block of the semiconductor device on which the test determination is performed, and there are ten test blocks in the example of the figure. The test block corresponds to the macro of the semiconductor device and shows the test result in each macro.

  For example, test block T / B1 indicates that the high-temperature test has been passed (indicated as PASS in the figure). In the test block T / B3, it is indicated that the location where the defect has occurred can be relieved by redundancy (in the figure, it is indicated as redundant). In the test block T / B2, the number of locations where defects have occurred is larger than the number that can be relieved by redundancy, indicating a failure (indicated as FAIL in the figure). That is, it is indicated that all defects of the macro (test block) cannot be relieved even by redundancy.

  FIG. 10 is an example showing a test result of a normal temperature test of the semiconductor device subjected to the high temperature test of FIG. The test blocks T / B3 and T / B6 shown in FIG. 9 pass in the room temperature test as shown in FIG. 10 by switching to the redundant circuit. On the other hand, because the environmental conditions of the normal temperature test are looser than the high temperature test, as shown by the test block T / B2 in FIG. 9, what was a failure in the high temperature test is different from the pass in the normal temperature test as shown in FIG. May be.

Of the 10 test blocks (macro), if the number of failures is 2 or less, if it is a semi-defective product, the semiconductor device of FIGS. 9 and 10 is essentially a semi-good product because there is one fail. As shown in FIG. 10, in the room temperature test, since all the test blocks have passed, as shown in FIG.
JP-A-61-61440 JP-A-8-213464 JP-A-11-243124 Japanese Patent Laid-Open No. 11-251382 JP 11-260924 A JP-A-11-243124

  As described above, when the high temperature test and the normal temperature test are performed in this order, even if the circuit block (macro) is determined to be failed in the high temperature test, in the normal temperature test, it is determined to be a pass and erroneous quality determination is performed. There was a problem of fear.

  The present invention has been made in view of these points, and a semiconductor device test method capable of appropriately determining the quality of a semiconductor device by recording the result of a high-temperature test in the semiconductor device. The purpose is to provide.

  In the present invention, in order to solve the above problem, in a semiconductor device testing method for testing a semiconductor device in the order of a high temperature test and a room temperature test as shown in FIG. 1, each of the plurality of circuit blocks 1a, 1b,. The high temperature test result of the circuit block 1a, 1b, ..., 1n is written in the provided high temperature test result information section 2a, 2b, ..., 2n, and is written in the high temperature test result information section 2a, 2b, ..., 2n. A test method for a semiconductor device is provided, wherein pass / fail judgment of the circuit blocks 1a, 1b,..., 1n is performed based on the obtained high temperature test result and the normal temperature test result of the normal temperature test of the circuit block. .

  According to such a semiconductor device testing method, the high temperature test result of the high temperature test is written in the high temperature test result information sections 2a, 2b,. Then, the pass / fail judgment of the circuit blocks 1a, 1b,..., 1n is performed based on the high temperature test result and the normal temperature test result of the circuit block. Thereby, even if the circuit blocks 1a, 1b,..., 1n judged to be unacceptable in the high temperature test pass in the normal temperature test, by referring to the high temperature test result information sections 2a, 2b,. It can be confirmed that the test was not successful in the high temperature test.

  In the semiconductor device test method of the present invention, the high-temperature test result of the high-temperature test is written in the high-temperature test result information section, and the pass / fail judgment of the circuit block is performed based on the high-temperature test result and the normal temperature test result of the normal temperature test of the circuit block. I did it. As a result, even if the circuit block that is judged to be rejected in the high-temperature test passes the normal-temperature test, it can be confirmed whether or not it was rejected in the high-temperature test by referring to the high-temperature test result information section. The quality of the semiconductor device can be determined.

Hereinafter, the principle of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram showing an outline of a semiconductor device. As shown in FIG. 1, the semiconductor device has circuit blocks 1a, 1b,..., 1n and high-temperature test result information sections 2a, 2b,. The semiconductor device is subjected to a test for detecting, for example, a disconnection, a dust defect, a margin defect, and the like in the order of a high temperature test and a normal temperature test.

The circuit blocks 1a, 1b,..., 1n are circuit blocks that realize predetermined functions. For example, a memory cell array that stores data.
The high temperature test result information sections 2a, 2b,..., 2n are provided in the plurality of circuit blocks 1a, 1b,. In the high temperature test result information sections 2a, 2b,..., 2n, the high temperature test results of the high temperature tests of the corresponding circuit blocks 1a, 1b,.

Hereinafter, a method for testing the semiconductor device shown in the figure will be described.
First, a high temperature test is performed. The high temperature test results in the high temperature test of the circuit blocks 1a, 1b, ..., 1n are written in the high temperature test result information sections 2a, 2b, ..., 2n provided in the plurality of circuit blocks 1a, 1b, ..., 1n, respectively. .

  Next, a room temperature test is performed. Then, the pass / fail judgment of the circuit blocks 1a, 1b,..., 1n is performed based on the high temperature test results written in the high temperature test result information sections 2a, 2b,. For example, even if the normal temperature test is acceptable, if the high temperature test result is unacceptable, the circuit block is determined to be unacceptable. That is, what has passed in both tests is determined to be acceptable.

  Then, the number of passing circuit blocks 1a, 1b,..., 1n is counted. If all of the circuit blocks 1a, 1b,..., 1n pass, it is determined that the product is non-defective.

  Thus, the high temperature test result of the high temperature test is written in the high temperature test result information sections 2a, 2b,..., 2n, and the circuit blocks 1a, 1b,. The pass / fail judgment was made. Thereby, even if the circuit blocks 1a, 1b,..., 1n judged to be unacceptable in the high temperature test pass in the normal temperature test, by referring to the high temperature test result information sections 2a, 2b,. In the high temperature test, it can be confirmed whether or not the semiconductor device has been rejected, and the quality of the semiconductor device can be properly determined.

Next, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 2 is a diagram illustrating a configuration example of a semiconductor device. The semiconductor device shown in the figure is, for example, a RAM (Random Access Memory), and has a plurality of memory macros 10a, 10b,. This semiconductor device is subjected to a high-temperature test at, for example, 85 ° C., and a redundant process is performed according to the test result. Next, for example, a normal temperature test at 25 ° C. is performed.

The memory macro 10a includes a memory cell array 11a, redundant bits 12a, and a pass / fail determination fuse circuit 13a.
The memory cell array 11a is composed of a plurality of memory cells that store 1-bit data.

  Redundant bit 12a is switched to the defective bit when any of a plurality of bits (memory cells) of memory cell array 11a is defective, and rescues memory cell array 11a. In the figure, the redundant bit 12a is 1 bit, and a 1-bit defective memory cell of the memory cell array 11a can be relieved. Of course, two or more redundant bits 12a may be provided to repair defective memory cells of two or more bits. Examples of defects include disconnection, dust defects, and margin defects.

The pass / fail determination fuse circuit 13a has a fuse in which the pass / fail result of the memory macro 10a in the high temperature test is written, and is cut by, for example, a laser.
The pass / fail judgment of the memory macro 10a in the high temperature test is judged as a failure when the number of defective memory cells in the memory cell array 11a exceeds the number of redundant bits 12a, and the fuse of the pass / fail judgment fuse circuit 13a is cut. Is done.

  On the other hand, if the number of defective memory cells in the memory cell array 11a is equal to or less than the number of redundant bits 12a, all the defective memory cells are relieved by the redundant bits 12a. The fuse of the fuse circuit 13a is not cut.

  The memory macros 10b,..., 10n are also similar to the memory cell array 11a, redundant bits 12a, and pass / fail judgment fuse circuit 13a of the memory macro 10a. The pass / fail judgment fuse circuits 13b,..., 13n are provided, and detailed description thereof is omitted. In each of the memory macros 10b to 10n, the result of the high temperature test is written in the pass / fail determination fuse circuits 13b to 13n.

Next, reading of output data of the memory macros 10a, 10b,..., 10n in the high temperature test will be described.
FIG. 3 is a diagram showing a scan circuit of the memory macro. As shown in the figure, FFs (flip-flops) 21a, 21b,..., 21n are connected to the memory macros 10a, 10b,.

  The FFs 21a, 21b,..., 21n constitute a scan circuit and hold output data of the memory macros 10a, 10b,. The output data held in the FFs 21a, 21b,..., 21n are sequentially output from IN to OUT. The path and fail of the memory macros 10a, 10b,..., 10n (memory cell arrays 11a, 11b,..., 11n) in the high temperature test can be determined based on the output data of the memory macros 10a, 10b,. The fuses of the pass / fail determination fuse circuits 13a, 13b,..., 13n can be cut according to the determined pass and fail. Similarly, in the normal temperature test, the test results of the memory macros 10a, 10b,..., 10n can be determined by the FFs 21a, 21b,.

  After the high temperature test, the redundant processing of the memory cell arrays 11a, 11b,. That is, the defective memory cells of the memory cell arrays 11a, 11b,..., 11n are switched to the redundant bits 12a, 12b,. Thereafter, a normal temperature test is performed, and the pass and fail of the memory macros 10a, 10b,..., 10n in the normal temperature test are determined by the scan circuit of FIG.

  At this time, the states of the pass / fail determination fuse circuits 13a, 13b,..., 13n are also read by the scan circuit for the pass / fail determination fuse circuit described below. Even if the memory macros 10a, 10b,..., 10n are determined to be passes by the scan circuit in FIG. 3, if any of the pass / fail determination fuse circuits 13a, 13b,. This is because the macros 10a, 10b,..., 10n are determined as fail. That is, even if the memory macros 10a, 10b,..., 10n determined to fail in the high temperature test are determined to pass in the normal temperature test, it is possible to determine that the memory macro 10a, 10b,.

  Next, a scan circuit that reads the pass / fail determination fuse circuits 13a, 13b,..., 13n will be described. FIG. 4 is a diagram showing a scan circuit of the pass / fail determination fuse circuit. As shown in the drawing, FFs 22a, 22b,..., 22n are connected to the pass / fail determination fuse circuits 13a, 13b,. The FFs 22a, 22b,..., 22n constitute a scan circuit, and the data of the pass / fail determination fuse circuits 13a, 13b,. The output data held in the FFs 22a, 22b,..., 22n are sequentially output from IN to OUT. Pass / fail of the memory macros 10a, 10b,..., 10n (memory cell arrays 11a, 11b,..., 11n) performed in the high temperature test is determined based on the output data of the pass / fail determination fuse circuits 13a, 13b,. be able to.

  Note that one end of the fuses of the pass / fail determination fuse circuits 13a, 13b,..., 13n is connected to the FFs 22a, 22b,..., 22n, and the other end receives, for example, a signal line signal such as a power supply. ing. When the fuses of the pass / fail determination fuse circuits 13a, 13b,. It can be seen whether the fuses of the circuits 13a, 13b,.

Hereinafter, the flow of the high temperature test, redundant process, and room temperature test of the semiconductor device of FIG. 2 will be described.
First, a high temperature test of the semiconductor device shown in FIG. 2 is performed. Then, the memory macros 10a, 10b,..., 10n are determined by the scan circuit described in FIG. If there is no defect in the memory cell of the memory cell array 11a of the memory macro 10a, the memory macro 10a is determined as a pass. If there are defects equal to or less than the number of redundant bits 12a in the memory cells of the memory cell array 11a of the memory macro 10a, the memory macro 10a is determined to be redundant. If there are defects exceeding the number of redundant bits 12a in the memory cells of the memory cell array 11a of the memory macro 10a, the memory macro 10a is determined to be failed. The determination is similarly performed in the memory macros 10b to 10n.

  FIG. 5 is a diagram illustrating an example of a test result of a semiconductor device subjected to a high temperature test. In the figure, the high temperature test results in each of the test blocks T / B1 to T / B10 of the semiconductor device are shown. The test block indicates a block of the semiconductor device on which the test determination is performed, and there are ten test blocks in the example of the figure. The test blocks correspond to the memory macros 10a, 10b,..., 10n of the semiconductor device in FIG. 2 (in this case, there are 10 memory macros 10a, 10b,..., 10n), and the memory macros 10a, 10b,. The test result in 10n is shown.

  For example, test block T / B1 indicates that the high-temperature test has been passed (indicated as PASS in the figure). In the test block T / B3, it is indicated that the location where the defect has occurred can be relieved by redundancy (in the figure, it is indicated as redundant). In the test block T / B2, the number of locations where defects have occurred is larger than the number that can be relieved by redundancy, indicating a failure (indicated as FAIL in the figure). That is, it is indicated that all the defects of the memory macro cannot be relieved even by redundancy.

The test block T / B3 and test block T / B6 of the resulting semiconductor device shown in FIG. 5 are subjected to redundancy processing, and the defective memory cell is relieved. Then, a room temperature test is performed.
FIG. 6 is an example showing a test result of a normal temperature test of the semiconductor device subjected to the high temperature test of FIG. The test blocks T / B3 and T / B6 shown in FIG. 5 pass in the room temperature test as shown in FIG. 6 by switching to the redundant bits. On the other hand, since the environmental conditions of the normal temperature test are looser than the high temperature test, as indicated by the test block T / B2 in FIG. 5, what was a failure in the high temperature test is different from the pass in the normal temperature test as shown in FIG. May be. For example, a margin defect may occur only in a high temperature test.

  When 8 or more of the 10 test blocks (memory macros 10a, 10b,..., 10n) are passes, if the semiconductor device is a semi-defective product, the semiconductor device of FIGS. However, as shown in FIG. 6, all the memory macros are passed in the room temperature test, and therefore, it is determined as a non-defective product.

  However, since the pass / fail judgment fuse circuits 13a, 13b,..., 13n can know the test results of the memory macros 10a, 10b,..., 10n at the time of the high temperature test, this result is used as the final result. To do. That is, even if the pass result is obtained in the normal temperature test, the pass / fail judgment fuse circuits 13a, 13b,..., 13n are read, so that the memory macros 10a, 10b,. Judge that.

  FIG. 7 is an example showing a test result of a normal temperature test of the semiconductor device which has been subjected to the high temperature test of FIG. As shown in FIG. 7, even if the test result of the test block T / B2 that has failed (in the high temperature test) in FIG. 5 is determined to be a pass in the room temperature test as shown in FIG. Is determined as a failure. Accordingly, it is possible to appropriately determine that the semiconductor device is a semi-defective product without determining that the semiconductor device is a good product.

Next, a test flow of the semiconductor device shown in FIG. 2 will be described using a flowchart.
FIG. 8 is a flowchart showing a test flow of the semiconductor device. The test of the semiconductor device is performed according to the following procedure.

  In step S1, PT1 (primary test 1: high temperature test) of the semiconductor device shown in FIG. 2 is performed. The scan circuit shown in FIG. 3 reads data from the memory macros 10a, 10b,..., 10n and obtains a test result of PT1.

  In step S2, it is determined in each of the memory macros 10a, 10b,..., 10n whether there is no defect in the memory cells of the memory cell arrays 11a, 11b,. In addition, even if a defect exists in the memory cell, it is determined by the redundant bits 12a, 12b,..., 12n whether all defective memory cells in the memory cell arrays 11a, 11b,. Also, it is determined whether all defective memory cells cannot be relieved by the redundant bits 12a, 12b,.

  As described above, in step S2, determination is performed in each of the memory macros 10a, 10b,. Therefore, when it is determined that a certain memory macro passes, the process proceeds to step S5 in the memory macro.

  If it is determined in a memory macro that all of the generated defective memory cells can be relieved with redundant bits, the memory macro proceeds to step S3, and the memory macros 10a, 10b, The defective memory cells of .about.10n are repaired by switching to redundant bits 12a, 12b,.

  If it is determined in a certain memory macro that all of the generated defective memory cells cannot be relieved with redundant bits, the memory macro proceeds to step S4, and the memory macro 10a, The fuses of the pass / fail judgment fuse circuits 13a, 13b,..., 13n of 10b,.

When the processes of steps S2 to S4 are performed, the process of step S5 is performed. In step S5, the semiconductor device PT2 (primary test 2: normal temperature test) is performed.
In step S6, it is determined whether the product is defective, non-defective or semi-defective. That is, if a predetermined number or more of failures have occurred in the memory macros 10a, 10b,..., 10n by PT2, it is determined that the product is defective and the process proceeds to step S12. In this way, after the normal temperature test, defective products are removed in advance, and the remaining products are determined as good or semi-defective, thereby shortening the test time of the semiconductor device. The result of PT2 can be obtained by reading data with the scan circuit shown in FIG.

  In step S7, in each of the memory macros 10a, 10b,..., 10n, it is determined whether the memory cells of the memory cell arrays 11a, 11b,. Further, in each of the memory macros 10a, 10b,..., 10n, it is determined whether a defect has occurred in the memory cells of the memory cell arrays 11a, 11b,.

  As described above, in step S7, each of the memory macros 10a, 10b,. Therefore, if it is determined that a certain memory macro has passed, the process proceeds to step S8 in that memory macro. If it is determined that a memory macro has failed, the process proceeds to step S10 in that memory macro. In all the memory macros 10a, 10b,..., 10n, when the processes of steps S7 to S10 are performed, the process of step S11 is performed.

  In step S8, pass / fail judgments of the fuse macros 13a, 13b,..., 13n of the memory macros 10a, 10b,. The pass / fail judgment of the pass / fail judgment fuse circuits 13a, 13b,..., 13n can be obtained from the data read by the scan circuit shown in FIG. When the pass / fail determination fuse circuits 13a, 13b,..., 13n indicate a path, the process proceeds to step S9. If a failure is indicated, the process proceeds to step S10.

In step S9, it is determined that the memory macros 10a, 10b,.
In step S10, it is determined that the memory macros 10a, 10b,.

  As described above, the test results of the memory macros 10a, 10b,..., 10n including the determination in the high temperature test are obtained. That is, a memory macro that has failed in the high-temperature test is determined to be failed even if it passes the normal temperature test.

  In step S11, the number of passed memory macros 10a, 10b,..., 10n with respect to the total number of memory macros 10a, 10b,. And it progresses to step S12-S14 according to the count number with respect to all the numbers.

  For example, the total number of memory macros 10a, 10b,. As a result of the test, if all the memory macros pass, in order to make a non-defective product determination, the process proceeds to step S13. Even if all the memory macros do not pass, if it passes 8 or more, it is determined as a semi-defective product. Proceed to step S14. If the path is 8 or less, the process proceeds to step S12 in order to determine a defective product.

  As described above, when a failure is determined in the high temperature test, information indicating that is written in the pass / fail determination fuse circuits 13a, 13b,..., 13n. As a result, even if the circuit block determined to fail in the high temperature test passes in the normal temperature test, it has failed in the high temperature test by referring to the pass / fail determination fuse circuits 13a, 13b,..., 13n. It is possible to recognize the non-defective product, the semi-defective product, and the defective product of the semiconductor device.

(Supplementary Note 1) In a semiconductor device testing method for testing a semiconductor device in the order of a high temperature test and a room temperature test,
Write the high temperature test result of the high temperature test of the circuit block to the high temperature test result information portion provided in each of the plurality of circuit blocks,
Based on the high temperature test result written in the high temperature test result information section and the normal temperature test result of the normal temperature test of the circuit block, the pass / fail judgment of the circuit block is performed.
A method for testing a semiconductor device.

  (Supplementary Note 2) In the semiconductor device according to Supplementary Note 1, wherein the pass / fail judgment of the circuit block is judged as a failure when the room temperature test result is acceptable but the high temperature test result is failed. Test method.

  (Additional remark 3) When all the said circuit blocks pass, the said semiconductor device is determined to be non-defective, and when the predetermined number of circuit blocks have passed, the said semiconductor device is determined to be a semi-defective product. Semiconductor device testing method.

  (Additional remark 4) In the said high temperature test result information part, the said high temperature test result is written according to whether all the defective parts which generate | occur | produced in the said circuit block were relieved by the redundant part. The test method of the semiconductor device as described.

(Additional remark 5) The said high temperature test result information part has a fuse, The said high temperature test result is written by the cutting | disconnection of the said fuse, The test method of the semiconductor device of Claim 1 characterized by the above-mentioned.
(Supplementary note 6) The semiconductor device testing method according to supplementary note 1, wherein the normal temperature test is not performed when a predetermined number of failures occur in the circuit block by the high temperature test.

(Appendix 7) In a semiconductor device in which tests are performed in the order of a high temperature test and a normal temperature test,
A plurality of circuit blocks;
A high-temperature test result information section in which a high-temperature test result of the high-temperature test is written, the pass / fail judgment of the circuit block is performed based on the normal-temperature test result of the normal-temperature test,
A semiconductor device comprising:

It is the figure which showed the outline | summary of the semiconductor device. It is a figure showing an example of composition of a semiconductor device. It is the figure which showed the scan circuit of the memory macro. It is the figure which showed the scan circuit of the pass / fail judgment fuse circuit. It is a figure of an example which showed the test result of the semiconductor device which performed the high temperature test. It is an example which showed the test result of the normal temperature test of the semiconductor device which performed the high temperature test of FIG. It is an example which showed the test result of the normal temperature test of the semiconductor device which performed the high temperature test of FIG. 5 considering the result of the pass / fail judgment fuse circuit. It is a flowchart which shows the flow of a test of a semiconductor device. It is a figure of an example which showed the test result of the semiconductor device which performed the high temperature test. It is an example which showed the test result of the normal temperature test of the semiconductor device which performed the high temperature test of FIG.

Explanation of symbols

1a, 1b,..., 1n circuit block 2a, 2b,.

Claims (5)

In the semiconductor device testing method for testing semiconductor devices in the order of high temperature test and normal temperature test,
Write the high temperature test result of the high temperature test of the circuit block to the high temperature test result information portion provided in each of the plurality of circuit blocks,
Based on the high temperature test result written in the high temperature test result information section and the normal temperature test result of the normal temperature test of the circuit block, the pass / fail judgment of the circuit block is performed.
A method for testing a semiconductor device.   The test method for a semiconductor device according to claim 1, wherein the pass / fail determination of the circuit block is determined to be rejected when the high-temperature test result is rejected even if the room temperature test result is pass.   2. The semiconductor device according to claim 1, wherein when all the circuit blocks pass, the semiconductor device is determined as a non-defective product, and when the predetermined number of circuit blocks passes, the semiconductor device is determined as a semi-defective product. Test method.   2. The semiconductor according to claim 1, wherein the high-temperature test result information section is written with the high-temperature test result according to whether or not all defective portions generated in the circuit block have been relieved by a redundant portion. Equipment test method.   2. The method of testing a semiconductor device according to claim 1, wherein the high temperature test result information section has a fuse, and the high temperature test result is written by cutting the fuse.

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