JP2006209946A - Ram冗長集積回路をテストするための方法およびシステム - Google Patents
Ram冗長集積回路をテストするための方法およびシステム Download PDFInfo
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- JP2006209946A JP2006209946A JP2006013557A JP2006013557A JP2006209946A JP 2006209946 A JP2006209946 A JP 2006209946A JP 2006013557 A JP2006013557 A JP 2006013557A JP 2006013557 A JP2006013557 A JP 2006013557A JP 2006209946 A JP2006209946 A JP 2006209946A
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- redundant
- integrated circuit
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/143—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using laser-fusible links
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
- G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
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- Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Tests Of Electronic Circuits (AREA)
- Static Random-Access Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
【解決手段】パッケージ化されたランダムアクセスメモリ(RAM)冗長集積回路ダイ(50,62)をテストするシステム及び方法は、パッケージ化されたランダムアクセスメモリ冗長集積回路ダイの冗長RAM内の故障している要素を識別するステップ(ステップB5)と、故障している要素をパッケージ化されたランダムアクセスメモリ冗長集積回路ダイの冗長RAM内の冗長要素で置き換えるステップ(ステップB6)を含む。
【選択図】図4
Description
52 ウェーハ
54 テスタユニット
58 プログラマ機能
70 テスト信号発生器
Claims (10)
- パッケージ化ランダムアクセスメモリ(RAM)冗長集積回路ダイ(50、62)をテストする方法であって、
前記パッケージ化集積回路ダイの冗長RAM内の不良素子を識別するステップ(ステップB5)と、
前記不良素子を、前記パッケージ化集積回路ダイの冗長RAM内の冗長素子で置き換えるステップ(ステップB6)
を含む、方法。 - 前記識別するステップと置き換えるステップが繰り返される(ステップB7)、請求項1に記載の方法。
- 前記識別するステップと置き換えるステップを、前記パッケージ化集積回路ダイの前記冗長RAM内に不良素子がある限り繰り返すステップ(ステップB7)を含む、請求項1に記載の方法。
- 前記識別するステップと置き換えるステップを、不良素子を置き換えるための冗長素子が前記冗長RAM内においてなくなるまで繰り返すステップ(ステップB7)を含む、請求項1に記載の方法。
- 前記置き換えるステップが、前記パッケージ化集積回路ダイの前記冗長RAM内のヒューズを電気的に飛ばして、前記不良素子を冗長素子で置き換えるステップを含む、請求項1に記載の方法。
- 前記置き換えるステップが、記憶セルの不良の行を、前記集積回路ダイの前記冗長RAM内の記憶セルの冗長な行で置き換えるステップを含む、請求項1に記載の方法。
- 前記置き換えるステップが、記憶セルの不良の列を、前記集積回路ダイの前記冗長RAM内の記憶セルの冗長な列で置き換えるステップを含む、請求項1に記載の方法。
- パッケージ化ランダムアクセスメモリ(RAM)冗長集積回路ダイ(50、62)をテストするためのシステムであって、
前記パッケージ化集積回路ダイに結合され、前記パッケージ化集積回路ダイの冗長RAM内の不良素子を識別するように動作する(ステップB5)テスタユニット(70)と、
前記テスタユニットとパッケージ化集積回路ダイ(72〜86)に結合され、前記不良素子を前記パッケージ化集積回路ダイの前記冗長RAM内の冗長素子で置き換えるように動作する(ステップB6)プログラマ(80)
を備える、システム。 - 前記プログラマが、前記パッケージ化集積回路ダイの前記冗長RAM内のヒューズを電気的に飛ばして、前記不良素子を冗長素子で置き換えるように動作する、請求項8に記載のシステム。
- 前記プログラマが前記テスタユニットと一体である、請求項8に記載のシステム。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/043,377 US7284168B2 (en) | 2005-01-26 | 2005-01-26 | Method and system for testing RAM redundant integrated circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2006209946A true JP2006209946A (ja) | 2006-08-10 |
Family
ID=36698479
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2006013557A Pending JP2006209946A (ja) | 2005-01-26 | 2006-01-23 | Ram冗長集積回路をテストするための方法およびシステム |
Country Status (2)
Country | Link |
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US (1) | US7284168B2 (ja) |
JP (1) | JP2006209946A (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2015133982A1 (en) * | 2014-03-03 | 2015-09-11 | Hewlett-Packard Development Company, L.P. | Dram row sparing |
US9653184B2 (en) * | 2014-06-16 | 2017-05-16 | Sandisk Technologies Llc | Non-volatile memory module with physical-to-physical address remapping |
US9613715B2 (en) | 2014-06-16 | 2017-04-04 | Sandisk Technologies Llc | Low-test memory stack for non-volatile storage |
US9606882B2 (en) | 2014-07-17 | 2017-03-28 | Sandisk Technologies Llc | Methods and systems for die failure testing |
Family Cites Families (28)
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US5570032A (en) * | 1993-08-17 | 1996-10-29 | Micron Technology, Inc. | Wafer scale burn-in apparatus and process |
US5841712A (en) * | 1996-09-30 | 1998-11-24 | Advanced Micro Devices, Inc. | Dual comparator circuit and method for selecting between normal and redundant decode logic in a semiconductor memory device |
US5764577A (en) * | 1997-04-07 | 1998-06-09 | Motorola, Inc. | Fusleless memory repair system and method of operation |
US6154851A (en) * | 1997-08-05 | 2000-11-28 | Micron Technology, Inc. | Memory repair |
US5920515A (en) * | 1997-09-26 | 1999-07-06 | Advanced Micro Devices, Inc. | Register-based redundancy circuit and method for built-in self-repair in a semiconductor memory device |
US6016264A (en) * | 1998-05-26 | 2000-01-18 | Vanguard International Semiconductor Corporation | Antifuse programming and detecting circuit |
US6233184B1 (en) * | 1998-11-13 | 2001-05-15 | International Business Machines Corporation | Structures for wafer level test and burn-in |
US6367042B1 (en) * | 1998-12-11 | 2002-04-02 | Lsi Logic Corporation | Testing methodology for embedded memories using built-in self repair and identification circuitry |
KR100319893B1 (ko) * | 1999-07-01 | 2002-01-10 | 윤종용 | 리던던시 메모리 셀 블락을 선택적으로 차단하여 테스트함으로써 불량 메모리 셀의 위치 판별이 용이한 반도체 메모리 장치 |
US6288436B1 (en) * | 1999-07-27 | 2001-09-11 | International Business Machines Corporation | Mixed fuse technologies |
US6363020B1 (en) * | 1999-12-06 | 2002-03-26 | Virage Logic Corp. | Architecture with multi-instance redundancy implementation |
DE10005618A1 (de) * | 2000-02-09 | 2001-08-30 | Infineon Technologies Ag | Integrierter Halbleiterspeicher mit redundanter Einheit von Speicherzellen |
DE10063685A1 (de) * | 2000-12-20 | 2002-07-18 | Infineon Technologies Ag | Schaltungsanordnung zur Ansteuerung einer programmierbaren Verbindung |
US6570805B2 (en) * | 2000-12-20 | 2003-05-27 | Actel Corporation | Antifuse memory cell and antifuse memory cell array |
JP2002217295A (ja) * | 2001-01-12 | 2002-08-02 | Toshiba Corp | 半導体装置 |
US6674667B2 (en) * | 2001-02-13 | 2004-01-06 | Micron Technology, Inc. | Programmable fuse and antifuse and method therefor |
US6691252B2 (en) * | 2001-02-23 | 2004-02-10 | Hewlett-Packard Development Company, L.P. | Cache test sequence for single-ported row repair CAM |
DE10126599C2 (de) * | 2001-05-31 | 2003-12-18 | Infineon Technologies Ag | Speicherbaustein, Verfahren zum Aktivieren einer Speicherzelle und Verfahren zum Reparieren einer defekten Speicherzelle |
US6570806B2 (en) * | 2001-06-25 | 2003-05-27 | International Business Machines Corporation | System and method for improving DRAM single cell fail fixability and flexibility repair at module level and universal laser fuse/anti-fuse latch therefor |
US6621324B2 (en) * | 2002-02-19 | 2003-09-16 | International Business Machines Corporation | Redundant antifuse segments for improved programming efficiency |
JP3866588B2 (ja) * | 2002-03-01 | 2007-01-10 | エルピーダメモリ株式会社 | 半導体集積回路装置 |
US6580156B1 (en) * | 2002-04-04 | 2003-06-17 | Broadcom Corporation | Integrated fuse with regions of different doping within the fuse neck |
US6828652B2 (en) * | 2002-05-07 | 2004-12-07 | Infineon Technologies Ag | Fuse structure for semiconductor device |
US6751150B2 (en) * | 2002-08-29 | 2004-06-15 | Micron Technology, Inc. | Circuits and method to protect a gate dielectric antifuse |
JP2004206756A (ja) * | 2002-12-24 | 2004-07-22 | Toshiba Corp | 半導体装置 |
US6876594B2 (en) * | 2002-12-26 | 2005-04-05 | Texas Instruments Incorporated | Integrated circuit with programmable fuse array |
KR100506978B1 (ko) * | 2003-02-25 | 2005-08-09 | 삼성전자주식회사 | 휘발성 반도체 메모리의 제조공정에서 제조된 불휘발성메모리 셀 트랜지스터를 퓨즈소자로서 갖는 반도체 집적회로장치 |
US6928011B2 (en) * | 2003-07-30 | 2005-08-09 | Texas Instruments Incorporated | Electrical fuse control of memory slowdown |
-
2005
- 2005-01-26 US US11/043,377 patent/US7284168B2/en not_active Expired - Fee Related
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2006
- 2006-01-23 JP JP2006013557A patent/JP2006209946A/ja active Pending
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Publication number | Publication date |
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US7284168B2 (en) | 2007-10-16 |
US20060168488A1 (en) | 2006-07-27 |
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