JP2006186038A - Resistor chip and its packaging method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a resistor chip where thin film resistors are stacked in high density. <P>SOLUTION: There are stacked on a silicon substrate 1 a plurality of layers of a thin film resistor group separated up and down. The thin film grouped resistors of each layer comprise a plurality of band-shaped thin film resistors 3-1 to 3-4 arranged in parallel on the same flat plane. The plurality of the thin film resistors 3-1 to 3-4 for every layer are covered respectively with the interlayer insulating films 4-1 to 4-4 of each layer. A plurality of plugs 6 are connected respectively to the plurality of the thin film resistors 7 of each layer, penetrate a plurality of layers of the interlayer insulating films 4-1 to 4-4 up and down, and derived onto the surface of the uppermost interlayer insulating film 4-4. To upper ends of the plurality of the plugs 6 there are joined pads 7 (7, 7-1a, 7-1b to 7-4a, 7-4b), respectively. The plurality of the pads 7 are separately disposed on the uppermost interlayer insulating film 4-4. The uppermost interlayer insulating film 4-4 is covered with a passivation film 8 excepting the pad 7. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a thin resistor component which is one of thin passive components, and more particularly to a resistor chip in which thin film resistors are stacked at a high density and a mounting method thereof.

  Conventionally, as a technique for laminating thin passive components, for example, there are those described in the following documents.

Kanno et al., “Development of integrated passive devices”, 17th Electronics Packaging Conference, March 2003, 13B-16, p. 177-178 Masu Okada "High-frequency passive device technology on silicon", Applied Physics, September 2004, Vol. 73, No. 9, p. 1172-1178

  As shown in Non-Patent Document 1, the recent downsizing of electronic devices is rapid, and in particular, mobile devices typified by mobile phones are highly demanded for miniaturization and light weight, and are highly functional. The demand for is also increasing. A device including a radio frequency (RF) transmission / reception circuit circuit such as a cellular phone is equipped with many passive components such as a capacitor, a resistor, and an inductor. The proportion of passive components in the current mounting area accounts for about 60%, which is a major obstacle to miniaturization.

  Further, as shown in Non-Patent Document 2, development of mounting a high-frequency passive component on silicon is also progressing.

  The conventional passive component is a single component and has a certain size and thickness, so there is no mounting method other than surface mounting, so the only way to reduce the mounting area is to reduce the size of the component, Miniaturization has been promoted in that direction. However, the miniaturization is approaching the limit, and the physical properties are approaching the limit. Furthermore, with the miniaturization of parts, mounters (mounting machines) for mounting parts cannot be used.

  In other words, since a passive component has a certain size and thickness, it must be mounted on the surface in a planar manner. It cannot cope with the increase in the number of parts. Miniaturization of parts has reached the limit, and even if it can be reduced beyond this limit, it is too small to be handled (gripped) by the mounter.

  An object of the present invention is to provide a thin resistor chip in which many resistors are mounted in a small mounting area, and a mounting method thereof, without the above limitation.

  The resistor chip of the present invention includes a substrate, a thin film resistor group in which a plurality of strip-like thin film resistors arranged in parallel on the same plane are stacked on the substrate in a vertically separated manner, and each of the layers A plurality of interlayer insulating films respectively covering a plurality of thin film resistors, and a plurality of plugs arranged separately in the lateral direction and respectively connected to the plurality of thin film resistors of the respective layers, A plurality of plugs extending vertically through the interlayer insulating film of the layer and drawn to the surface of the uppermost interlayer insulating film, and respectively joined to upper ends of the plurality of plugs, on the uppermost interlayer insulating film And a plurality of electrodes spaced apart from each other.

  In the resistor chip of the present invention, the uppermost interlayer insulating film may be covered with a passivation film with the plurality of electrodes exposed. A stopper insulating film may be formed on the lower surface of the plurality of thin film resistors of each layer. A conductive post may be erected on each of the electrodes. Further, a rewiring layer connected to the plurality of electrodes and disposed on the passivation film, a plurality of pads connected to the rewiring layer and disposed at predetermined plane positions, and the plurality of pads exposed. An insulating film that covers the rewiring layer may be provided in the state of being made to be.

  In the resistor chip mounting method of the present invention, the resistor chip is used, and another chip is mounted on the surface opposite to the surface on which the solder balls are formed. Other resistor chips may be mounted in the element mounting region using the resistor chip. Further, the resistor chip may be used to thin the substrate by back grinding (bottom surface polishing) and embedded in another substrate including a printed circuit board.

  According to the first, second, eleventh and twelfth aspects of the present invention, since there are a plurality of resistors having respective resistance values in each layer, a plurality of resistors can be obtained with one resistor chip. it can. Further, if the substrate is thinned by back grinding, the entire thickness of the resistor chip can be easily reduced to, for example, several tens of μm. When such a thin resistor chip is used, a plurality of resistors can be mounted at a time, so that the mounting area can be reduced and the mounting cost can also be reduced.

  According to the invention of claim 3, since each stopper insulating film is formed under the resistor of each layer, over-etching can be prevented when a contact hole for providing a plug is formed.

  According to the invention of claim 4, since the post is provided on the electrode, the resistor chip is embedded in the substrate and the electrode can be drawn out by the post, and the surface mounting area of other components can be increased.

  According to the inventions according to claims 5 and 6, since the pads are rearranged by the rewiring layer, the pads can be rearranged in a uniform state from the state where the pads are unevenly distributed in the chip peripheral portion, and the adjacent distance between the pads is Become wider. Thereby, mounting using a solder ball etc. is attained.

  According to the seventh aspect of the present invention, another small chip or the like can be mounted on the element mounting region without a pad, and the mounting area can be reduced.

  According to the invention which concerns on Claim 8, many resistors with the same resistance value can be integrated | stacked by making the length of a resistor the same, for example. In addition, the design of the resistors is the same for each layer, and the arrangement positions are different, so that the design is facilitated.

  According to the ninth and tenth aspects of the present invention, the resistance value can be adjusted to be different by adjusting the doping amount of ions to the polysilicon of each layer. In addition, the degree of freedom in designing the number of resistors having which resistance value is increased.

  According to the thirteenth aspect of the present invention, since the resistor chip can be firmly connected to the substrate or the like by the solder ball, another chip can be mounted on the resistor chip, and the mounting area can be effectively utilized.

  According to the fourteenth aspect of the present invention, the mounting area can be effectively used by mounting another chip in the element mounting region.

  According to the fifteenth aspect of the present invention, the entire resistor chip can be thinned by thinning the substrate, and a thin component-embedded printed circuit board with a laminated structure can be easily manufactured.

  The resistor chip of the best mode for carrying out the present invention has a substrate, and a plurality of thin film resistor groups are stacked on the substrate so as to be spaced apart from each other in the vertical direction. The thin film resistor group of each layer is composed of a plurality of strip-like thin film resistors arranged in parallel on the same plane. The plurality of thin film resistors for each layer are covered with an interlayer insulating film of each layer. The plurality of plugs spaced apart in the horizontal direction are connected to the plurality of thin film resistors in each layer, respectively, penetrate the plurality of interlayer insulating films vertically, and are drawn to the surface of the uppermost interlayer insulating film. Yes. Electrodes are joined to the upper ends of the plurality of plugs, respectively, and the plurality of electrodes are arranged separately on the uppermost interlayer insulating film. The uppermost interlayer insulating film is covered with a passivation film with a plurality of electrodes exposed.

(Constitution)
1A and 1B are schematic configuration diagrams of a resistor chip showing Example 1 of the present invention. FIG. 1A is a plan view seen from the surface, and FIG. It is a longitudinal cross-sectional view.

  This resistor chip has a laminated structure with a total thickness of, for example, 100 μm or less, preferably 50 μm or less, and the bottom surface is thinned by back grinding (for example, 100 μm or less, preferably 50 μm or less). A silicon substrate 1 is provided. A protective insulating film 2 made of an oxide film (SiO 2) is deposited on the silicon substrate 1, and a plurality of layers (for example, four layers) of thin film resistors are formed on the protective insulating film 2. Are laminated via inter-layer insulating films 4-1 to 4-4.

  The thin film resistor group of each layer is formed by a polysilicon film into which ions such as boron or arsenic are implanted. For example, the polysilicon film becomes p-type by boron implantation and becomes n-type by arsenic implantation. The first-layer thin film resistor group is configured by arranging a plurality of strip-shaped thin film resistors 3-1 having the same length L1 in parallel on the same plane. Similarly, the second thin film resistor group is a plurality of strip thin film resistors 3-2 having the same length L2, and the third thin film resistor group is a plurality of strip thin film resistors 3- having the same length L3. 3, the fourth-layer thin film resistor group is constituted by a plurality of strip-shaped thin film resistors 4-2 having the same length L4. The lengths L1, L2, L3, and L4 of the resistors 3-1 to 3-4 in the respective layers are different, for example, L1> L2> L3> L4.

  A plurality of contact holes 5 spaced apart are formed in the vertical direction located at one end and the other end of the resistors 3-1 to 3-4 of each layer, and tungsten (W ) Etc. are embedded to form a plurality of plugs 6. The upper end surfaces of the plurality of plugs 6 are positioned on the same plane as the surface of the fourth-layer interlayer insulating film 4-1, and a plurality of electrodes (for example, pad) made of aluminum are formed on the upper end surfaces of the plugs 6. 7-1a, 7-1b to 7-4a, 7-4b are formed.

  The pad 7-1a is connected to one end of the first-layer resistor 3-1 through the plug 6, and the pad 7-1b spaced apart from the pad 7-1a is connected to the other end of the first-layer resistor 3-1 through the plug 6. It is connected to the. Similarly, the pads 7-2a and 7-2b are connected to one end and the other end of the resistor 3-2 in the second layer through each plug 6, and the pads 7-3a and 7-3b are connected to each plug 6 respectively. Are connected to one end and the other end of the third layer resistor 3-3, and the pads 7-4a and 7-4b are connected to one end and the other end of the fourth layer resistor 3-4 through each plug 6. Has been. The fourth interlayer insulating film 4-4 is covered with a passivation film (hereinafter referred to as "PV film") 8 which is an inactive film such as a nitride film (SiN), and each pad 7- Openings 9 are formed only at 1a, 7-1b to 7-4a, 7-4b, and the pads 7-1a, 7-1b to 7-4a, 7-4b are exposed.

(Production method)
The resistor chip of FIG. 1 is manufactured by the following process, for example.
First, the silicon substrate 1 is heated while flowing water vapor to form the protective insulating film 2 made of an oxide film. A first polysilicon film is formed thereon and ions such as boron or arsenic are implanted. The ion dose (implantation amount) at this time is adjusted according to the target resistance value. A plurality of thin film resistors 3 each having a linear strip shape are formed by spin-coating (rotating coating) a resist on the polysilicon film and curing (heat treatment), and then etching the polysilicon film after patterning the resist by photolithography. -1. Next, a first interlayer insulating film 4-1 made of an oxide film is formed on the plurality of thin film resistors 3-1 by, for example, CVD (chemical vapor deposition) using plasma TEOS. . Thereafter, annealing (heat treatment) is performed.

  On the first interlayer insulating film 4-1, a polysilicon film is formed in the second layer in the same manner as described above, ions such as boron are implanted, and patterning is performed using a photolithography technique. A plurality of thin film resistors 3-2 are formed. The only difference from the first layer is that the pattern of the thin film resistor 3-2 is short. Thereafter, in the same manner as described above, a second interlayer insulating film 4-2 made of an oxide film is formed.

  A plurality of third-layer thin film resistors 3-3 are formed on the interlayer insulating film 4-2 in the same manner as described above. In this case, the process is exactly the same except that the length of the resistor 3-3 is shorter than that of the second layer. Further, a third interlayer insulating film 4-3 made of an oxide film is formed thereon.

  On the interlayer insulating film 4-3, a plurality of fourth-layer thin film resistors 3-4 are formed in the same manner as described above. In this case, the process is exactly the same except that the length of the resistor 3-4 is shorter than that of the third layer. Further, a fourth interlayer insulating film 4-4 made of an oxide film is formed thereon.

  After applying and curing a resist on the interlayer insulating film 4-4, the resist is removed only at the positions of both ends of the resistors 3-1 to 3-4 of each layer by photolithography. Contact holes 5 are opened in the interlayer insulating films 4-1 to 4-4 located at both ends of the resistors 3-1 to 3-4 of each layer with an oxide film etcher (removal device). A barrier film made of titanium or the like is formed in the contact hole 5 and, for example, a tungsten plug 6 is buried by a CVD method. Next, polishing is performed by a CMP apparatus (chemical mechanical polishing apparatus) until there is no tungsten on the interlayer insulating film 4-4.

  An aluminum film is formed on the polished interlayer insulating film 4-4 by sputtering. Using an photolithography technique, the aluminum film other than on the plug 6 is etched to form pads 7-1a, 7-1b to 7-4a, 7-4b. A PV film 8 such as a nitride film is formed on the pads 7-1a, 7-1b to 7-4a, 7-4b. A resist is applied on the PV film 8, and the PV film 8 on the pads 7-1a, 7-1b to 7-4a, 7-4b is removed by etching using a photolithography technique. Through the above steps, a resistor array having the structure of FIG. 1 is formed.

  In such a resistor array, a plurality of resistor chips having a plurality of resistance values are obtained by the resistors 3-1 to 3-4 formed in multiple layers. This resistor chip is back-ground to form a thin film, and is separated into pieces by dicing (cutting). Thereafter, at the time of mounting, for example, die bonding (fixing) is performed on a printed circuit board or the like, and the pads 7-1a, 7-1b to 7-4a, 7-4b of the die-bonded resistor chips are required. By connecting to other parts by wire bonding (wire connection) or the like, a desired circuit operation can be performed.

(effect)
In Example 1, the following effects (a) and (b) are obtained. (A) Since a plurality of resistors 3-1 to 3-4 having respective resistance values exist in each layer, 1 A plurality of resistors 3-1 to 3-4 can be obtained with one resistor chip.

  (B) Since the substrate 1 is thinned by back grinding, the entire thickness of the resistor chip can be easily reduced to, for example, several tens of μm. When such a thin resistor chip is used, a plurality of resistors 3-1 to 3-4 can be mounted at a time, so that the mounting area can be reduced and the mounting cost can also be reduced.

(Configuration / Manufacturing method)
FIG. 2 is a schematic longitudinal sectional view of a resistor chip showing Embodiment 2 of the present invention. Elements common to those in FIG. 1 showing Embodiment 1 are denoted by common reference numerals.

  In Example 2, before forming the polysilicon film for the thin film resistor of each layer in Example 1, the underlying interlayer insulating films 4-1 to 4-4 are flattened by CMP and formed thereon. After forming the stopper insulating films 10-1 to 10-4 such as nitride films by the CVD method, the polysilicon film for the thin film resistor of each layer is formed to form the thin film resistor group of each layer Only the difference is from the first embodiment. Other configurations and manufacturing methods are almost the same as those in the first embodiment.

(effect)
In the second embodiment, in addition to the effects of the first embodiment, there are the following effects (c) and (d).
(C) Since the bottom of the polysilicon resistors 3-1 to 3-4 of each layer is flattened by CMP, the processing accuracy of the resistors 3-1 to 3-4 is improved.

  (D) Since the stopper insulating films 10-1 to 10-4 are formed under the polysilicon resistors 3-1 to 3-4 of the respective layers, over-etching occurs when the contact holes 5 are formed. However, there is no possibility that the lower insulating films 2, 4-1 to 4-3 are etched. That is, over-etching can be prevented by the stopper insulating films 10-1 to 10-4.

(Configuration / Manufacturing method)
FIG. 3 is a schematic longitudinal sectional view of a resistor chip showing Embodiment 3 of the present invention. Elements common to those in FIG. 2 showing Embodiment 2 are denoted by common reference numerals.

  In the third embodiment, a nickel-phosphorous (NiP) film 11 and a copper (Cu) film 12 are plated on the aluminum pads 7-1a, 7-1b to 7-4a, 7-4b in the second embodiment. Then, the silicon substrate 1 is thinned to about 50 μm by the back grinding method. Other configurations and manufacturing methods are substantially the same as those in the second embodiment.

(Implementation example)
FIG. 4 is a schematic longitudinal sectional view showing an example of mounting the resistor chip 20 of FIG. 3 on the substrate.

  For example, when the resistor chip 20 of FIG. 3 is embedded in a substrate 21 such as a printed circuit board, the resistor chip 20 is fixed on the substrate 21 and then the entire surface is covered with the resin insulating film 22. Via holes 23 are formed in the resin insulating film 22 on the pads 7-1a, 7-1b to 7-4a, 7-4b by a carbon dioxide laser or the like, and the copper posts 24 are formed by plating. Since the copper film 12 is formed on the upper surfaces of the pads 7-1a, 7-1b to 7-4a, 7-4b, plating is easy and conduction with the copper post 24 can be achieved.

(effect)
The third embodiment has the following effect (e) in addition to the effects of the first and second embodiments.
(E) Since the resistor chip 20 is embedded in the substrate 21, the surface mounting area of other components increases. In the mounting example of FIG. 4, the resistor chip 20 is mounted on the substrate 21. Instead of this, a housing recess is provided in the substrate 21, and the resistor chip 20 is embedded in the housing recess. Also good. Thereby, the whole thickness can be made thin.

(Configuration / Manufacturing method)
5 (a) and 5 (b) are schematic configuration diagrams of a resistor chip showing Example 4 of the present invention. FIG. 5 (a) is a plan view seen from the surface, and FIG. FIG. In FIG. 5, elements common to the elements in FIG. 1 illustrating the first embodiment are denoted by common reference numerals.

  In Example 1 of FIG. 1, polysilicon thin film resistors 3-1 to 3-4 having different lengths are provided for each layer. In Example 4, polysilicon thin film resistor 3A of each layer is provided. -1 to 3A-4 have the same length. Other configurations and manufacturing methods are almost the same as those in the first embodiment.

(effect)
The fourth embodiment has the following effects (f) and (g) in addition to the effects of the first to third embodiments.
(F) Since the polysilicon thin film resistors 3A-1 to 3A-4 of the respective layers have the same length, a large number of resistors 3A-1 to 3A-4 having the same resistance value can be integrated. Further, by adjusting the doping amount of ions in the polysilicon of each layer, it is possible to adjust to different resistance values.

  (G) Since the design of the resistors 3A-1 to 3A-4 is the same for each layer and the arrangement positions are different, the design is facilitated. Further, since the resistance value is adjusted by ion implantation (implantation), the degree of freedom in designing which resistance value and how many resistors are prepared is increased.

  In the fifth embodiment, a WCSP (wafer level chip size package) in which the resistor chip 20 of the first, second, or fourth embodiment is packaged will be described.

  The WCSP performs rewiring with copper on an upgraded wafer. In a normal IC chip (integrated circuit chip), pads are arranged on the periphery of the chip. On the other hand, in the WCSP, the pads can be placed in free positions by rewiring, so that the degree of freedom in selecting the mounting form increases.

  6 (1), (2-1) to (2-3), (3-1) to (3-4), and (4-1) to (4-6) are the WCSPs used in the fifth embodiment. It is a figure which shows the kind of.

  FIG. 6A is a schematic cross-sectional view of the processed wafer 30 including the resistor chip 20 manufactured in the first, second, or fourth embodiment. The processed wafer 30 has a wafer main body 30A on which a large number of resistor chips 20 are formed. The wafer main body 30A is covered with the PV film 8, and a large number of aluminum pads 7 are exposed.

  6 (2-1) to (2-3) are schematic manufacturing process diagrams showing a type 1 WCSP 40-1 using the processed wafer 30. FIG. In this WCSP 40-1, the copper rewiring 41 is formed on the PV film 8 in the process (2-1), and the upper part is covered with the insulating film 42-1 in the process (2-2). If the insulating film 42-1 at a predetermined location on the rewiring 41 is removed by etching to form an opening, and the solder ball 43 is formed in the opening in the step (2-3), the type 1 WCSP 40-1 can be manufactured.

  6 (3-1) to (3-4) are schematic manufacturing process diagrams showing a type 2 WCSP 40-2 using the processed wafer 30. FIG. In this WCSP 40-2, in step (3-1), after forming the insulating film 42-1 on the PV film 8, the pad 7 locations and the solder ball formation planned locations in the insulating film 42-1 are etched. Remove. In the step (3-2), a copper rewiring 41 is formed on the insulating film 42-1. In the step (3-3), the rewiring 41 is covered with the insulating film 42-2, and then a handball formation scheduled portion in the insulating film 42-2 is removed by etching to form an opening. In the step (3-4), if the solder ball 43 is formed in the opening, the type 2 WCSP 40-2 can be manufactured.

  6 (4-1) to (4-6) are schematic manufacturing process diagrams showing a type 3 WCSP 40-3 using the processed wafer 30. FIG. In this WCSP 40-3, after the insulating film 42-1 is formed on the PV film 8 in the step (4-1), seven pads in the insulating film 42-1 are removed by etching. In the step (4-2), the copper rewiring 41 is formed on the insulating film 42-1, and in the step (4-3), the metal pad 44 is formed at a predetermined position of the rewiring 41. In the step (4-4), after covering the entire surface with the insulating film 42-2, in the step (4-5), the insulating film 42-2 is etched until the pad 44 is exposed. Thereafter, in the step (4-6), if the solder balls 43 are formed on the exposed pads 44, the type 3 WCSP 40-3 can be manufactured.

7 (1) to 7 (9) are manufacturing process diagrams showing an example of a method for manufacturing the WCSP of FIG.
Prior to manufacturing, WCSPs 40-1 to 40-3 to be manufactured are selected from the types 1 to 3 of WCSPs 40-1 to 40-3 in consideration of adhesion, number of pads, chip area, and the like. . Hereinafter, an example of a manufacturing process of WCSP 40-3 will be described.

  Using the processed wafer 30 that has been subjected to the wafer process (WP) prepared in the step (1), an insulating film 42-1 is formed on the entire surface in the step (2). In the step (3), a rewiring 41 made of copper plating is formed on the insulating film 42-1, and in a step (4), a copper pad 44 is formed at a predetermined location on the rewiring 41. In the step (5), the entire surface is sealed with a resin insulating film 42-2. In the step (6), the insulating film 42-2 is ground (polished) to expose the upper surface of the pad 44. In the step (7), solder balls 43 are formed on the pads 44 by solder printing or the like. In the step (8), an electrical test or the like is performed. Further, the back surface of the wafer is back-thinned to form a thin film and separated into individual pieces by dicing. Then, in the step (9), the appearance inspection of the manufactured WCSP 40-3 To complete the manufacturing process.

FIG. 8 is a plan view showing an example of rearrangement of the pads 44 by the WCSP 40-3 of FIG.
In this WCSP 40-3, by arranging a large number of pads 44 uniformly, the area per one pad 44 increases. Therefore, even the resistor chip 20 having a large number of pads can be connected (mounted) to the wiring formed on the substrate by the solder balls 43 or the like.

FIG. 9 is a diagram illustrating an example in which the WCSP 40-3 of FIG. 8 is mounted on a substrate.
In this mounting example, the WCSP 40-3 in FIG. 8 is placed on the copper wiring 46 formed in advance on the surface of the substrate 45 and connected by the solder balls 43. Since the WCSP 40-3 having a large number of pads is connected by the solder balls 43, it can be firmly connected. Therefore, it is possible to mount another chip or the like on the WCSP 40-3.

FIG. 10 is a diagram illustrating another example of stacking other chips on the WCSP 40-3 in FIG.
In this laminated example, another chip 50 is fixed to the surface opposite to the solder ball 43 in the WCSP 40-3 mounted on the substrate 45, and the wire 51 of this chip 50 is connected to another chip or the like by wire bonding. is doing. Thereby, the mounting density can be improved.

(effect)
The WCSP of the fifth embodiment has the following effects (A) and (B).
(A) By the WCSP 40-1 shown in FIG. 8, the pad 7-1a, 7-1b to 7-4a, 7-4b in FIG. Therefore, the adjacent distance between the pads 44 is increased. As a result, mounting using the solder balls 43 and the like becomes possible.

  (B) Since the WCSP 40-3 can be firmly connected to the substrate 45 by the solder balls 43 shown in FIG. 9, another chip 50 as shown in FIG. 10 can be mounted on the WCSP 40-3, so that the mounting area is effective. Available to:

(Configuration / Manufacturing method)
FIG. 11 is a diagram of another rearrangement example of the pad 44 by the WCSP 40-3 showing the sixth embodiment of the present invention. Elements common to the elements in FIG. Has been.

  When the resistor chip 20 is rewired by the WCSP 40-3, a large number of pads 44 are unevenly distributed in the peripheral portion of the element mounting region provided at the center of the WCSP surface. Further, gold or the like is formed on the upper surface of the pad 44 after rewiring. In this way, it is possible to mount another small chip in the central element mounting region without the pad 44.

FIG. 12 is a diagram showing another example of stacking other chips on the WCSP 40-3 in FIG.
If a small chip 51 is produced by a method similar to that of WCSP 40-3 in FIG. 11, this chip 51 can be die bonded to the element mounting region of WCSP 40-3. Since the pad 44 of the lower WCSP 40-3 is exposed from the upper chip 51, the necessary chip and the like can be connected by wire bonding from the pad 52 of the upper chip 51 and the pad 44 of the lower WCSP 40-3. Yes. In the sixth embodiment, since gold or the like is formed on the upper surfaces of the pads 44 and 52, good bonding characteristics can be obtained.

(effect)
In the sixth embodiment, the WCSP 40-3 concentrates the pads 44 in which the pads 7-1a, 7-1b to 7-4a, 7-4b of the resistor chip 20 of FIG. In addition, another small chip 51 can be mounted on the element mounting region without the pad 44. Thus, by stacking the chips 51, the mounting area can be reduced.

  FIG. 13 is a schematic cross-sectional view of a component-embedded printed board using a resistor chip 20 showing Example 7 of the present invention.

  FIG. 13 shows a mounting example of a component-embedded printed board in which the thin resistor chip 20 of Examples 1 to 4 is built in a printed board. In the manufacture of the component-embedded printed circuit board, for example, in addition to the thin resistor chip 20, thin components such as a thin inductor chip 53, a capacitor chip 54, and an IC chip 55 are manufactured in advance. Then, for example, the capacitor chip 54 and the IC chip 55 are fixed on the printed circuit board main body 60 and connected by the first wiring layer 61-1 such as aluminum foil or copper foil, and these are covered with the resin insulating film 62. Thus, the first layer is formed. Further, the resistor chip 20 and the inductor chip 53 are fixed on the first layer, and are connected by the second wiring layer 61-2 connected to the first wiring layer 61-1 through the via hole 63. If these are covered with the resin insulating film 62 to form the second layer, etc., a thin component-embedded printed circuit board having a laminated structure as shown in FIG. 13 can be easily manufactured.

  As another mounting example of the resistor chip 20 and the like, for example, a storage recess (not shown) is formed in the printed circuit board body 60, and the resistor chip 20 and the like are mounted in the storage recess and covered with the resin insulating film 62 and the like. Various mounting forms are possible, such as.

  The present invention is not limited to the above-described embodiments, and various modifications and usage forms are possible. As an eighth embodiment which is this usage mode, for example, there are the following (1) and (2).

  (1) In the resistor chip 20, the silicon substrate 1 is used, but a glass substrate, an alumina substrate, or the like may be used.

  (2) Although the thin film resistors 3-1 to 3-4 and 3A-1 to 3A-4 are configured in a straight strip shape, they may be configured in another strip shape such as a curve or a square. In addition, as the thin film resistors 3-1 to 3-4 and 3A-1 to 3A-4, a polysilicon film into which ions such as boron and arsenic are implanted is used. However, ruthenium oxide, nickel (Ni), Transition elements such as cobalt (Co) and chromium (Cr) and alloys thereof may be used.

It is a schematic block diagram of the resistor chip | tip which shows Example 1 of this invention. It is a schematic longitudinal cross-sectional view of the resistor chip | tip which shows Example 2 of this invention. It is a schematic longitudinal cross-sectional view of the resistor chip | tip which shows Example 3 of this invention. FIG. 4 is a schematic longitudinal sectional view showing an example of embedding mounting of the resistor chip 20 of FIG. 3 on a substrate. It is a schematic block diagram of the resistor chip | tip which shows Example 4 of this invention. It is a figure which shows the kind of WCSP used for this Example 5 of this invention. FIG. 7 is a manufacturing process diagram illustrating a manufacturing method example of the WCSP of FIG. 6. It is a top view which shows the example of the rearrangement of the pad 44 by WCSP40-3 of FIG. It is a figure which shows the example which mounted WCSP40-3 of FIG. 8 on the board | substrate. It is a figure which shows the example of lamination | stacking of the other chip | tip on WCSP40-3 of FIG. It is a figure of the other rearrangement example of the pad 44 by WCSP40-3 which shows Example 6 of this invention. It is a figure which shows the example of lamination | stacking of the other chip | tip on WCSP40-3 of FIG. It is general | schematic sectional drawing of the component built-in printed circuit board using the resistor chip | tip 20 which shows Example 7 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 3-1 to 3-4, 3A-1 to 3A-4 Resistor 4-1 to 4-4 Interlayer insulation film 5 Contact hole 6 Plug 7,7-1a, 7-1b-7-7a, 7 -4b, 44, 52 Pad 8 Passivation film (PV film)
10-1 to 10-4 Stopper insulating film 20 Resistor chip 21, 45 Substrate 22, 62 Resin insulating film 24 Post 30 Processed wafer 30A Wafer body 40-1 to 40-3 WCSP
41 Rewiring 42-1, 42-2 Insulating Film 43 Solder Ball 50, 51 Chip 53 Inductor Chip 54 Capacitor Chip 55 IC Chip 60 Printed Circuit Board Body

Claims (15)

A substrate,
A plurality of strip-shaped thin film resistors arranged in parallel in the same plane, a thin film resistor group in which a plurality of layers are stacked apart from each other on the substrate;
A plurality of interlayer insulating films respectively covering a plurality of thin film resistors for each layer;
A plurality of plugs that are spaced apart in the lateral direction and are connected to the plurality of thin film resistors of the respective layers, and that vertically penetrate the interlayer insulating films of the plurality of layers and The plurality of plugs drawn to the surface;
A plurality of electrodes respectively joined to upper ends of the plurality of plugs and spaced apart on the uppermost interlayer insulating film;
A resistor chip comprising: The resistor chip according to claim 1,
The resistor chip, wherein the uppermost interlayer insulating film is covered with a passivation film with the plurality of electrodes exposed. The resistor chip according to claim 2,
A resistor chip, wherein a stopper insulating film is formed on the lower surface of each of the plurality of thin film resistors in each layer. The resistor chip according to claim 2 or 3,
A resistor chip, wherein a conductive post is erected on each of the electrodes. The resistor chip according to claim 2 or 3,
A rewiring layer connected to the plurality of electrodes and disposed on the passivation film;
A plurality of pads connected to the redistribution layer and arranged at predetermined plane positions;
An insulating film covering the rewiring layer in a state where the plurality of pads are exposed;
A resistor chip comprising: The resistor chip according to claim 5,
The resistor chip, wherein the plurality of pads are arranged at intervals larger than the arrangement interval of the plurality of electrodes, and solder balls are formed on the pads. The resistor chip according to claim 5,
The resistor chip, wherein the plurality of pads are arranged in a peripheral portion of an element mounting region provided on the surface. In the resistor chip according to any one of claims 1 to 7,
The thin film resistor is a resistor chip whose resistance value is adjusted by the length. In the resistor chip according to any one of claims 1 to 7,
The resistor chip, wherein the thin film resistor is made of polysilicon implanted with ions. The resistor chip according to claim 9,
The thin film resistor has a resistance value adjusted by the amount of ions implanted. In the resistor chip according to any one of claims 1 to 7,
The thin film resistor is formed of any one of ruthenium oxide, a transition element containing nickel, cobalt, or chromium and an alloy thereof. The resistor chip according to any one of claims 1 to 11,
The resistor chip, wherein the substrate is made of any one of a silicon substrate, a glass substrate, and an alumina substrate.   7. A method of mounting a resistor chip, comprising using the resistor chip according to claim 6 and mounting another chip on a surface opposite to the surface on which the solder balls are formed.   8. A method of mounting a resistor chip, comprising using the resistor chip according to claim 7 and mounting another chip in the element mounting region. Using the resistor chip according to any one of claims 1 to 14,
A method of mounting a resistor chip, wherein the substrate is thinned by back grinding and embedded in another substrate including a printed circuit board.

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