JPH02229403A - Manufacture of resistance array - Google Patents
Manufacture of resistance arrayInfo
- Publication number
- JPH02229403A JPH02229403A JP1249649A JP24964989A JPH02229403A JP H02229403 A JPH02229403 A JP H02229403A JP 1249649 A JP1249649 A JP 1249649A JP 24964989 A JP24964989 A JP 24964989A JP H02229403 A JPH02229403 A JP H02229403A
- Authority
- JP
- Japan
- Prior art keywords
- green sheet
- insulating
- resistor
- multilayer body
- resistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims abstract description 10
- 238000010304 firing Methods 0.000 claims description 7
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 abstract description 6
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 abstract description 5
- 238000007650 screen-printing Methods 0.000 abstract description 4
- 239000011521 glass Substances 0.000 abstract description 2
- 239000002241 glass-ceramic Substances 0.000 abstract description 2
- 239000011148 porous material Substances 0.000 description 10
- 238000003491 array Methods 0.000 description 6
- 239000000203 mixture Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000011195 cermet Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000013065 commercial product Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】 本発明は抵抗アレーの製造方法に関する。[Detailed description of the invention] The present invention relates to a method of manufacturing a resistor array.
最近、抵抗器の実装密度を大きくすることを目的に数個
の抵抗体を１つの絶縁基板上に一体化した抵抗アレーが
幅広く電子機器に活用されている。Recently, resistor arrays in which several resistors are integrated on one insulating substrate have been widely used in electronic devices in order to increase the packaging density of resistors.
一般に抵抗アレーの殆どは純度９５〜９９％のアルミナ
からなるセラミック基板上に形成されており、その基板
上に２酸化ルテニウムを主成分とする抵抗ペーストをス
クリーン印刷法を用いて被着し、温度８００〜１０００
℃の空気雰囲気中で約１時間焼成して抵抗体を形成して
いる。この抵抗体をレーザートリミング法などにより所
望の抵抗値に修正している．これらの通常市販されてい
る抵抗アレーの抵抗体は通常平面的に構成されている。Generally, most resistor arrays are formed on a ceramic substrate made of alumina with a purity of 95 to 99%, and a resistor paste containing ruthenium dioxide as a main component is applied onto the substrate using a screen printing method, and then 800-1000
The resistor was formed by firing in an air atmosphere at .degree. C. for about 1 hour. This resistor is modified to the desired resistance value using a laser trimming method. The resistors of these commonly commercially available resistor arrays are usually configured in a planar manner.
しかし電子機器の小型化が進行している現在、より多く
の抵抗体を多層状に一体化した抵抗アレーが必要になっ
て来ている。この要求に対して従来用いられてきた抵抗
アレーの上述した製造手段では次に述べる理由により多
層化は困難であった．従来、抵抗体の２層化まで試みら
れた手段を用いて、より多層化した抵抗アレーの断面図
を第１図に示す。（実際には多層化のメリットが出ない
ので市販品としては出廻っていない。）この構造を有す
る抵抗アレーの製造を簡単に説明すると、アルミナセラ
ミック基板１上にサーメット抵抗体２が印刷、焼成され
る。同時に電極３も形成される。次いで抵抗体２とほぼ
同一の温度で焼成できる絶縁ペーストを用い、印刷、焼
成して絶縁膜４を形成する．多層化は抵抗体２及び絶縁
膜４を繰返して形成して行う。この場合、第１図にも示
してあるように最後に行う抵抗値のトリミング用の窓５
を設けておかなければならないので、抵抗体はほとんど
それよりも下層に設けられた抵抗体と重畳することはで
きない．抵抗体を重畳することができなければ、多層化
して小形化するという目的を足させることは出来ない。However, as electronic equipment continues to become smaller, there is a growing need for resistor arrays that integrate more resistors into a multilayer structure. In response to this requirement, it has been difficult to create multiple layers using the above-mentioned manufacturing methods for resistor arrays that have been conventionally used for the following reasons. FIG. 1 shows a cross-sectional view of a multi-layered resistor array using the conventional method of creating two layers of resistors. (Actually, it is not available as a commercial product because it does not have the advantage of multilayering.) To briefly explain the manufacturing of a resistor array with this structure, a cermet resistor 2 is printed and fired on an alumina ceramic substrate 1. be done. At the same time, electrode 3 is also formed. Next, an insulation film 4 is formed by printing and firing using an insulation paste that can be fired at approximately the same temperature as the resistor 2. Multilayering is achieved by repeatedly forming the resistor 2 and the insulating film 4. In this case, as shown in FIG.
Therefore, it is almost impossible for a resistor to overlap with a resistor installed in a lower layer. If it is not possible to overlap resistors, the purpose of multilayering and miniaturization cannot be achieved.
この原因の主たるものはこのように多層化された抵抗ア
レーを製造する上で、焼成後抵抗値のトリミングが必要
であるからである．
発明者らは特願昭５５−１５６３６９に於いて開示した
抵抗グリーンシートを用いて抵抗値偏差のきわめて小さ
い抵抗器の製造方法を提案しており、この製造方法を抵
抗アレーの製造方法に適用することにより、まったく新
規な構造をもつ抵抗アレーが可能であることが発明でき
た。The main reason for this is that in manufacturing such a multilayered resistor array, it is necessary to trim the resistance value after firing. The inventors have proposed a method for manufacturing a resistor with extremely small deviation in resistance value using the resistor green sheet disclosed in Japanese Patent Application No. 55-156369, and this manufacturing method is applied to a method for manufacturing a resistor array. As a result, we were able to invent a resistor array with a completely new structure.
本発明の目的は多層状の抵抗アレーの製造方法を提供す
ることにある．
本発明によればあらかじめ形成された抵抗グリーンシー
トの個片を複数の絶縁グリーンシートの層間に配置後、
熱圧着して多層体を得る工程と、前記多層体を焼成する
工程とを有することを特徴とする抵抗アレーの製造方法
が得られる．以下本発明を第２図〜第５図を参照して詳
細に説明する．
第２図は本発明抵抗アレーの一実施例の断面図を示す．
絶縁層６はアルミナーガラスセラミック複合物（絶縁層
５ａ，・・・・・・，６ｎは均一組成）であり、内装化
された抵抗体７は２酸化ルテニウムを主成分としてガラ
スフリフトを混合した構造にしている．外部電極８およ
び外部電極８と内装の抵抗体７とを電気的に接続する配
線９は絶縁層６に設けられた数百ミクロンメーター細孔
を金、銀、銀一パラジウムなどの金属で埋めることによ
り形成する．本発明実施例の抵抗アレーは複数の抵抗体
および均一組成を持つ複数の絶縁層を多層化して焼結し
た一体物であり、その抵抗強度は約２０００ｋｇ／ａｍ
”という大きな値を示している。An object of the present invention is to provide a method for manufacturing a multilayer resistor array. According to the present invention, after placing individual pieces of preformed resistive green sheets between layers of a plurality of insulating green sheets,
A method for manufacturing a resistor array is obtained, which comprises the steps of: obtaining a multilayer body by thermocompression bonding; and firing the multilayer body. The present invention will be explained in detail below with reference to FIGS. 2 to 5. FIG. 2 shows a cross-sectional view of one embodiment of the resistor array of the present invention.
The insulating layer 6 is an alumina glass ceramic composite (insulating layers 5a, . . . , 6n have a uniform composition), and the internal resistor 7 is made of ruthenium dioxide as a main component mixed with glass drift. It has a similar structure. The external electrode 8 and the wiring 9 that electrically connects the external electrode 8 and the internal resistor 7 are made by filling pores of several hundred micrometers provided in the insulating layer 6 with metal such as gold, silver, silver-palladium, etc. Formed by. The resistor array according to the embodiment of the present invention is an integrated product made by laminating and sintering a plurality of resistors and a plurality of insulating layers having a uniform composition, and its resistance strength is approximately 2000 kg/am.
” indicates a large value.
第３図（ａｌ． （ｂ）． （Ｑ）は本発明抵抗アレー
の一実施例の製造工程の一部を示すものである．第２図
に示した絶縁層および抵抗体はそれぞれ厚さ０． １
ｍ・〜０．０３ｍの未焼成膜（以下グリーンシートと呼
ぶ）の形で予め準備される．
絶縁グリーンシートおよび抵抗グリーンシートの組成比
は第１表および第２表の通りである。Figure 3 (al. (b). (Q) shows a part of the manufacturing process of one embodiment of the resistor array of the present invention. The insulating layer and the resistor shown in Figure 2 each have a thickness of 0. .1
It is prepared in advance in the form of an unfired film (hereinafter referred to as a green sheet) with a thickness of ~0.03 m. The composition ratios of the insulating green sheet and the resistive green sheet are shown in Tables 1 and 2.
第１表（絶縁グリーンシートの組成）
第３表（グリーンシートの特性）
第２表（抵抗グリーンシートの組成）
それぞれのグリーンシートの特性は第３表の通りであっ
た。Table 1 (Composition of insulating green sheet) Table 3 (Characteristics of green sheet) Table 2 (Composition of resistive green sheet) The characteristics of each green sheet were as shown in Table 3.
この２種類のグリーンシートを多層化して抵抗アレーを
製造する．
第３図（ａ）は絶縁グリーンシート１０に金型を用いて
直径約１５０，ｉＪｍの複数の細孔１１を形成した状態
を示す。この細孔１１の位置は後述するように多層化し
た時に、抵抗体と接続する位置にそれぞれ形成されてい
る。A resistor array is manufactured by layering these two types of green sheets. FIG. 3(a) shows a state in which a plurality of pores 11 having a diameter of about 150, iJm are formed in the insulating green sheet 10 using a mold. The pores 11 are formed at positions where they will be connected to resistors when multilayered, as will be described later.
本実施例の抵抗アレーは絶縁層２１層とし、その層間に
２０枚の抵抗シートの個片を配置して、最終出来上がり
抵抗アレーは素子数２０になるようにした．また抵抗ア
レ−１個の外形寸法は１０ｖａａ Ｘ ５． Ｏ ｍ
Ｘ ２． Ｏ ｔｍになるようにした。The resistor array of this example had 21 insulating layers, and 20 pieces of resistor sheets were arranged between the layers, so that the final completed resistor array had 20 elements. Also, the external dimensions of one resistor array are 10 vaa x 5. O m
X 2. I tried to make it O tm.
本実施例では抵抗グリーンシートの目標抵抗値を１ｋΩ
１種頻に設定しこの抵抗グリーンシートを長さ３ｍ，輻
１ｆｌに切断して抵抗グリーンシートの個片（図示省略
）を形成してお《．次に細孔ｌ１を形成した絶縁グリー
ンシート１０に細孔１１および細孔１１が抵抗体と外接
する位置、すなわち細孔１１の近傍の上面に銀一パラジ
ウムペーストをスクリーン印刷法を用いて矩形状に被着
させ、内部電極１２を形成する。この時細孔１０内には
銀−パラジウムペーストが充填され絶縁グリーンシート
の表裏が電気的に導通される。このような方法で内部電
極ｌ２が形成された絶縁グリーンシ−｝１０上にあらか
じめ形成しておいた抵抗グリーンシートの個片１３を第
３図（ｂ）に示すように隣接する２個の内部電極ｌ２に
外接するように配置し、熱プレス機で温度１１５℃，圧
力５０ｋｇ／ｃｍ”で１分間熱圧着を行う。このように
して抵抗グリーンシートの個片１３を圧着した絶縁グリ
ーンシートを銀−パラジウムペーストが埋められた細孔
１１が互に接続するように位置合せして２１枚積層し、
熱プレス機で温度１１５℃，圧力２５０１ｇ／ｃｓ＝”
， ２ ０分間熱圧着を行い第３図（Ｃ）に示す多
層体１４にする。In this example, the target resistance value of the resistor green sheet is 1kΩ.
The resistance green sheet is cut into pieces of 3 m in length and 1 fl in width to form individual pieces of resistance green sheet (not shown). Next, a silver-palladium paste is applied to the insulating green sheet 10 in which the pores l1 are formed using a screen printing method to form a rectangular shape on the pores 11 and the upper surface near the pores 11, where the pores 11 circumscribe the resistor. to form the internal electrodes 12. At this time, the pores 10 are filled with silver-palladium paste, and the front and back surfaces of the insulating green sheet are electrically connected. As shown in FIG. 3(b), the individual pieces 13 of the resistive green sheet formed in advance on the insulating green sheet 10 on which the internal electrode l2 has been formed in this manner are placed between two adjacent internal parts. The insulating green sheet with the individual pieces 13 of the resistive green sheet crimped in this way is then bonded using a heat press machine at a temperature of 115°C and a pressure of 50 kg/cm for 1 minute. - Align and stack 21 sheets so that the pores 11 filled with palladium paste are connected to each other,
Temperature: 115℃, pressure: 2501g/cs=”
, 20 minutes of thermocompression bonding is performed to form the multilayer body 14 shown in FIG. 3(C).
次にこの多層体１４の上部表面に内部の配腺９（第２図
参照）に接続するように外部電極８をスクリーン印刷方
法を用いて形成する．
次に第３図（Ｃ）に示すように切断線Ａ−Ａ．ＢＢに沿
ってナイフなどにより多層体１４を切断して個片１４ａ
とする。Next, external electrodes 8 are formed on the upper surface of this multilayer body 14 using a screen printing method so as to be connected to internal glands 9 (see FIG. 2). Next, as shown in FIG. 3(C), cut line A-A. The multilayer body 14 is cut along BB with a knife or the like to form individual pieces 14a.
shall be.
次いでこの個片１４ａを第４図に示す温度曲線を有する
焼成炉（図示省略）中で焼成した。Next, this individual piece 14a was fired in a firing furnace (not shown) having a temperature curve shown in FIG.
このようにして製作された抵抗アレーは第２図に示す断
面形状を有しその特性は第４表に示す結果であった．
第４表（抵抗アレーの特性）
この特性は現在市販されている抵抗アレーの特性に匹敵
する。The resistor array thus fabricated had the cross-sectional shape shown in Figure 2, and its characteristics were shown in Table 4. Table 4 (Characteristics of resistor array) These characteristics are comparable to those of resistor arrays currently on the market.
以上、本発明による抵抗アレーの特性は従来品と同等で
あり、かつ外形は約１／４以下ときわめて小型化された
効果は大きい．As described above, the characteristics of the resistor array according to the present invention are the same as those of conventional products, and the external size is approximately 1/4 or less, which is extremely compact, which has a great effect.
第１図は従来手段を用いて製作した抵抗アレーの縦断面
図、第２図は本発明の一実施例によって得られる抵抗ア
レーの縦断面図、第３図（ａ）は絶縁グリーンシートに
細孔を設けた状態を示す斜視図、第３図山）は第２図（
ａｌの絶縁グリーンシート上に内部電極および抵抗グリ
ーンシートを被着した状態を示す斜視図、第３図（Ｃ）
は第２図（ｂ）の絶縁グリーンシートを積層し多層体と
した斜視図、第４図は本発明の一実施例で使用した焼成
炉の温度曲線図。
６・・・絶縁層、７・・・抵抗体、８・・・外部電極、
９・・・配線、１０・・・絶縁グリーンシート、１１・
・・細孔、１２・・・内部電極、１３・・・抵抗グリー
ンシートの個片、１４・・・多層体、１４ａ・・・（多
層体の）個片。
１・・・アルミナセラミック基板、２・・・サーメット
抵抗体、３・・・電極、４・・・絶縁膜、５・・・窓。
第１区
第
図
第
図（α）
１フ
第
図（ｂ）
第
図（ｃ）FIG. 1 is a longitudinal sectional view of a resistor array manufactured using conventional means, FIG. 2 is a longitudinal sectional view of a resistor array obtained by an embodiment of the present invention, and FIG. A perspective view showing the state in which holes are provided, Figure 3) is shown in Figure 2 (
Figure 3 (C) is a perspective view showing a state in which internal electrodes and resistance green sheets are covered on an Al insulating green sheet.
2(b) is a perspective view of the insulating green sheets laminated to form a multilayer body, and FIG. 4 is a temperature curve diagram of a firing furnace used in an embodiment of the present invention. 6... Insulating layer, 7... Resistor, 8... External electrode,
9... Wiring, 10... Insulating green sheet, 11.
... Pore, 12... Internal electrode, 13... Individual piece of resistive green sheet, 14... Multilayer body, 14a... Individual piece (of multilayer body). DESCRIPTION OF SYMBOLS 1... Alumina ceramic substrate, 2... Cermet resistor, 3... Electrode, 4... Insulating film, 5... Window. 1st section diagram (α) 1st floor diagram (b) Figure (c)
Claims (1)
複数の絶縁グリーンシートの層間に配置後、熱圧着して
多層体を得る工程と、前記多層体を焼成する工程とを有
することを特徴とする抵抗アレーの製造方法。The method is characterized by comprising the steps of: obtaining a multilayer body by arranging individual pieces of resistive green sheets formed in advance between layers of a plurality of insulating green sheets and bonding them by thermocompression; and firing the multilayer body. Method of manufacturing a resistor array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1249649A JPH02229403A (en) | 1989-09-25 | 1989-09-25 | Manufacture of resistance array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1249649A JPH02229403A (en) | 1989-09-25 | 1989-09-25 | Manufacture of resistance array |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56156671A Division JPS5857703A (en) | 1981-10-01 | 1981-10-01 | Resistor array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02229403A true JPH02229403A (en) | 1990-09-12 |
| JPH0435886B2 JPH0435886B2 (en) | 1992-06-12 |
Family
ID=17196163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1249649A Granted JPH02229403A (en) | 1989-09-25 | 1989-09-25 | Manufacture of resistance array |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02229403A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0491543A2 (en) * | 1990-12-17 | 1992-06-24 | Hughes Aircraft Company | Via resistors within multilayer 3-dimensional structures/substrates |
| JP2000182811A (en) * | 1998-12-21 | 2000-06-30 | Alps Electric Co Ltd | Resistance attenuator |
| JP2005045257A (en) * | 2003-07-23 | 2005-02-17 | Robert Bosch Gmbh | Method for fabricating hybrid product comprising several wiring planes |
| JP2006186038A (en) * | 2004-12-27 | 2006-07-13 | Oki Electric Ind Co Ltd | Resistor chip and its packaging method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50119815A (en) * | 1974-03-08 | 1975-09-19 |
-
1989
- 1989-09-25 JP JP1249649A patent/JPH02229403A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50119815A (en) * | 1974-03-08 | 1975-09-19 |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0491543A2 (en) * | 1990-12-17 | 1992-06-24 | Hughes Aircraft Company | Via resistors within multilayer 3-dimensional structures/substrates |
| JP2000182811A (en) * | 1998-12-21 | 2000-06-30 | Alps Electric Co Ltd | Resistance attenuator |
| JP2005045257A (en) * | 2003-07-23 | 2005-02-17 | Robert Bosch Gmbh | Method for fabricating hybrid product comprising several wiring planes |
| JP2006186038A (en) * | 2004-12-27 | 2006-07-13 | Oki Electric Ind Co Ltd | Resistor chip and its packaging method |
| JP4644482B2 (en) * | 2004-12-27 | 2011-03-02 | Ｏｋｉセミコンダクタ株式会社 | Resistor chip and mounting method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0435886B2 (en) | 1992-06-12 |
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