JP2006185975A - Method of manufacturing multilayered electronic component element assembly - Google Patents

Method of manufacturing multilayered electronic component element assembly Download PDF

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JP2006185975A
JP2006185975A JP2004375127A JP2004375127A JP2006185975A JP 2006185975 A JP2006185975 A JP 2006185975A JP 2004375127 A JP2004375127 A JP 2004375127A JP 2004375127 A JP2004375127 A JP 2004375127A JP 2006185975 A JP2006185975 A JP 2006185975A
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support
insulating layer
insulating
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Hisashi Sato
恒 佐藤
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Kyocera Corp
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<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a multilayered electronic component element assembly which can prevent poor adhesion between insulating layers and can also prevent a internal defect at the time of burning even if the individual insulating layers are made thin and the number of layers is increased. <P>SOLUTION: The method of manufacturing the multilayered electronic component element assembly comprises a process A wherein an insulating layer is formed on one principal plane of a first support body; process B wherein through holes are formed through the first support body and the insulation layer at predetermined positions of the insulating layer; process C wherein an insulation sheet held on a second support body is pasted on the insulating layer so as to close the openings of the through holes; process D wherein a conductive layer is formed inside the through holes of the insulation sheet from the other principal plane side of the first support body to form a composite sheet consisting of the insulation sheet, insulating layer, and conductive layer; and process E wherein after delaminating the first support body from the composite sheet, the composite sheet from which the first support body has been delaminated is stacked on a laminate, and then the second support body is delaminated. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、積層セラミックコンデンサ等の積層電子部品素体の製造方法に関する。   The present invention relates to a method for manufacturing a multilayer electronic component body such as a multilayer ceramic capacitor.

近年、電子機器の小型化、高密度化に伴い、積層電子部品の小型、高機能化が求められている。代表的な積層電子部品である積層セラミックコンデンサ10としては図6に示すような、複数枚の絶縁シート24を積層してなる積層体11内部で、隣接する絶縁シート24間に導電層26を介在させるとともに、積層体11の側面から主面にかけて、導電層24の一端に接続される外部電極12を被着させた構造のものが知られており、小型、高容量化の要求に答えるために、積層体11を構成する絶縁シート24、導電層26等の薄層化及び多層化がより進められている。   In recent years, with the downsizing and high density of electronic devices, there has been a demand for miniaturization and high functionality of laminated electronic components. As a multilayer ceramic capacitor 10 which is a typical multilayer electronic component, as shown in FIG. 6, a conductive layer 26 is interposed between adjacent insulating sheets 24 inside a multilayer body 11 in which a plurality of insulating sheets 24 are stacked. In addition, a structure in which the external electrode 12 connected to one end of the conductive layer 24 is attached from the side surface to the main surface of the multilayer body 11 is known. Further, thinning and multilayering of the insulating sheet 24, the conductive layer 26, and the like constituting the laminated body 11 are being promoted.

このような薄層化及び多層化に伴い、特に導電層(導体材料)26の厚みが製品のできばえに大きく影響するようになってきている。すなわち、導電層26が形成されている部分と形成されていない部分との間で導電層26の厚みによる段差が発生し、積層されることで累積し、導電層26の周囲の絶縁シート24同士の密着が弱くなり、焼成時のデラミネーションやクラックなどの内部欠陥が発生しやすくなるという問題点があった。   With such thinning and multilayering, the thickness of the conductive layer (conductor material) 26 has been greatly affected by the quality of products. That is, a step due to the thickness of the conductive layer 26 is generated between a portion where the conductive layer 26 is formed and a portion where the conductive layer 26 is not formed. There is a problem that the adhesion of the resin becomes weak and internal defects such as delamination and cracks are easily generated during firing.

このような問題点を解決する為に、図7に示すような、(a)第1の支持体32上に、導電層36及び絶縁層31をスクリーン印刷により形成する工程と、(b)導電層36及び絶縁層31を第2の支持体35上に形成した絶縁シート34上に転写し導電層36と絶縁層31と絶縁シート34とから成る複合シート37を形成する工程と、(c)第1の支持体32を剥離する工程と、(d)複合シート37を被積層体38に転写する工程と、(e)第2の支持体35を剥離する工程とを順次繰り返すことにより、大型積層体を形成し、さらに大型積層体から抽出した積層体を焼成することにより積層セラミック電子部品を製造する方法が、特開2001−244117号公報に開示されている(特許文献1参照)。なお被積層体とは絶縁シート或は/且つ複合シートあるいは複数積層した複合シートを示す。
特開2001−244117号公報(8頁、図9)
In order to solve such problems, as shown in FIG. 7, (a) a step of forming a conductive layer 36 and an insulating layer 31 on the first support 32 by screen printing, and (b) a conductive layer. Transferring the layer 36 and the insulating layer 31 onto the insulating sheet 34 formed on the second support 35 to form a composite sheet 37 comprising the conductive layer 36, the insulating layer 31, and the insulating sheet 34; and (c). By repeating the step of peeling the first support 32, the step of (d) transferring the composite sheet 37 to the laminated body 38, and the step of (e) peeling the second support 35, a large size is obtained. JP-A-2001-244117 discloses a method of manufacturing a multilayer ceramic electronic component by forming a multilayer body and firing a multilayer body extracted from a large-sized multilayer body (see Patent Document 1). The laminated body refers to an insulating sheet and / or a composite sheet or a composite sheet in which a plurality of layers are laminated.
JP 2001-244117 A (page 8, FIG. 9)

しかしながら、上記製造方法によれば、図8に示すように導電層36、絶縁層31の分岐領域である境界部分においてスクリーン印刷特有の端面がダレるということに起因した空隙部Vが発生するために、積層による段差を完全に解消することが困難であるという問題があった。また前記製造方法では、通常、絶縁層31を形成するスクリーン印刷の精度が30〜200μmあり、このような印刷の位置ずれのために、図9に示すように、絶縁層31の一部が導電層36上に乗り上げてしまい、あるいは逆に導電層36の一部が絶縁層31に乗り上げてしまい、段差を助長する結果を招いてしまうという問題があった。   However, according to the above manufacturing method, as shown in FIG. 8, the void portion V is generated due to the sagging of the end face peculiar to screen printing at the boundary portion that is a branch region of the conductive layer 36 and the insulating layer 31. In addition, there is a problem that it is difficult to completely eliminate the step due to the lamination. Further, in the manufacturing method, the accuracy of screen printing for forming the insulating layer 31 is usually 30 to 200 μm, and due to such printing misalignment, a part of the insulating layer 31 is electrically conductive as shown in FIG. There is a problem in that it rides on the layer 36, or conversely, a part of the conductive layer 36 rides on the insulating layer 31, resulting in a step difference.

さらには、積層電子部品の低コスト化の要求に応えるために、製造工程においては大型積層体の大面積化が行われており、このため、ますます印刷による位置ずれが顕在化されるという問題を有していた。   Furthermore, in order to meet the demand for cost reduction of multilayer electronic components, large-scale laminates have been increased in area in the manufacturing process, which has caused the problem of misalignment due to printing. Had.

本発明は、上述の問題点に鑑みて案出されたものであり、その目的は、絶縁シートを薄層化して積層数を増加した場合にも、積層時の段差の累積を防止し、絶縁シート間の密着不良並びに焼成時の内部欠陥を防止できる積層電子部品素体の製造方法を提供することにある。   The present invention has been devised in view of the above-mentioned problems, and its purpose is to prevent accumulation of steps during lamination even when the number of laminations is increased by thinning an insulating sheet, and insulation is achieved. An object of the present invention is to provide a method for manufacturing a multilayer electronic component element body that can prevent poor adhesion between sheets and internal defects during firing.

本発明の積層電子部品素体の第1の請求項に関する製造方法は、 絶縁層、絶縁シートおよび導体層が積層されて成る被積層体に、複合シートを積層一体してなる積層電子部品素体の製造方法であって、
第1の支持体の一方主面に、絶縁層を形成する工程aと、
前記絶縁層の所定箇所に、前記第1の支持体及び前記絶縁層を貫通する貫通孔を形成する工程bと、
前記絶縁層の表面に前記貫通孔の開口を塞ぐようにして、第2の支持体に保持された絶縁シートを貼着させる工程cと、
前記第1の支持体の他方主面側から、前記絶縁シートの前記貫通孔内に導電層を形成し、前記絶縁シートと前記絶縁層と前記導電層とから成る複合シートを形成する工程dと、
前記複合シートから前記第1の支持体を剥離した後、前記第1の支持体を剥離した前記複合シートを被積層体に積層し、しかる後前記第2の支持体を剥離する工程eと、
を具備することを特徴とする積層電子部品素体の製造方法である。
The method for producing a multilayer electronic component element according to the first aspect of the present invention includes: a multilayer electronic component element in which a composite sheet is laminated and integrated on a laminate in which an insulating layer, an insulating sheet, and a conductor layer are laminated. A manufacturing method of
Forming an insulating layer on one main surface of the first support;
Forming a through-hole penetrating the first support and the insulating layer at a predetermined location of the insulating layer; and b.
A step c of adhering an insulating sheet held on the second support so as to close the opening of the through hole on the surface of the insulating layer;
Forming a conductive layer in the through hole of the insulating sheet from the other main surface side of the first support, and forming a composite sheet comprising the insulating sheet, the insulating layer, and the conductive layer; and ,
After peeling off the first support from the composite sheet, stacking the composite sheet from which the first support has been peeled off, and then peeling off the second support, e.
It is a manufacturing method of the laminated electronic component element | base_body characterized by comprising.

また、請求項2の発明は、絶縁層、絶縁シートおよび導体層が積層されて成る被積層体に、複合シートを積層一体してなる積層電子部品素体の製造方法であって、
第1の支持体の一方主面に、絶縁層を形成する工程aと、
前記絶縁層の所定箇所に、前記第1の支持体及び前記絶縁層を貫通する貫通孔を形成する工程bと、
前記絶縁層の表面に前記貫通孔の開口を塞ぐようにして、第2の支持体に保持された絶縁シートを貼着させる工程cと、
前記第1の支持体の他方主面側から、前記絶縁シートの前記貫通孔内に導電層を形成し、前記絶縁シートと前記絶縁層と前記導電層とから成る複合シートを形成する工程dと、
前記複合シートから前記第一および第2の支持体を剥離した後、前記第一および第2の支持体から剥離した前記複合シートを被積層体に積層する工程eと、
を具備することを特徴とする積層電子部品素体の製造方法である。
The invention of claim 2 is a method for manufacturing a multilayer electronic component element body in which a composite sheet is laminated and integrated on a laminate in which an insulating layer, an insulating sheet, and a conductor layer are laminated.
Forming an insulating layer on one main surface of the first support;
Forming a through-hole penetrating the first support and the insulating layer at a predetermined location of the insulating layer; and b.
A step c of adhering an insulating sheet held on the second support so as to close the opening of the through hole on the surface of the insulating layer;
Forming a conductive layer in the through hole of the insulating sheet from the other main surface side of the first support, and forming a composite sheet comprising the insulating sheet, the insulating layer, and the conductive layer; and ,
After peeling the first and second supports from the composite sheet, the step e of laminating the composite sheet peeled from the first and second supports on a laminate;
It is a manufacturing method of the laminated electronic component element | base_body characterized by comprising.

さらに、請求項3の発明は、絶縁層、絶縁シートおよび導体層が積層されて成る被積層体に、複合シートを積層一体してなる積層電子部品素体の製造方法であって、
第1の支持体の一方主面に、絶縁層を形成する工程aと、
前記絶縁層の所定箇所に、前記第1の支持体及び前記絶縁層を貫通する貫通孔を形成する工程bと、
前記絶縁層の表面に前記貫通孔の開口を塞ぐようにして、絶縁シートを貼着させる工程cと、
前記第1の支持体の他方主面側から、前記絶縁シートの前記貫通孔内に導電層を形成し、前記絶縁シートと前記絶縁層と前記導電層とから成る複合シートを形成する工程dと、
前記複合シートから前記第1の支持体を剥離した後、前記複合シートを被積層体に積層する工程eと、
を具備することを特徴とする積層電子部品素体の製造方法である。
Further, the invention of claim 3 is a method for manufacturing a multilayer electronic component element body in which a composite sheet is laminated and integrated on a laminate in which an insulating layer, an insulating sheet, and a conductor layer are laminated.
Forming an insulating layer on one main surface of the first support;
Forming a through-hole penetrating the first support and the insulating layer at a predetermined location of the insulating layer; and b.
A step c of adhering an insulating sheet so as to block the opening of the through hole on the surface of the insulating layer;
Forming a conductive layer in the through hole of the insulating sheet from the other main surface side of the first support, and forming a composite sheet comprising the insulating sheet, the insulating layer, and the conductive layer; and ,
After peeling the first support from the composite sheet, the step e of laminating the composite sheet on a laminate;
It is a manufacturing method of the laminated electronic component element | base_body characterized by comprising.

請求項4の発明は、絶縁層、絶縁シートおよび導体層が積層されて成る被積層体に、複合シートを積層一体してなる積層電子部品素体の製造方法であって、
第1の支持体の一方主面に、絶縁層を形成する工程aと、
前記絶縁層の所定箇所に、前記第1の支持体及び前記絶縁層を貫通する貫通孔を形成する工程bと、
前記絶縁層の表面に前記貫通孔の開口を塞ぐようにして、絶縁シートを貼着させる工程cと、
前記第1の支持体の他方主面側から、前記絶縁シートの前記貫通孔内に導電層を形成し、前記絶縁シートと前記絶縁層と前記導電層とから成る複合シートを形成する工程dと、
前記複合シートを被積層体に積層した後、前記第1の支持体を剥離する工程eと、
を具備することを特徴とする積層電子部品素体の製造方法である。
The invention of claim 4 is a method for producing a multilayer electronic component element body in which a composite sheet is laminated and integrated on a laminate in which an insulating layer, an insulating sheet, and a conductor layer are laminated.
Forming an insulating layer on one main surface of the first support;
Forming a through-hole penetrating the first support and the insulating layer at a predetermined location of the insulating layer; and b.
A step c of adhering an insulating sheet so as to block the opening of the through hole on the surface of the insulating layer;
Forming a conductive layer in the through hole of the insulating sheet from the other main surface side of the first support, and forming a composite sheet comprising the insulating sheet, the insulating layer, and the conductive layer; and ,
After laminating the composite sheet on the laminate, a step e of peeling the first support;
It is a manufacturing method of the laminated electronic component element | base_body characterized by comprising.

さらにまた本発明の積層電子部品素体の製造方法は、導電層がダイコート法、スプレーコート法のいずれかにより形成することを特徴とする。   Furthermore, the method for producing a multilayer electronic component body according to the present invention is characterized in that the conductive layer is formed by either a die coating method or a spray coating method.

本発明の積層電子部品素体の製造方法によれば、第1の支持体及び絶縁層を貫通する貫通孔を形成した後、絶縁層表面に、絶縁シートまたは絶縁シートが被着された第2の支持体を貫通孔を塞ぐようにして貼着させ、しかる後第1の支持体の他方主面の貫通孔領域に導電層を形成し、必要に応じて第2の支持体を剥離して絶縁シートと絶縁層と導電層から成る複合シートを形成することから、絶縁層と導電層が重なって段差を生じることはなく、その結果、複合シートを複数積層した場合においても、密着性の低下をまねくことが無く、内部欠陥の発生を防止できるという効果が得られる。   According to the method for manufacturing a multilayer electronic component element body of the present invention, after forming the through hole penetrating the first support and the insulating layer, the insulating sheet or the insulating sheet is attached to the surface of the insulating layer. The support is attached so as to close the through hole, and then a conductive layer is formed in the through hole region of the other main surface of the first support, and the second support is peeled off as necessary. Forming a composite sheet consisting of an insulating sheet, an insulating layer, and a conductive layer, the insulating layer and the conductive layer do not overlap to form a step. As a result, even when a plurality of composite sheets are laminated, the adhesion is reduced. The effect of preventing the occurrence of internal defects can be obtained.

また本発明は、上記積層電子部品素体の製造方法において、導電層をダイコート法、スプレーコート法のいずれかを用いて形成することから、導電層の表面が平坦となり、絶縁層と導電層との境界に空隙部が生じないので、積層した場合において密着性の低下をまねくことが無く、内部欠陥の発生を防止できるという効果が得られる。   Further, the present invention provides a method for manufacturing a multilayer electronic component body, wherein the conductive layer is formed using either a die coating method or a spray coating method, so that the surface of the conductive layer becomes flat, and the insulating layer, the conductive layer, Since no void portion is generated at the boundary, there is no reduction in adhesion when laminated, and the effect of preventing the occurrence of internal defects can be obtained.

以下、本発明を添付図面に基づいて詳細に説明する。   Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

代表的な積層電子部品として、積層セラミックコンデンサを用いて説明する。   A typical multilayer electronic component will be described using a multilayer ceramic capacitor.

図1は積層セラミックコンデンサの縦断面図である。この図で1(31)は絶縁層、4(34)は絶縁シート、6(36)は導電層、11は積層体、12は外部電極を表し主にこれらで積層セラミックコンデンサが構成されている。なお、(31)、(34)、(36)は従来の技術で説明した符号であり、以下では、符号1、4、6を用いて説明する。   FIG. 1 is a longitudinal sectional view of a multilayer ceramic capacitor. In this figure, 1 (31) is an insulating layer, 4 (34) is an insulating sheet, 6 (36) is a conductive layer, 11 is a laminate, 12 is an external electrode, and these mainly constitute a multilayer ceramic capacitor. . In addition, (31), (34), and (36) are the codes | symbols demonstrated by the prior art, and it demonstrates using the codes | symbols 1, 4, and 6 below.

積層体11を構成する絶縁シート4、絶縁層1は、その材料が例えば、BaTiO、CaTiO、SrTiO等を主成分とする高誘電率の誘電体材料やTiO等を主成分とする温度補償用の誘電体材料であり、その厚みが例えば1層あたり1μm〜3μmである。また積層体11における絶縁シート4の積層数は、例えば20層〜2000層である。 The insulating sheet 4 and the insulating layer 1 constituting the laminate 11 are mainly composed of a dielectric material having a high dielectric constant whose main component is BaTiO 3 , CaTiO 3 , SrTiO 3, or the like, or TiO 2 or the like. It is a dielectric material for temperature compensation, and its thickness is, for example, 1 μm to 3 μm per layer. The number of laminated insulating sheets 4 in the laminate 11 is, for example, 20 to 2000 layers.

導電層6は、積層体11の内部で隣接する絶縁シート4層間に形成され、その材料は、Ni、Cu、Cu−Ni、Ag−Pd等の金属を主成分とする導体材料であり、その厚みが例えば0.5μm〜2μmである。なお絶縁シート4を介して対向する一対の導電層6は、対向する領域間で静電容量が形成され、その一端はそれぞれ積層体11の異なる端面に導出される。   The conductive layer 6 is formed between adjacent insulating sheet 4 layers inside the laminate 11, and the material thereof is a conductor material mainly composed of a metal such as Ni, Cu, Cu—Ni, Ag—Pd, and the like. The thickness is, for example, 0.5 μm to 2 μm. The pair of conductive layers 6 that face each other with the insulating sheet 4 between them has a capacitance between the facing regions, and one end thereof is led out to a different end face of the laminate 11.

積層体11の端面から主面にかけて被着される外部電極12は、その材料としては例えば、導電率が高く半田に浸食されにくいCu等の導体材料であり、その厚みが例えば5μm〜10μmに設定される。また外部電極12は、端面に導出した導電層6の一端に接続され、積層体11の内部で形成される静電容量と電気的に接続される。   The external electrode 12 deposited from the end surface to the main surface of the multilayer body 11 is, for example, a conductor material such as Cu having high conductivity and not easily eroded by solder, and the thickness thereof is set to 5 μm to 10 μm, for example. Is done. The external electrode 12 is connected to one end of the conductive layer 6 led to the end face, and is electrically connected to a capacitance formed inside the stacked body 11.

なお、一般的には、外部電極12の表面には、回路基板に半田で搭載される場合の耐熱性を向上するための厚みが1μm〜3μmのNi層や、半田が塗れやすくするための厚みが4μm〜5μmの半田あるいはSn層等(図1では図示せず)を被覆形成される。   In general, the surface of the external electrode 12 has a thickness of 1 μm to 3 μm for improving heat resistance when mounted on a circuit board with solder, or a thickness for easily applying solder. Is coated with a 4 μm to 5 μm solder or Sn layer (not shown in FIG. 1).

次に、まず本発明の積層電子部品素体の第一の製造方法について図2を用いて説明する。なお、図面において、各符号は焼成の前後で区別しないことにする。   Next, a first manufacturing method of the multilayer electronic component body of the present invention will be described with reference to FIG. In the drawings, each symbol is not distinguished before and after firing.

最初に、図2(a)に示すように、第1の支持体2の一方主面にセラミックスラリを塗布後乾燥することにより、絶縁層1となるセラミックグリーンシートを形成する(工程a)。   First, as shown in FIG. 2A, a ceramic green sheet to be the insulating layer 1 is formed by applying a ceramic slurry to one main surface of the first support 2 and drying it (step a).

ここで、第1の支持体2としては、強度、平滑性、剥離性等を考慮してPETフィルム、ポリプロピレンフィルムなどが用いられ、また、絶縁層1を形成する方法としては、ダイコータ法やマイクログラビア印刷法などが挙げられる。   Here, as the first support 2, a PET film, a polypropylene film, or the like is used in consideration of strength, smoothness, releasability, and the like. As a method for forming the insulating layer 1, a die coater method or a microscopic method is used. Examples include gravure printing.

次に、図2(b)に示すように、第1の支持体2及び絶縁層1の両方を貫くように、貫通孔3を形成する。貫通孔3の形状、縦横の長さは即ち貫通孔3に形成される導電層6の形状に応じて縦横の長さを所定寸法となっている。一般的には形状は長方形で縦横の長さは0.8mm〜3.4mm×0.1mm〜1.2mmである。このような貫通孔3は、レーザ光照射の場合、レーザの種類としてCOレーザ、UV−YAGレーザ、あるいはエキシマレーザなどを使用して形成される。また、その他の方法としてドリル、パンチなどにより、貫通孔3を形成しても良い。(工程b)
次に、図2(c)に示すように、絶縁層1上に貫通孔3を塞ぐように第2の支持体5に保持された絶縁シート4を粘着させる。第2の支持体5としては、第1の支持体2に準じPETフィルム、ポリプロピレンフィルムなどが用いられる。(工程c)
次に、図2(d)に示すように、第1の支持体2の略全面及び第1の支持体2の貫通孔3から露出した絶縁シート2上に、導体材料を塗布し、内部電極となる導電層6を形成し、絶縁シート2、絶縁層1及び導電層6から構成される複合シート7を形成する。第1の支持体2の略全面及び第1の支持体2の貫通孔3から露出した絶縁シート4上に、導体材料を塗布する方法としてダイコート法、スプレーコート法などが挙げられる。
Next, as shown in FIG. 2B, the through hole 3 is formed so as to penetrate both the first support 2 and the insulating layer 1. The vertical and horizontal lengths of the through holes 3 have predetermined dimensions according to the shape of the conductive layer 6 formed in the through holes 3. In general, the shape is rectangular, and the length and width are 0.8 mm to 3.4 mm × 0.1 mm to 1.2 mm. In the case of laser beam irradiation, such a through hole 3 is formed using a CO 2 laser, a UV-YAG laser, an excimer laser, or the like as the type of laser. Moreover, you may form the through-hole 3 with a drill, a punch, etc. as another method. (Process b)
Next, as shown in FIG. 2C, the insulating sheet 4 held by the second support 5 is adhered to the insulating layer 1 so as to close the through hole 3. As the second support 5, a PET film, a polypropylene film, or the like is used according to the first support 2. (Process c)
Next, as shown in FIG. 2 (d), a conductive material is applied on the insulating sheet 2 exposed from substantially the entire surface of the first support 2 and the through holes 3 of the first support 2, and the internal electrode The conductive layer 6 is formed, and the composite sheet 7 composed of the insulating sheet 2, the insulating layer 1, and the conductive layer 6 is formed. Examples of a method for applying a conductive material on the substantially entire surface of the first support 2 and the insulating sheet 4 exposed from the through holes 3 of the first support 2 include a die coating method and a spray coating method.

ダイコート法による塗布方法では、Ni、Cu、Ag、Pd等の金属粉末に添加剤または樹脂、有機溶剤もしくは水を加えペーストを作成し、タンクよりダイコーターのスロッドダイにインキを導きヘッドノズルからペーストを吐出させ貫通孔3内の絶縁シート2表面に導電層6を形成する。なお塗布厚みはペースト粘度に応じて吐出量と成形スピードでコントロールする。   In the coating method using the die coating method, a paste is made by adding an additive or a resin, an organic solvent or water to a metal powder such as Ni, Cu, Ag, Pd, etc., and the ink is led from the tank to the die die of the die coater, and the paste from the head nozzle A conductive layer 6 is formed on the surface of the insulating sheet 2 in the through hole 3 by discharging. The coating thickness is controlled by the discharge amount and the molding speed according to the paste viscosity.

またスプレーコート法による塗布方法では、Ni、Cu、Ag、Pd等の金属粉末に添加剤または樹脂、有機溶剤もしくは水を加えペーストを作成し、タンクよりスプレーガンにインキを導きノズル部分からペーストを噴出させ貫通孔3内の絶縁シート4の表面に導電層6を形成する。なお塗布厚みはペースト粘度、スプレー圧、塗布回数等を適宜変えコントロールする。   In the spray coating method, an additive or resin, organic solvent or water is added to a metal powder such as Ni, Cu, Ag, Pd to create a paste, ink is introduced from a tank to a spray gun, and the paste is applied from the nozzle part. The conductive layer 6 is formed on the surface of the insulating sheet 4 in the through hole 3 by jetting. The coating thickness is controlled by appropriately changing the paste viscosity, spray pressure, number of coatings, and the like.

次に、図2(e)に示すように、複合シート7から、第1の支持体2を剥離し、その後、前記第1の支持体2を剥離した前記複合シート7を、順次被積層体8に積層し、しかる後に、前記第2の支持体5を剥離する。これを繰り返して大型積層体9を形成する。   Next, as shown in FIG. 2 (e), the first support 2 is peeled from the composite sheet 7, and then the composite sheets 7 from which the first support 2 is peeled are sequentially laminated. Then, the second support 5 is peeled off. This process is repeated to form the large laminate 9.

第1の支持体2を剥離する方法としては、導体材料が塗布された第1の支持体2上に粘着テープを当接させることにより、転写させる方法(ピーリング法)が挙げられる。このとき、剥離強度が絶縁シート4−第1の支持体2間より、第1の支持体2−粘着テープ間が大であることが必要である。また、確実に剥離するためには、剥離の角度θが鋭角になるように剥離することが望ましい。   As a method for peeling off the first support 2, a method (peeling method) of transferring by bringing an adhesive tape into contact with the first support 2 coated with a conductive material may be used. At this time, it is necessary for the peel strength to be greater between the first support 2 and the adhesive tape than between the insulating sheet 4 and the first support 2. Moreover, in order to peel reliably, it is desirable to peel so that peeling angle (theta) may become an acute angle.

また第1の支持体2を剥離した後の具体的な手順としては、下金型上に載置させた被積層体8と上金型との間に、第2の支持体5に裏打ちされた複合シート7を、第2の支持体5が上金型側となるように配置させた後、第2の支持体5を上金型で下金型側へ加圧加熱することにより、複合シート7を被積層体8に熱圧着する工程を繰り返すことにより、大型積層体9を形成する。   Further, as a specific procedure after the first support 2 is peeled off, the second support 5 is lined between the stacked body 8 placed on the lower mold and the upper mold. The composite sheet 7 is disposed so that the second support 5 is on the upper mold side, and then the second support 5 is pressurized and heated to the lower mold side with the upper mold, thereby combining By repeating the step of thermocompression bonding the sheet 7 to the laminate 8, the large laminate 9 is formed.

この後、この大型積層体9を各素子領域毎に切断して、未焼成状態の積層体11を得る。   Thereafter, the large laminate 9 is cut for each element region to obtain an unfired laminate 11.

さらに、この未焼成状態の積層体11を所定の雰囲気及び温度条件下で焼成して、積層体11を得る。この積層体11は、複数の複合シート7が積層されているとともに、一対の端面に導電層6が露出している。   Further, the unfired laminate 11 is fired under a predetermined atmosphere and temperature conditions to obtain the laminate 11. In the laminate 11, a plurality of composite sheets 7 are laminated, and the conductive layer 6 is exposed on a pair of end faces.

次に、外部電極12となる導体膜を積層体11の一対の端面にディップ法により形成する。さらに、導体膜は、所定の雰囲気、温度、時間を加えて焼成、外部電極12を形成する。そして、外部電極12表面にNiメッキ/Snメッキを形成する。   Next, a conductor film to be the external electrode 12 is formed on the pair of end surfaces of the multilayer body 11 by a dipping method. Further, the conductor film is baked by adding a predetermined atmosphere, temperature and time to form the external electrode 12. Then, Ni plating / Sn plating is formed on the surface of the external electrode 12.

このようにして、図1に示すような積層セラミックコンデンサ10が得られる。   In this way, a multilayer ceramic capacitor 10 as shown in FIG. 1 is obtained.

上述の積層セラミックコンデンサの製造方法において請求項2に示すように形成しても構わない。すなわち、その製造方法は工程a〜dまでは上述の製造方法と同様であるが工程eにおいて、第2の支持体5が複合シート7を被積層体8に積層する前に剥離しても構わない。その製造法の図3に示す。すなわち図3において、積層工程においては、第2の支持体5は存在しない。   You may form as shown in Claim 2 in the manufacturing method of the above-mentioned multilayer ceramic capacitor. That is, the manufacturing method is the same as the above-described manufacturing method up to steps a to d, but in step e, the second support 5 may be peeled off before the composite sheet 7 is laminated on the stack 8. Absent. The manufacturing method is shown in FIG. That is, in FIG. 3, the 2nd support body 5 does not exist in a lamination process.

また、上述の積層セラミックコンデンサの製造方法において請求項3、4に示すように形成しても構わない。すなわち、上述の製造方法では、第2の支持体5は絶縁シート4と一体化しているが、第2支持体5を省略して絶縁シート4のみを貫通孔3に被着しても構わない。その製造法の図4、5に示す。   Moreover, you may form as shown in Claim 3, 4 in the manufacturing method of the above-mentioned multilayer ceramic capacitor. That is, in the manufacturing method described above, the second support 5 is integrated with the insulating sheet 4, but the second support 5 may be omitted and only the insulating sheet 4 may be attached to the through-hole 3. . The manufacturing method is shown in FIGS.

この場合、第1の支持体2の剥離に関しては、複合シート7を被積層体8に積層する前や後に剥離しても構わない。   In this case, the first support 2 may be peeled before or after the composite sheet 7 is laminated on the laminated body 8.

図4においては、第1の支持体2の剥離は、積層工程前に剥離して、複合シート7のみの状態で、複合シート7を被積層体8に積層している。図5においては、第1の支持体2が被着されていない複合シート7面を利用して、複合シート7を被積層体8に積層し、積層したのちに、第1の支持体2を剥離している。   In FIG. 4, the first support 2 is peeled off before the laminating step, and the composite sheet 7 is laminated on the laminated body 8 in the state of only the composite sheet 7. In FIG. 5, the composite sheet 7 is laminated on the laminated body 8 using the surface of the composite sheet 7 to which the first support 2 is not attached, and after the lamination, the first support 2 is attached. It is peeling.

これらの製造方法によれば、第1の支持体2及び絶縁層1を貫通する貫通孔3を形成した後、絶縁層1表面に絶縁シート4を、貫通孔3を塞ぐようにして貼着させ、しかる後第1の支持体2の他方主面の絶縁シート4の貫通孔領域に導電層6を形成し、絶縁シート4と絶縁層1と導電層6から成る複合シート7を形成することから、絶縁層1と導電層6が重なって段差を生じることはなく、その結果、複合シート7を複数積層した場合においても、密着性の低下をまねくことが無く、内部欠陥の発生を防止出来る効果が得られる。   According to these manufacturing methods, after the through hole 3 penetrating the first support 2 and the insulating layer 1 is formed, the insulating sheet 4 is adhered to the surface of the insulating layer 1 so as to close the through hole 3. Thereafter, the conductive layer 6 is formed in the through hole region of the insulating sheet 4 on the other main surface of the first support 2, and the composite sheet 7 composed of the insulating sheet 4, the insulating layer 1, and the conductive layer 6 is formed. The insulating layer 1 and the conductive layer 6 do not overlap to form a step, and as a result, even when a plurality of composite sheets 7 are laminated, the adhesiveness is not lowered and the generation of internal defects can be prevented. Is obtained.

また、導電層をダイコート法、スプレーコート法のいずれかを用いて形成することから、導電層の表面が平坦となり、絶縁層と導電層との境界に空隙部が生じないので、積層した場合において密着性の低下をまねくことが無く、内部欠陥の発生を防止できる効果が得られる。   In addition, since the conductive layer is formed by using either the die coating method or the spray coating method, the surface of the conductive layer becomes flat, and no gap is formed at the boundary between the insulating layer and the conductive layer. The effect of preventing the occurrence of internal defects without causing a decrease in adhesion is obtained.

本発明者は、前記導電層6と絶縁層1の厚みの関係について、以下の実験を行ない、導電層6と絶縁層1の厚み差による内部欠陥発生状況を確認した。   The inventor conducted the following experiment on the relationship between the thickness of the conductive layer 6 and the insulating layer 1 and confirmed the occurrence of internal defects due to the difference in thickness between the conductive layer 6 and the insulating layer 1.

なお、試料において導電層6の印刷方法としてはダイコート法(表1)、スプレーコート法(表2)のいずれかを用い、絶縁層1の形成方法としてはダイコート法を用いた。また、試料の積層数100層として、試料数100個について調べた。 In the sample, either a die coating method (Table 1) or a spray coating method (Table 2) was used as a printing method of the conductive layer 6, and a die coating method was used as a method of forming the insulating layer 1. Further, 100 samples were examined as 100 samples.

なお、判定にあたり、良品「○」は欠陥試料が0/100個であり、1つでも欠陥の試料があれば不良「×」とした。

Figure 2006185975
In the determination, the non-defective product “◯” had 0/100 defective samples, and if there was even one defective sample, it was determined as a defective “x”.
Figure 2006185975

Figure 2006185975
Figure 2006185975

その結果、絶縁層1厚みをZt、導電層6厚みをDtと表した時、ダイコート法、スプレーコート法いずれもダイコート法の場合でも、0.67Zt≦Dt≦1.5Ztの関係で、絶縁層1の厚みと導電層6の厚みの関係を満足することで、密着不良並びに焼成時の内部欠陥を完全に無くす事が出来る。   As a result, when the thickness of the insulating layer 1 is expressed as Zt and the thickness of the conductive layer 6 is expressed as Dt, the insulating layer has a relationship of 0.67Zt ≦ Dt ≦ 1.5Zt in both cases of the die coating method and the spray coating method. By satisfying the relationship between the thickness of 1 and the thickness of the conductive layer 6, poor adhesion and internal defects during firing can be completely eliminated.

またさらに本発明は上述した実施形態に限定されるものではなく、本発明の要旨を逸脱しない範囲において種々の変更、改良等が可能である。   Furthermore, the present invention is not limited to the above-described embodiments, and various changes and improvements can be made without departing from the scope of the present invention.

例えば、上記実施の形態では、本発明の積層電子部品10を積層セラミックコンデンサに適用した例を用いて説明したが、本発明は、積層型インダクタ、積層型圧電部品、回路基板、半導体部品など、さまざまな積層電子部品10に適用できる。   For example, in the above embodiment, the multilayer electronic component 10 of the present invention has been described using an example in which the multilayer electronic component 10 is applied to a multilayer ceramic capacitor, but the present invention includes a multilayer inductor, a multilayer piezoelectric component, a circuit board, a semiconductor component, etc. The present invention can be applied to various laminated electronic components 10.

本発明および従来技術に説明した積層セラミックコンデンサ縦断面図である。1 is a longitudinal sectional view of a multilayer ceramic capacitor described in the present invention and the prior art. 本発明の積層電子部品の製造方法を示す図であり、(a)は絶縁層形成工程、(b)は貫通孔形成工程、(c)は絶縁シート粘着工程、(d)は導体層及び複合シート形成工程、(e)は第1の支持体剥離及び積層及び第2の支持体剥離工程を示す概略断面図である。It is a figure which shows the manufacturing method of the multilayer electronic component of this invention, (a) is an insulating layer formation process, (b) is a through-hole formation process, (c) is an insulation sheet adhesion process, (d) is a conductor layer and a composite. (E) is a schematic sectional view showing a first support peeling and lamination and a second support peeling step. 本発明の積層電子部品の製造方法を示す図であり、(a)は絶縁層形成工程、(b)は貫通孔形成工程、(c)は絶縁シート粘着工程、(d)は導体層及び複合シート形成工程、(e)は第1の支持体及び第2の支持体剥離及び積層工程を示す概略断面図である。It is a figure which shows the manufacturing method of the multilayer electronic component of this invention, (a) is an insulating layer formation process, (b) is a through-hole formation process, (c) is an insulation sheet adhesion process, (d) is a conductor layer and a composite. (E) is a schematic sectional view showing a first support and a second support peeling and laminating step. 本発明の積層電子部品の製造方法を示す図であり、(a)は絶縁層形成工程、(b)は貫通孔形成工程、(c)は絶縁シート粘着工程、(d)は導体層及び複合シート形成工程、(e)第1の支持体剥離及び積層工程を示す概略断面図である。It is a figure which shows the manufacturing method of the multilayer electronic component of this invention, (a) is an insulating layer formation process, (b) is a through-hole formation process, (c) is an insulation sheet adhesion process, (d) is a conductor layer and a composite. It is a schematic sectional drawing which shows a sheet | seat formation process, (e) 1st support body peeling and a lamination process. 本発明の積層電子部品の製造方法を示す図であり、(a)は絶縁層形成工程、(b)は貫通孔形成工程、(c)は絶縁シート粘着工程、(d)は導体層及び複合シート形成工程、(e)は積層及び第1の支持体剥離工程の概略断面図である。It is a figure which shows the manufacturing method of the multilayer electronic component of this invention, (a) is an insulating layer formation process, (b) is a through-hole formation process, (c) is an insulation sheet adhesion process, (d) is a conductor layer and a composite. (E) is a schematic cross-sectional view of the lamination and the first support peeling process. 従来の積層セラミックコンデンサ縦断面図である。It is a conventional multilayer ceramic capacitor longitudinal section. 従来の積層電子部品の製造方法を示す図であり、(a)絶縁層形成工程、(b)絶縁シート粘着工程、(c)第1の支持体剥離工程、(d)積層工程、(e)第2の支持体剥離工程 である。It is a figure which shows the manufacturing method of the conventional multilayer electronic component, (a) Insulating layer formation process, (b) Insulation sheet adhesion process, (c) 1st support body peeling process, (d) Lamination process, (e) It is a 2nd support body peeling process. 従来の積層電子部品の製造方法における絶縁シート、絶縁層及び導電層の断面を示す図である。It is a figure which shows the cross section of the insulating sheet in the conventional manufacturing method of a multilayer electronic component, an insulating layer, and a conductive layer. 従来の積層電子部品の製造方法における絶縁シート、絶縁層及び導電層の断面を示し、絶縁層印刷ずれの状態を示す図である。It is a figure which shows the cross section of the insulating sheet in the conventional manufacturing method of a multilayer electronic component, an insulating layer, and a conductive layer, and shows the state of an insulating layer printing shift.

符号の説明Explanation of symbols

10・・・・・・・・積層セラミックコンデンサ(積層電子部品)
11・・・・・・・・積層体
1、21、31・・・絶縁層
2、22、32・・・第1の支持体
3・・・・・・・・・貫通孔
4、24、34・・・絶縁シート
5、25、35・・・第2の支持体
6、26、36・・・導電層
7、37・・・ ・・・複合シート
8、38・・・・・・被積層体
9、39・・・ ・・・大型積層体
12・・・・・・ ・・外部電極
10 ... Multilayer ceramic capacitors (multilayer electronic components)
11... Laminated bodies 1, 21, 31... Insulating layers 2, 22, 32... First support 3. 34 ... Insulating sheets 5, 25, 35 ... Second supports 6, 26, 36 ... Conductive layers 7, 37 ... Composite sheets 8, 38 ... Laminate 9, 39 ... ... Large laminate 12 ..... External electrode

Claims (5)

絶縁層、絶縁シートおよび導体層が積層されて成る被積層体に、複合シートを積層一体してなる積層電子部品素体の製造方法であって、
第1の支持体の一方主面に、絶縁層を形成する工程aと、
前記絶縁層の所定箇所に、前記第1の支持体及び前記絶縁層を貫通する貫通孔を形成する工程bと、
前記絶縁層の表面に前記貫通孔の開口を塞ぐようにして、第2の支持体に保持された絶縁シートを貼着させる工程cと、
前記第1の支持体の他方主面側から、前記絶縁シートの前記貫通孔内に導電層を形成し、前記絶縁シートと前記絶縁層と前記導電層とから成る複合シートを形成する工程dと、
前記複合シートから前記第1の支持体を剥離した後、前記第1の支持体を剥離した前記複合シートを被積層体に積層し、しかる後前記第2の支持体を剥離する工程eと、
を具備することを特徴とする積層電子部品素体の製造方法。
A laminated electronic component body manufacturing method in which a composite sheet is laminated and integrated on a laminated body in which an insulating layer, an insulating sheet, and a conductor layer are laminated,
Forming an insulating layer on one main surface of the first support;
Forming a through-hole penetrating the first support and the insulating layer at a predetermined location of the insulating layer; and b.
A step c of adhering an insulating sheet held on the second support so as to close the opening of the through hole on the surface of the insulating layer;
Forming a conductive layer in the through hole of the insulating sheet from the other main surface side of the first support, and forming a composite sheet comprising the insulating sheet, the insulating layer, and the conductive layer; and ,
After peeling off the first support from the composite sheet, stacking the composite sheet from which the first support has been peeled off, and then peeling off the second support, e.
A method for producing a laminated electronic component body, comprising:
絶縁層、絶縁シートおよび導体層が積層されて成る被積層体に、複合シートを積層一体してなる積層電子部品素体の製造方法であって、
第1の支持体の一方主面に、絶縁層を形成する工程aと、
前記絶縁層の所定箇所に、前記第1の支持体及び前記絶縁層を貫通する貫通孔を形成する工程bと、
前記絶縁層の表面に前記貫通孔の開口を塞ぐようにして、第2の支持体に保持された絶縁シートを貼着させる工程cと、
前記第1の支持体の他方主面側から、前記絶縁シートの前記貫通孔内に導電層を形成し、前記絶縁シートと前記絶縁層と前記導電層とから成る複合シートを形成する工程dと、
前記複合シートから前記第一および第2の支持体を剥離した後、前記第一および第2の支持体から剥離した前記複合シートを被積層体に積層する工程eと、
を具備することを特徴とする積層電子部品素体の製造方法。
A laminated electronic component body manufacturing method in which a composite sheet is laminated and integrated on a laminated body in which an insulating layer, an insulating sheet, and a conductor layer are laminated,
Forming an insulating layer on one main surface of the first support;
Forming a through-hole penetrating the first support and the insulating layer at a predetermined location of the insulating layer; and b.
A step c of adhering an insulating sheet held on the second support so as to close the opening of the through hole on the surface of the insulating layer;
Forming a conductive layer in the through hole of the insulating sheet from the other main surface side of the first support, and forming a composite sheet comprising the insulating sheet, the insulating layer, and the conductive layer; and ,
After peeling the first and second supports from the composite sheet, the step e of laminating the composite sheet peeled from the first and second supports on a laminate;
A method for producing a laminated electronic component body, comprising:
絶縁層、絶縁シートおよび導体層が積層されて成る被積層体に、複合シートを積層一体してなる積層電子部品素体の製造方法であって、
第1の支持体の一方主面に、絶縁層を形成する工程aと、
前記絶縁層の所定箇所に、前記第1の支持体及び前記絶縁層を貫通する貫通孔を形成する工程bと、
前記絶縁層の表面に前記貫通孔の開口を塞ぐようにして、絶縁シートを貼着させる工程cと、
前記第1の支持体の他方主面側から、前記絶縁シートの前記貫通孔内に導電層を形成し、前記絶縁シートと前記絶縁層と前記導電層とから成る複合シートを形成する工程dと、
前記複合シートから前記第1の支持体を剥離した後、前記複合シートを被積層体に積層する工程eと、
を具備することを特徴とする積層電子部品素体の製造方法。
A laminated electronic component body manufacturing method in which a composite sheet is laminated and integrated on a laminated body in which an insulating layer, an insulating sheet, and a conductor layer are laminated,
Forming an insulating layer on one main surface of the first support;
Forming a through-hole penetrating the first support and the insulating layer at a predetermined location of the insulating layer; and b.
A step c of adhering an insulating sheet so as to block the opening of the through hole on the surface of the insulating layer;
Forming a conductive layer in the through hole of the insulating sheet from the other main surface side of the first support, and forming a composite sheet comprising the insulating sheet, the insulating layer, and the conductive layer; and ,
After peeling the first support from the composite sheet, the step e of laminating the composite sheet on a laminate;
A method for producing a laminated electronic component body, comprising:
絶縁層、絶縁シートおよび導体層が積層されて成る被積層体に、複合シートを積層一体してなる積層電子部品素体の製造方法であって、
第1の支持体の一方主面に、絶縁層を形成する工程aと、
前記絶縁層の所定箇所に、前記第1の支持体及び前記絶縁層を貫通する貫通孔を形成する工程bと、
前記絶縁層の表面に前記貫通孔の開口を塞ぐようにして、絶縁シートを貼着させる工程cと、
前記第1の支持体の他方主面側から、前記絶縁シートの前記貫通孔内に導電層を形成し、前記絶縁シートと前記絶縁層と前記導電層とから成る複合シートを形成する工程dと、
前記複合シートを被積層体に積層した後、前記第1の支持体を剥離する工程eと、
を具備することを特徴とする積層電子部品素体の製造方法。
A laminated electronic component body manufacturing method in which a composite sheet is laminated and integrated on a laminated body in which an insulating layer, an insulating sheet, and a conductor layer are laminated,
Forming an insulating layer on one main surface of the first support;
Forming a through-hole penetrating the first support and the insulating layer at a predetermined location of the insulating layer; and b.
A step c of adhering an insulating sheet so as to block the opening of the through hole on the surface of the insulating layer;
Forming a conductive layer in the through hole of the insulating sheet from the other main surface side of the first support, and forming a composite sheet comprising the insulating sheet, the insulating layer, and the conductive layer; and ,
After laminating the composite sheet on the laminate, a step e of peeling the first support;
A method for producing a laminated electronic component body, comprising:
前記導電層がダイコート法、スプレーコート法のいずれかにより形成することを特徴とする請求項1〜4に記載の積層電子部品素体の製造方法。 The method for producing a multilayer electronic component element body according to claim 1, wherein the conductive layer is formed by either a die coating method or a spray coating method.
JP2004375127A 2004-12-27 2004-12-27 Method of manufacturing multilayered electronic component element assembly Pending JP2006185975A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09326329A (en) * 1996-04-02 1997-12-16 Matsushita Electric Ind Co Ltd Ceramic multilayer device member and manufacture thereof
JPH1197285A (en) * 1997-07-24 1999-04-09 Matsushita Electric Ind Co Ltd Manufacture of multilayer ceramic electronic component
JP2000100648A (en) * 1998-09-22 2000-04-07 Sumitomo Rubber Ind Ltd Manufacture of laminated ceramic capacitor
JP2000138129A (en) * 1998-10-30 2000-05-16 Kyocera Corp Laminated ceramic capacitor and its manufacture
WO2004061880A1 (en) * 2002-12-27 2004-07-22 Tdk Corporation Method for manufacturing multilayer electronic component

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09326329A (en) * 1996-04-02 1997-12-16 Matsushita Electric Ind Co Ltd Ceramic multilayer device member and manufacture thereof
JPH1197285A (en) * 1997-07-24 1999-04-09 Matsushita Electric Ind Co Ltd Manufacture of multilayer ceramic electronic component
JP2000100648A (en) * 1998-09-22 2000-04-07 Sumitomo Rubber Ind Ltd Manufacture of laminated ceramic capacitor
JP2000138129A (en) * 1998-10-30 2000-05-16 Kyocera Corp Laminated ceramic capacitor and its manufacture
WO2004061880A1 (en) * 2002-12-27 2004-07-22 Tdk Corporation Method for manufacturing multilayer electronic component

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