JP2006179775A - Semiconductor element housing package and semiconductor device - Google Patents

Semiconductor element housing package and semiconductor device Download PDF

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JP2006179775A
JP2006179775A JP2004373182A JP2004373182A JP2006179775A JP 2006179775 A JP2006179775 A JP 2006179775A JP 2004373182 A JP2004373182 A JP 2004373182A JP 2004373182 A JP2004373182 A JP 2004373182A JP 2006179775 A JP2006179775 A JP 2006179775A
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semiconductor element
lead terminal
package
hole
semiconductor device
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Michinobu Iino
道信 飯野
Hiroyuki Nakamichi
博之 中道
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Kyocera Corp
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Kyocera Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element housing package that reduces reflection loss in a bonding wire and prevents an effect on an external electric circuit, and to provide a semiconductor device. <P>SOLUTION: The semiconductor element housing package comprises a metal substrate 1 that has a semiconductor element S mounting part 1a on the center of the top face thereof, and a through hole 1b formed around the mounting part 1a from the top face to the bottom face; and a lead terminal 3 which is inserted through the through-hole 1b, is fixed via a sealing member 2 in such a way that at least a lower end thereof projects from the through hole 1b, and an upper end thereof is electrically connected to the electrode of the semiconductor element S. A conductive projection 7 is formed in a standing state along the upper end of the lead terminal 3 in connection with an earth potential near the through hole 1b on the top face of the metal substrate 1. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、光通信分野等に用いられる光半導体素子等の半導体素子を収納するための半導体素子収納用パッケージおよびそれを用いた半導体装置に関する。   The present invention relates to a semiconductor element housing package for housing a semiconductor element such as an optical semiconductor element used in the field of optical communication and the like, and a semiconductor device using the same.

近年、40km以下の伝送距離における高速通信に対する需要が急激に増加しており、高速大容量な情報伝送に関する研究開発が進められている。とりわけ、光通信装置を用いて光信号を受発信する半導体装置等の高速化が注目されており、半導体装置による光信号の高出力化と高速化が伝送容量を向上させるための課題として研究開発されている。   In recent years, the demand for high-speed communication at a transmission distance of 40 km or less has been increasing rapidly, and research and development on high-speed and large-capacity information transmission is underway. In particular, increasing the speed of semiconductor devices that receive and transmit optical signals using optical communication devices has attracted attention, and research and development as an issue to improve transmission capacity is to increase the output and speed of optical signals by semiconductor devices. Has been.

従来の半導体装置の光出力は0.2〜0.5mW程度であり、半導体素子の駆動電力は5mW程度であった。しかし、より大出力の半導体装置では、光出力が1mWのレベルになってきており、また、半導体素子の駆動電力も10mW以上が要求されている。さらに、従来の半導体装置による伝送容量は2.5Gbps程度であったが、近年10Gbps程度まで向上してきており、半導体装置をより高出力化させ、高速化させることが要求されている。   The optical output of the conventional semiconductor device is about 0.2 to 0.5 mW, and the driving power of the semiconductor element is about 5 mW. However, in a semiconductor device having a higher output, the optical output has become a level of 1 mW, and the driving power of the semiconductor element is required to be 10 mW or more. Furthermore, although the transmission capacity of the conventional semiconductor device was about 2.5 Gbps, it has been improved to about 10 Gbps in recent years, and there is a demand for higher output and higher speed of the semiconductor device.

従来の光通信装置に用いられているLD(Laser Diode:レーザダイオード)やPD(Photo Diode:フォトダイオ−ド)等の光半導体素子を含む半導体素子を収納する半導体素子収納用パッケージ(以下、単にパッケージともいう)およびこれを用いた半導体装置を図7、図8に示す。ここで図7は、半導体装置の蓋体を外した状態でのパッケージ内側から見た平面図、図8は図7のパッケージのA−A’線断面図である。   A package for housing a semiconductor element (hereinafter simply referred to as a package for housing a semiconductor element) containing a semiconductor element including an optical semiconductor element such as an LD (Laser Diode) or a PD (Photo Diode) used in a conventional optical communication device. A package) and a semiconductor device using the same are shown in FIGS. Here, FIG. 7 is a plan view seen from the inside of the package with the lid of the semiconductor device removed, and FIG. 8 is a cross-sectional view of the package of FIG.

従来のパッケージは、上面の中央部に半導体素子S’の搭載部11aを有するとともにこの搭載部11aの周辺に上面から下面にかけて形成された直径0.5〜2mmの貫通孔11bを有する鉄(Fe)−ニッケル(Ni)−コバルト(Co)合金やFe−マンガン(Mn)合金等の金属から成る円板状の金属基板11と、貫通孔11bに挿通され、少なくとも下端部が貫通孔11bから突出するように封止材12を介して固定され、上端部が半導体素子S’の電極に電気的に接続されるFe−Ni−Co合金やFe−Ni合金等の金属から成るリード端子13と、他の貫通孔11bに挿通されるとともに金属基板11に電気的に接続された接地用リード端子13aとを具備している。   The conventional package has iron (Fe) − having a mounting portion 11a for the semiconductor element S ′ at the center of the upper surface and a through hole 11b having a diameter of 0.5 to 2 mm formed from the upper surface to the lower surface around the mounting portion 11a. A disc-shaped metal substrate 11 made of a metal such as a nickel (Ni) -cobalt (Co) alloy or an Fe-manganese (Mn) alloy is inserted into the through hole 11b so that at least the lower end protrudes from the through hole 11b. A lead terminal 13 made of a metal such as an Fe-Ni-Co alloy or Fe-Ni alloy, whose upper end is electrically connected to the electrode of the semiconductor element S ', And a ground lead terminal 13a that is inserted into the through hole 11b and electrically connected to the metal substrate 11.

そして、このパッケージの搭載部11aに搭載に半導体素子S’を搭載するとともに、その電極をリード端子13の上端部に電気的に接続し、半導体素子S’を覆うように金属基板11の上面に蓋体16を接合することにより半導体装置となる。   Then, the semiconductor element S ′ is mounted on the mounting portion 11a of the package, and the electrode is electrically connected to the upper end portion of the lead terminal 13 so that the semiconductor element S ′ is covered on the upper surface of the metal substrate 11. By joining the lid 16, a semiconductor device is obtained.

なお、金属基板11とリード端子13との接合はホウケイ酸を主成分とする絶縁ガラスを介して行なわれ、絶縁ガラスによって金属基板11とリード端子13とが電気的に絶縁されている。接地用リード端子13aは金属基板11に銀(Ag)−銅(Cu)等の高融点ロウ材によりロウ付け固定され、外部電気回路(図示せず)の接地導体層と鉛(Pb)−錫(Sn)半田などの半田材にて電気的に接続される。また、半導体素子S’は、金属基板11に200〜400℃の融点を有する金(Au)−Sn等の低融点ロウ材によりロウ付け固定され、半導体素子S’の電極がボンディングワイヤ14を介してリード端子13に電気的に接続される。   The metal substrate 11 and the lead terminal 13 are joined via an insulating glass containing borosilicate as a main component, and the metal substrate 11 and the lead terminal 13 are electrically insulated by the insulating glass. The ground lead terminal 13a is fixed to the metal substrate 11 by brazing with a high melting point brazing material such as silver (Ag) -copper (Cu), and a ground conductor layer of an external electric circuit (not shown) and lead (Pb) -tin. (Sn) It is electrically connected with a solder material such as solder. The semiconductor element S ′ is brazed and fixed to the metal substrate 11 with a low melting point brazing material such as gold (Au) —Sn having a melting point of 200 to 400 ° C., and the electrode of the semiconductor element S ′ is bonded via the bonding wire 14. And electrically connected to the lead terminal 13.

また、金属基板11の上面には、外周端から幅1mm以内の外周部に、半導体素子S’の保護を目的として、Fe−Ni−Co合金等から成る蓋体16がYAGレーザ溶接、シーム溶接またはロウ付け等接合されることにより製品としての半導体装置となる。   On the upper surface of the metal substrate 11, a lid 16 made of an Fe-Ni-Co alloy or the like is provided on the outer peripheral portion within 1 mm in width from the outer peripheral end for the purpose of protecting the semiconductor element S '. Or it becomes a semiconductor device as a product by joining by brazing.

なお、この蓋体16には図8に示すように、半導体素子S’と対向する部分に光ファイバ15を固定したり、半導体素子S’と対向する部分に光を透過させる窓を設けたりすることもある。   As shown in FIG. 8, the lid 16 is provided with an optical fiber 15 fixed to a portion facing the semiconductor element S ′ or a window through which light is transmitted at a portion facing the semiconductor element S ′. Sometimes.

この半導体装置は大容量の光通信等に使用され、外部電気回路(図示せず)から供給される駆動信号によって半導体素子S’を光励起させ、励起された光を戻り光防止用の光アイソレータ(図示せず)を介して光ファイバ15に授受させるとともに光ファイバ15内に伝達させる。そして、40km以下の伝送距離における2.5Gbps(Giga bit per second)以下の伝送容量の通信に多用されている。
特開平8−130266号公報
This semiconductor device is used for large-capacity optical communication and the like, and a semiconductor device S ′ is optically excited by a drive signal supplied from an external electric circuit (not shown), and the excited light is returned to an optical isolator for preventing return light ( The optical fiber 15 is transmitted / received through the optical fiber 15 via the optical fiber 15 (not shown). It is often used for communications with a transmission capacity of 2.5 Gbps (Gigabit per second) or less over a transmission distance of 40 km or less.
JP-A-8-130266

しかしながら、上記従来のパッケージに、10GHz以上の高周波信号で駆動される半導体素子S’を搭載し、駆動しようとすると、半導体素子S’のボンディングワイヤ14における誘導成分が大きくなり、ボンディングワイヤ14における反射損失が増大し、半導体素子S’が誤動作するという問題点があった。   However, when a semiconductor element S ′ that is driven by a high-frequency signal of 10 GHz or more is mounted on the conventional package, an inductive component in the bonding wire 14 of the semiconductor element S ′ increases, and reflection on the bonding wire 14 occurs. There is a problem that the loss increases and the semiconductor element S ′ malfunctions.

これは、従来のパッケージでは、ボンディングワイヤ14における特性インピーダンスが他の部位における特性インピーダンスの値から大きめにずれて、誘導成分をもつためである。   This is because in the conventional package, the characteristic impedance of the bonding wire 14 is slightly shifted from the value of the characteristic impedance in the other part and has an inductive component.

従って、本発明は上記従来の問題点に鑑みて完成されたものであり、その目的は、ボンディングワイヤにおける反射損失を低減し、外部電気回路の特性に影響を与えることを防ぐ半導体素子収納用パッケージおよび半導体装置を提供することにある。   Accordingly, the present invention has been completed in view of the above-described conventional problems, and an object thereof is to reduce a reflection loss in a bonding wire and prevent a semiconductor element storage package from affecting the characteristics of an external electric circuit. Another object is to provide a semiconductor device.

本発明の半導体素子収納用パッケージは、上面の中央部に半導体素子の搭載部を有するとともに該搭載部の周辺に前記上面から下面にかけて形成された貫通孔を有する金属基板と、前記貫通孔に挿通され、少なくとも下端部が前記貫通孔から突出するように封止材を介して固定されるとともに上端部が前記半導体素子の電極に電気的に接続されるリード端子とを具備している半導体素子収納用パッケージにおいて、前記金属基板の上面で、前記貫通孔の近傍に、接地電位に接続された上、前記リード端子の上端部と並んで立設される導電性の突起部を形成したことを特徴とする。   The semiconductor element storage package of the present invention includes a metal substrate having a semiconductor element mounting portion at the center of the upper surface and a through-hole formed in the periphery of the mounting portion from the upper surface to the lower surface, and inserted into the through hole. A semiconductor element housing having a lead terminal which is fixed through a sealing material so that at least a lower end portion protrudes from the through-hole, and an upper end portion is electrically connected to an electrode of the semiconductor element In the package for use, on the upper surface of the metal substrate, in the vicinity of the through-hole, a conductive projection is provided that is connected to the ground potential and is erected along with the upper end of the lead terminal. And

また本発明の半導体素子収納用パッケージにおいて、好ましくは前記突起部を平面視して円弧状としたことを特徴とする。   In the package for housing a semiconductor element according to the present invention, it is preferable that the projection is formed in an arc shape when seen in a plan view.

また本発明の半導体素子収納用パッケージにおいて、好ましくは前記突起部を前記リード端子の周囲に全周にわたって取り囲むように形成したことを特徴とする。   In the package for housing a semiconductor element according to the present invention, it is preferable that the protrusion is formed around the lead terminal so as to surround the entire circumference.

また本発明の半導体装置は、本発明の半導体素子収納用パッケージと、前記搭載部に搭載するとともに電極を前記リード端子に電気的に接続した半導体素子と、前記半導体素子を覆う封止部材とを具備していることを特徴とする。   The semiconductor device of the present invention includes a semiconductor element storage package of the present invention, a semiconductor element mounted on the mounting portion and having an electrode electrically connected to the lead terminal, and a sealing member covering the semiconductor element. It is characterized by having.

本発明の半導体素子収納用パッケージによれば、金属基板の上面で、貫通孔の近傍に、接地電位に接続された上、リード端子の上端部と並んで立設される導電性の突起部を形成したことから、突起部が半導体素子の接地用電極の電位と近似し、リード端子の上端部とボンディングワイヤとの接続部の接地電位を突起部によって強化することができ、伝送特性を良好にすることができる。また、この突起部を直接、半導体素子の接地用電極にボンディングワイヤで電気的に接続することにより、突起部と半導体素子の接地用電極との電位差がきわめて小さくなり、リード端子の上端部とボンディングワイヤとの接続部に対する接地電位をより強化することができる。   According to the package for housing a semiconductor element of the present invention, the conductive protrusions which are connected to the ground potential on the upper surface of the metal substrate in the vicinity of the through hole and are erected along with the upper end portion of the lead terminal. As a result, the protruding portion approximates the potential of the grounding electrode of the semiconductor element, and the ground potential of the connection portion between the upper end portion of the lead terminal and the bonding wire can be strengthened by the protruding portion, and transmission characteristics are improved. can do. In addition, by connecting the protrusion directly to the grounding electrode of the semiconductor element with a bonding wire, the potential difference between the protrusion and the grounding electrode of the semiconductor element becomes extremely small. The ground potential for the connection portion with the wire can be further strengthened.

これにより、リード端子と半導体素子とを電気的に接続するボンディングワイヤにて発生する誘導成分を低減し、ボンディングワイヤでの特性インピーダンスを他の部位の特性インピーダンスの値に近づけることができ、ボンディングワイヤにおける反射損失を低減し、外部電気回路の特性に影響を与えることを防ぐことができる。   As a result, the inductive component generated in the bonding wire that electrically connects the lead terminal and the semiconductor element can be reduced, and the characteristic impedance of the bonding wire can be brought close to the value of the characteristic impedance of other parts. It is possible to reduce the reflection loss at and to affect the characteristics of the external electric circuit.

本発明の半導体素子収納用パッケージによれば、突起部を平面視して円弧状としたことから、リード端子の上端部とボンディングワイヤとの接続部に対し、より良好に突起部で接地電位の強化を行なうことができ、より反射損失を低減し、外部電気回路の特性に影響を与えることを防ぐことができる。   According to the package for housing a semiconductor element of the present invention, since the projecting portion has an arc shape in plan view, the projecting portion has a better ground potential than the connection portion between the upper end portion of the lead terminal and the bonding wire. Strengthening can be performed, reflection loss can be further reduced, and influence on the characteristics of the external electric circuit can be prevented.

本発明の半導体素子収納用パッケージによれば、突起部をリード端子の周囲に全周にわたって取り囲むように形成したことから、リード端子の上端部とボンディングワイヤとの接続部を同軸状に突起部で取り囲むことによって接地電位を極めて良好に強化することができ、伝送特性をきわめて高くすることができる。   According to the package for housing a semiconductor element of the present invention, since the protruding portion is formed so as to surround the entire circumference of the lead terminal, the connecting portion between the upper end portion of the lead terminal and the bonding wire is coaxially formed by the protruding portion. By surrounding, the ground potential can be strengthened very well, and the transmission characteristics can be made extremely high.

本発明の半導体装置によれば、上記の半導体素子収納用パッケージと、搭載部に搭載するとともに電極をリード端子に電気的に接続した半導体素子と、半導体素子を覆う封止部材とを具備していることから、高周波信号によって半導体装置が駆動されても、高周波信号がボンディングワイヤにて反射されて、半導体素子が誤動作するような影響を与えることのない半導体装置を提供することができる。   According to a semiconductor device of the present invention, the semiconductor device housing package described above, a semiconductor device mounted on a mounting portion and having an electrode electrically connected to a lead terminal, and a sealing member covering the semiconductor device are provided. Therefore, even when the semiconductor device is driven by a high-frequency signal, the semiconductor device can be provided in which the high-frequency signal is reflected by the bonding wire and the semiconductor element does not malfunction.

次に、本発明の半導体素子収納用パッケージおよび半導体装置について添付の図面に基づいて詳細に説明する。   Next, a semiconductor element housing package and a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

図1は、本発明の半導体素子収納用パッケージおよび半導体装置の実施の形態の一例として、半導体素子に光半導体素子を用いた光半導体素子収納用パッケージおよび光半導体装置を示す図であり、ここで図1は、半導体装置の蓋体を外した状態でのパッケージ内側から見た平面図、図2は図1の半導体装置のA−A’線断面図、図3は図1の半導体装置のB−B’線断面図である。   FIG. 1 is a diagram showing an optical semiconductor element storage package and an optical semiconductor device using an optical semiconductor element as a semiconductor element, as an example of an embodiment of a semiconductor element storage package and a semiconductor device according to the present invention. 1 is a plan view seen from the inside of the package with the lid of the semiconductor device removed, FIG. 2 is a cross-sectional view taken along the line AA ′ of the semiconductor device of FIG. 1, and FIG. 3 is B of the semiconductor device of FIG. FIG.

これらの図において、1は金属基板、1aは半導体素子の搭載部、2は封止材、3はリード端子、7は突起部であり、これらで本発明のパッケージが基本的に構成される。また、このパッケージと半導体素子Sと蓋体6とで本発明の半導体装置が基本的に構成される。   In these figures, 1 is a metal substrate, 1a is a semiconductor element mounting portion, 2 is a sealing material, 3 is a lead terminal, and 7 is a protrusion, and these basically constitute the package of the present invention. The package, the semiconductor element S, and the lid 6 basically constitute a semiconductor device of the present invention.

なお、図1、図2および図3には、1個の半導体素子Sを搭載し、4つの貫通孔1bを形成した例を示しているが、複数の半導体素子Sを搭載してもよい。また、貫通孔1bも4つに限らず、4つ以上あるいは4つ以下でもよい。   1, 2 and 3 show an example in which one semiconductor element S is mounted and four through holes 1b are formed. However, a plurality of semiconductor elements S may be mounted. Further, the number of through holes 1b is not limited to four, and may be four or more or four or less.

金属基板1は、上面の中央部に半導体素子Sの搭載部1aを有するとともに搭載された半導体素子Sが発生する熱をパッケージの外部に放散する機能を有し、搭載部1aの周辺には上面から下面にかけて形成された直径1.15〜2.65mmの貫通孔1bを有する。また、金属基板1の形状は、例えば直径3.0〜6.0mmの円板状,半径1.5〜8.0mmの円周の一部を切り取った半円板状,一辺3.0〜15mmの四角板状等で、厚みが0.5〜2mmの平板状である。   The metal substrate 1 has a mounting portion 1a for the semiconductor element S at the center of the upper surface and has a function of radiating heat generated by the mounted semiconductor element S to the outside of the package. And a through hole 1b having a diameter of 1.15 to 2.65 mm formed from the bottom surface to the bottom surface. Moreover, the shape of the metal substrate 1 is, for example, a disc shape having a diameter of 3.0 to 6.0 mm, a semicircular shape obtained by cutting a part of the circumference having a radius of 1.5 to 8.0 mm, a square plate shape having a side of 3.0 to 15 mm, and the like. The plate has a thickness of 0.5 to 2 mm.

このような金属基板1は、Fe−Ni−Co合金やFe−Mn合金等の金属から成り、例えば金属基板1がFe−Mn合金から成る場合は、このインゴット(塊)に圧延加工や打ち抜き加工等の従来周知の金属加工方法を施すことによって所定形状に製作される。   Such a metal substrate 1 is made of a metal such as an Fe—Ni—Co alloy or an Fe—Mn alloy. For example, when the metal substrate 1 is made of an Fe—Mn alloy, the ingot (lumb) is rolled or punched. It is manufactured in a predetermined shape by applying a conventionally well-known metal processing method.

また、金属基板1の表面には耐食性に優れ、ロウ材との濡れ性に優れた厚さ0.5〜9μmのNi層と厚さ0.5〜5μmのAu層とをめっき法により順次被着させておくのがよい。これにより、金属基板1が酸化腐食するのを有効に防止するとともに各部品を金属基板1に良好にロウ付けすることができる。   Further, a Ni layer having a thickness of 0.5 to 9 μm and an Au layer having a thickness of 0.5 to 5 μm, which are excellent in corrosion resistance and excellent in wettability with a brazing material, are sequentially deposited on the surface of the metal substrate 1 by a plating method. It is good. Thereby, it is possible to effectively prevent the metal substrate 1 from being oxidatively corroded and to braze each component to the metal substrate 1 satisfactorily.

なお、金属基板1の厚みは0.5mm以上2mm以下が好ましい。厚みが0.5mm未満の場合、後述する蓋体6を金属基体1の上面に接合する際に、接合温度等の接合条件により金属基板1が曲がったりして変形し易くなり、厚みが2mmを超えると、パッケージや半導体装置の厚みが不要に厚いものとなり小型化し難くなる。   The thickness of the metal substrate 1 is preferably 0.5 mm or more and 2 mm or less. When the thickness is less than 0.5 mm, when the lid body 6 to be described later is bonded to the upper surface of the metal substrate 1, the metal substrate 1 is easily bent and deformed depending on the bonding conditions such as the bonding temperature, and the thickness exceeds 2 mm. As a result, the thickness of the package or semiconductor device becomes unnecessarily thick, making it difficult to reduce the size.

金属基板1に形成された貫通孔1bには、リード端子3が挿通され、少なくとも下端部が貫通孔1bから突出するように封止材2を介して固定される。リード端子3の金属基板1の上端部は、半導体素子Sの電極にボンディングワイヤ4を介して電気的に接続されることによって、リード端子3は半導体素子Sと外部電気回路(図示せず)との間の入出力信号を伝送する機能をなす。なお、リード端子3は、少なくとも下端部が貫通孔1bから1〜20mm程度突出するように封止材2を介して固定され、上端部は貫通孔1bから0〜2mm程度突出する。   The lead terminal 3 is inserted into the through hole 1b formed in the metal substrate 1, and is fixed via the sealing material 2 so that at least the lower end portion protrudes from the through hole 1b. The upper end portion of the metal substrate 1 of the lead terminal 3 is electrically connected to the electrode of the semiconductor element S via the bonding wire 4 so that the lead terminal 3 is connected to the semiconductor element S and an external electric circuit (not shown). The function to transmit input / output signals between. The lead terminal 3 is fixed via the sealing material 2 so that at least the lower end portion protrudes from the through hole 1b by about 1 to 20 mm, and the upper end portion protrudes from the through hole 1b by about 0 to 2 mm.

リード端子3の上端部は半導体素子Sの電極に電気的に接続されるので、貫通孔1bは搭載部1aの周辺の近い位置に配置され、例えば搭載部1aから平面視距離で0.1〜5mmの位置に形成される。貫通孔1bが搭載部1aの周辺の近い位置に配置されると、半導体素子Sの電極に接続するボンディングワイヤ4の長さを短くできるので、ボンディングワイヤ4での誘導成分の影響を小さくすることができる。   Since the upper end portion of the lead terminal 3 is electrically connected to the electrode of the semiconductor element S, the through hole 1b is disposed at a position near the periphery of the mounting portion 1a, for example, 0.1 to 5 mm in plan view distance from the mounting portion 1a. Formed in position. When the through-hole 1b is disposed at a position near the periphery of the mounting portion 1a, the length of the bonding wire 4 connected to the electrode of the semiconductor element S can be shortened, so that the influence of the inductive component on the bonding wire 4 is reduced. Can do.

リード端子3は、Fe−Ni−Co合金やFe−Ni合金等の金属から成り、例えばリード端子3がFe−Ni−Co合金から成る場合は、このインゴット(塊)を圧延加工や打ち抜き加工等の従来周知の金属加工方法を施すことによって、長さが1.5〜22mm、直径が0.1〜1mmの線状に製作される。   The lead terminal 3 is made of a metal such as an Fe—Ni—Co alloy or an Fe—Ni alloy. For example, when the lead terminal 3 is made of an Fe—Ni—Co alloy, the ingot (lumb) is rolled or punched. By applying a conventionally known metal processing method, a wire having a length of 1.5 to 22 mm and a diameter of 0.1 to 1 mm is manufactured.

封止材2は、ガラスやセラミックスなどの無機材料から成り、リード端子3と金属基板1との絶縁間隔を確保するとともに、リード端子3を金属基板1の貫通孔1bに固定する機能を有す。   The sealing material 2 is made of an inorganic material such as glass or ceramics, and has a function of securing an insulation interval between the lead terminal 3 and the metal substrate 1 and fixing the lead terminal 3 to the through hole 1 b of the metal substrate 1. .

そして、封止材2がガラスから成る場合は、内径がリード端子3の外径より大きく、外径が金属基板1の貫通孔1bの内径より小さい筒状に成形された封止材2を貫通孔1bに挿入し、リード端子3をこの封止材2に挿通し、しかる後、所定の温度に加熱して封止材2を溶融させることにより、リード端子3が同軸状とされて封止材2に埋め込まれるとともに貫通孔1bに挿通されたリード端子3が貫通孔1bに気密に固定された本発明のパッケージが製作される。   When the sealing material 2 is made of glass, the inner diameter is larger than the outer diameter of the lead terminal 3, and the outer diameter is smaller than the inner diameter of the through hole 1b of the metal substrate 1. The lead terminal 3 is inserted into the hole 1b, the lead terminal 3 is inserted into the sealing material 2, and then heated to a predetermined temperature to melt the sealing material 2, so that the lead terminal 3 is coaxial and sealed. The package of the present invention is manufactured in which the lead terminal 3 embedded in the material 2 and inserted through the through hole 1b is airtightly fixed to the through hole 1b.

本発明のパッケージによれば、金属基板1の上面で、貫通孔1bの近傍に、接地電位に接続された上、リード端子3の上端部と並んで立設される導電性の突起部7を形成したことにより、半導体素子Sとリード端子3とを電気的に接続するボンディングワイヤ4の近傍に接地用のボンディングワイヤを突起部7と半導体素子Sに配置することができる。一般的にボンディングワイヤ7は誘導成分が高く、特性インピーダンスが大きめにずれる。この誘導成分を低減させるために、接地用のボンディングワイヤを近傍に配置し、誘導成分を低減させる。   According to the package of the present invention, the conductive protrusion 7 that is connected to the ground potential on the upper surface of the metal substrate 1 in the vicinity of the through hole 1 b and is erected along with the upper end of the lead terminal 3 is provided. The formation of the bonding wire for grounding in the vicinity of the bonding wire 4 that electrically connects the semiconductor element S and the lead terminal 3 to the protruding portion 7 and the semiconductor element S can be achieved. In general, the bonding wire 7 has a high inductive component, and the characteristic impedance shifts slightly. In order to reduce this inductive component, a bonding wire for grounding is arranged in the vicinity to reduce the inductive component.

本発明の突起部7は金属基板1の上面で貫通孔1bの近傍に接地電位と接続されるように設けられている。この近傍とはリード端子3と電気的影響を与えることのできる範囲であり、具体的には、リード端子3と突起部7との間の間隔が0.05〜1mmであるのがよい。1mmを超えるとリード端子3に対する接地電位の強化が困難になりやすい。また、0.05mm未満では、リード端子3と突起部7とが接触しやすくなる。   The protrusion 7 of the present invention is provided on the upper surface of the metal substrate 1 in the vicinity of the through hole 1b so as to be connected to the ground potential. This vicinity is a range in which the lead terminal 3 can be electrically affected. Specifically, the distance between the lead terminal 3 and the protrusion 7 is preferably 0.05 to 1 mm. If it exceeds 1 mm, it is difficult to strengthen the ground potential with respect to the lead terminal 3. Moreover, if it is less than 0.05 mm, the lead terminal 3 and the protrusion part 7 will be easy to contact.

突起部7はFe−Ni−Co合金やFe−Ni合金等から成り、金属基板1に200〜400℃の融点を有するAu−Sn等のロウ材によりロウ付けされて固定される。好ましくはその上端部を半導体素子Sの接地用電極にボンディングワイヤ4を介して電気的に接続するのがよい。突起部7は金属基板1とインゴット(塊)を圧延加工や打ち抜き加工等の従来周知の金属加工方法を施すことによって、一体とする形状でもよい。   The protrusion 7 is made of an Fe—Ni—Co alloy, Fe—Ni alloy, or the like, and is fixed to the metal substrate 1 by brazing with a brazing material such as Au—Sn having a melting point of 200 to 400 ° C. Preferably, the upper end thereof is electrically connected to the grounding electrode of the semiconductor element S via the bonding wire 4. The protrusion 7 may have a shape in which the metal substrate 1 and the ingot (lumb) are integrated by applying a conventionally known metal processing method such as rolling or punching.

半導体素子Sは、搭載部1aに200〜400℃の融点を有するAu−Sn等のロウ材によりロウ付けされて固定され、しかる後、その電極をボンディングワイヤ4を介してリード端子3の上端部に電気的に接続される。半導体素子Sとしては、LD(レーザーダイオード)やPD(フォトダイオ−ド),等の例が挙げられる。   The semiconductor element S is fixed to the mounting portion 1a by brazing with a brazing material such as Au—Sn having a melting point of 200 to 400 ° C. After that, the electrode is connected to the upper end portion of the lead terminal 3 via the bonding wire 4. Is electrically connected. Examples of the semiconductor element S include LD (laser diode) and PD (photodiode).

そして、金属基板1の上面の外周端から幅1mm程度以内の外周部に、Fe−Ni合金や、Fe−Ni−Co合金、Fe−Mn合金等から成る、蓋体6をYAGレーザ溶接,シーム溶接またはロウ付け等で接合することにより半導体素子Sを気密に封止し、半導体装置となる。   Then, a lid 6 made of Fe—Ni alloy, Fe—Ni—Co alloy, Fe—Mn alloy or the like is attached to the outer peripheral portion within a width of about 1 mm from the outer peripheral edge of the upper surface of the metal substrate 1 by YAG laser welding, seam. By joining by welding or brazing, the semiconductor element S is hermetically sealed and a semiconductor device is obtained.

このような蓋体6は、半導体素子Sと対向する部位に光ファイバ5と戻り光防止用の光アイソレータ(図示せず)とが樹脂接着剤で接着されていてもよい。あるいは、半導体素子Sと対向する部位に光を透過させる窓が形成されていてもよい。   In such a lid 6, an optical fiber 5 and an optical isolator (not shown) for preventing return light may be bonded to a portion facing the semiconductor element S with a resin adhesive. Or the window which permeate | transmits light may be formed in the site | part facing the semiconductor element S. FIG.

さらには、光を透過させるための窓を有する蓋体6と光ファイバ5を固定した蓋体6とを複数接合させてもよい。   Furthermore, a plurality of lid bodies 6 having windows for transmitting light and lid bodies 6 to which optical fibers 5 are fixed may be joined.

また、蓋体6の窓には、平板やボールレンズ、非球面レンズなどの各種形状の窓部材が低融点ガラス等により接合されてもよい。この窓部材により半導体素子Sから発光される光を集光させることができる。   In addition, various shapes of window members such as a flat plate, a ball lens, and an aspherical lens may be joined to the window of the lid 6 with a low-melting glass or the like. The light emitted from the semiconductor element S can be collected by this window member.

蓋体6は、例えばFe−Mn合金から成る場合は、このインゴット(塊)を圧延加工や打ち抜き加工等の従来周知の金属加工方法を施すことによって製作される。   When the lid 6 is made of, for example, an Fe—Mn alloy, the ingot (lumb) is manufactured by applying a conventionally known metal processing method such as rolling or punching.

本発明の半導体装置によれば、上記の本発明の半導体素子収納用パッケージを具備することから、10GHz以上の高周波信号において半導体装置が駆動されても、蓋体6から高周波信号が電磁波となって不要輻射されるのを抑止し、この電磁波が半導体装置の周辺に配置された外部電気回路の信号波形に歪みを発生させることを抑止するので、外部電気回路の特性に影響を与えることのない半導体装置とすることができる。   According to the semiconductor device of the present invention, since the semiconductor element storage package of the present invention is provided, even if the semiconductor device is driven with a high-frequency signal of 10 GHz or more, the high-frequency signal is converted into an electromagnetic wave from the lid 6. A semiconductor that does not affect the characteristics of the external electric circuit because it suppresses unwanted radiation and prevents the electromagnetic wave from distorting the signal waveform of the external electric circuit placed around the semiconductor device. It can be a device.

かくして、本発明の半導体素子収納用パッケージおよび半導体装置によれば、金属基板1の貫通孔1bにリード端子3に同軸状とされて封止材2に埋め込まれた金属製の筒状部材4が金属基板1と封止材2を介して絶縁されるように固定されることから、10GHz以上の高周波信号において半導体装置が駆動されても、リード端子3に流れる高周波信号の電荷による高周波電流によって誘起された高周波電流が金属基板1や蓋体6に流れるのを防ぐことができ、この高周波電流が蓋体6から電磁波として放射されて、半導体装置の周辺に配置された外部電気回路に流れる信号波形が歪むことを抑止するので、外部電気回路を安定して動作させることができる半導体素子収納用パッケージおよび半導体装置となる。   Thus, according to the semiconductor element housing package and the semiconductor device of the present invention, the metal cylindrical member 4 which is coaxial with the lead terminal 3 and embedded in the sealing material 2 in the through hole 1b of the metal substrate 1 is provided. Since it is fixed so as to be insulated through the metal substrate 1 and the sealing material 2, even if the semiconductor device is driven with a high frequency signal of 10 GHz or more, it is induced by a high frequency current due to the charge of the high frequency signal flowing through the lead terminal 3. The generated high-frequency current can be prevented from flowing to the metal substrate 1 and the lid 6, and the high-frequency current is radiated as an electromagnetic wave from the lid 6 and flows into an external electric circuit arranged around the semiconductor device. Therefore, the semiconductor element storing package and the semiconductor device capable of stably operating the external electric circuit are obtained.

本発明の半導体装置と比較用の試料とを作製して結果を比較した。   The semiconductor device of the present invention and a comparative sample were manufactured and the results were compared.

本発明の半導体装置となる評価用の半導体装置を以下のように作製した。まず、Fe99.6%−Mn0.4%系のSPC(Steel Plate Cold)材から成る厚み1.0mm×直径5.6mmの板材に厚み1.5mm×直径3.0mmの円柱状の搭載部1aを切削加工により設けた金属基板1の中央部に、打ち抜き加工により直径0.7mmの貫通孔1bを形成した。そして、金属基板1の貫通孔1bに長さ1.0mm×内径0.3mm×外径0.7mmの筒状に成形した低融点ガラスから成る封止材2にFe68%−Ni42%合金から成る長さ15mm×直径0.3mmのリード端子3を挿入し、700℃の炉中にてガラスを溶融させることにより貫通孔1aを気密封止した。   An evaluation semiconductor device to be a semiconductor device of the present invention was manufactured as follows. First, a cylindrical mounting portion 1a having a thickness of 1.5 mm and a diameter of 3.0 mm is cut by a cutting process on a plate material having a thickness of 1.0 mm and a diameter of 5.6 mm made of an SPC (Steel Plate Cold) material of Fe99.6% -Mn0.4%. A through-hole 1b having a diameter of 0.7 mm was formed in the center of the provided metal substrate 1 by punching. The sealing material 2 made of low-melting glass formed into a cylindrical shape having a length of 1.0 mm, an inner diameter of 0.3 mm and an outer diameter of 0.7 mm in the through hole 1b of the metal substrate 1 has a length of 15 mm made of Fe68% -Ni42% alloy. X A lead terminal 3 having a diameter of 0.3 mm was inserted, and the through-hole 1a was hermetically sealed by melting glass in a furnace at 700 ° C.

さらに、金属基板1およびリード端子3の露出した表面には、厚さ2μmのNi層と厚さ2μmのAu層とをめっき法により順次被着させた。その後、金属基板1の搭載部1aに半導体素子SとなるレーザダイオードとFe68%−Ni42%合金から成る0.2mm×0.2mm×高さ0.5mmの突起部7をAu−Snロウ材にてロウ付けして搭載し、その後半導体素子Sの電極とリード端子3の上端部とをボンディングワイヤにて電気的に接続した。   Furthermore, a Ni layer having a thickness of 2 μm and an Au layer having a thickness of 2 μm were sequentially deposited on the exposed surfaces of the metal substrate 1 and the lead terminals 3 by a plating method. Thereafter, a projection 7 having a size of 0.2 mm × 0.2 mm × 0.5 mm in height made of a laser diode serving as a semiconductor element S and a Fe68% -Ni42% alloy is brazed to the mounting portion 1a of the metal substrate 1 with an Au—Sn brazing material After that, the electrode of the semiconductor element S and the upper end portion of the lead terminal 3 were electrically connected by a bonding wire.

そして、Fe−Ni−Co合金から成る内径3.9mm×外径4.2mm×高さ2.4mmのキャップ形状の蓋体6を金属基板1の上面の外周部にシーム溶接により接合して半導体素子Sを気密封止し、評価用の半導体装置を作製した。   Then, a cap-shaped lid body 6 made of Fe—Ni—Co alloy having an inner diameter of 3.9 mm, an outer diameter of 4.2 mm, and a height of 2.4 mm is joined to the outer peripheral portion of the upper surface of the metal substrate 1 by seam welding. A semiconductor device for evaluation was fabricated by hermetically sealing.

次に、本発明の他の実施の形態として、突起部7を内径0.7mm×外径1.3mm×高さ0.5mmの円弧状の形状にしたものを作製した。   Next, as another embodiment of the present invention, a projection 7 having an arc shape with an inner diameter of 0.7 mm, an outer diameter of 1.3 mm, and a height of 0.5 mm was produced.

次に、比較用としての従来の半導体装置を準備した。従来の半導体装置は、金属基板11に形成された0.7mmの貫通孔11bにリード端子13が封止材12を介して接合固定されており、突起部7が設けられていない他は、上記の評価用の半導体装置と同じものである。   Next, a conventional semiconductor device for comparison was prepared. In the conventional semiconductor device, the lead terminal 13 is bonded and fixed to the 0.7 mm through-hole 11b formed in the metal substrate 11 via the sealing material 12, and the protrusion 7 is not provided. It is the same as the semiconductor device for evaluation.

上記試料をシミュレータ(アンソフト(株)製、HFSS)にてシミュレーションを行い、その際の反射損失(S11)を比較した。シミュレーションの周波数は1〜20GHzとし、その範囲での最も悪い反射損失の値を表1に示す。

Figure 2006179775
The sample was simulated by a simulator (HFSS, manufactured by Ansoft Corporation), and the reflection loss (S11) at that time was compared. The frequency of simulation is 1 to 20 GHz, and Table 1 shows the worst reflection loss values in that range.
Figure 2006179775

表1に示されるように、突起部7を設けることにより、反射損失が低減されている。   As shown in Table 1, the reflection loss is reduced by providing the protrusion 7.

なお、本発明は、上述の実施の形態の例および実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲内であれば種々の変更は可能である。例えば、2.5Gbpsといった低速通信でも使用することは可能である。   The present invention is not limited to the above-described embodiments and examples, and various modifications can be made without departing from the scope of the present invention. For example, it can be used for low-speed communication such as 2.5 Gbps.

本発明の半導体素子収納用パッケージおよび半導体装置の実施の形態の一例を示したもので、蓋体を外した状態での平面図である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a semiconductor element storage package and a semiconductor device according to an embodiment of the present invention, with a lid removed. 図1の半導体素子収納用パッケージおよび半導体装置のA−A’線での断面図である。FIG. 2 is a cross-sectional view taken along line A-A ′ of the semiconductor element storage package and the semiconductor device of FIG. 1. 図1の半導体素子収納用パッケージおよび半導体装置のB−B’線での断面図である。FIG. 2 is a cross-sectional view taken along line B-B ′ of the semiconductor element storage package and the semiconductor device of FIG. 1. 本発明の半導体素子収納用パッケージおよび半導体装置の実施の形態の他の形態を示したもので、蓋体を外した状態での平面図である。It is the top view in the state which removed the cover body, showing the other form of embodiment of the package for semiconductor element accommodation of this invention, and a semiconductor device. 図4の半導体素子収納用パッケージおよび半導体装置のA−A’線での断面図である。FIG. 5 is a cross-sectional view taken along line A-A ′ of the semiconductor element storage package and the semiconductor device of FIG. 4. 図4の半導体素子収納用パッケージおよび半導体装置のB−B’線での断面図である。FIG. 5 is a cross-sectional view taken along line B-B ′ of the semiconductor element storage package and the semiconductor device of FIG. 4. 従来の半導体素子収納用パッケージおよび半導体装置の蓋体を外した状態での平面図である。It is a top view in the state where a conventional semiconductor element storage package and a lid of a semiconductor device were removed. 図7の半導体素子収納用パッケージおよび半導体装置のA−A’線での断面図である。FIG. 8 is a cross-sectional view taken along line A-A ′ of the semiconductor element storage package and the semiconductor device of FIG. 7.

符号の説明Explanation of symbols

1・・・・・・・金属基板
1a・・・・・・搭載部
1b・・・・・・貫通孔
2・・・・・・・封止材
3・・・・・・・リード端子
6・・・・・・・蓋体
7・・・・・・・突起部
S・・・・・・・半導体素子
1 .... Metal substrate 1a ... Mounting part 1b ... Through hole 2 .... Encapsulant 3 .... Lead terminal 6 ··················································· Semiconductor element

Claims (4)

上面の中央部に半導体素子の搭載部を有するとともに該搭載部の周辺に前記上面から下面にかけて形成された貫通孔を有する金属基板と、前記貫通孔に挿通され、少なくとも下端部が前記貫通孔から突出するように封止材を介して固定されるとともに上端部が前記半導体素子の電極に電気的に接続されるリード端子とを具備している半導体素子収納用パッケージにおいて、前記金属基板の上面で、前記貫通孔の近傍に、接地電位に接続された上、前記リード端子の上端部と並んで立設される導電性の突起部を形成したことを特徴とする半導体素子収納用パッケージ。 A metal substrate having a semiconductor element mounting portion in the center of the upper surface and having a through hole formed in the periphery of the mounting portion from the upper surface to the lower surface, and inserted through the through hole, at least a lower end portion extending from the through hole In a package for housing a semiconductor element, wherein the upper end of the package is fixed through a sealing material so as to protrude, and the lead terminal is electrically connected to the electrode of the semiconductor element. A package for housing a semiconductor element, characterized in that, in the vicinity of the through hole, a conductive protrusion is formed which is connected to the ground potential and is erected in parallel with the upper end of the lead terminal. 前記突起部を平面視して円弧状としたことを特徴とする請求項1記載の半導体素子収納用パッケージ。 The package for housing a semiconductor element according to claim 1, wherein the projecting portion has an arc shape when viewed from above. 前記突起部を前記リード端子の周囲に全周にわたって取り囲むように形成したことを特徴とする請求項1または請求項2記載の半導体素子収納用パッケージ。 3. The package for housing a semiconductor element according to claim 1, wherein the protruding portion is formed around the lead terminal so as to surround the entire circumference. 請求項1乃至請求項3のいずれかに記載の半導体素子収納用パッケージと、前記搭載部に搭載するとともに電極を前記リード端子に電気的に接続した半導体素子と、前記半導体素子を覆う封止部材とを具備していることを特徴とする半導体装置。 A package for housing a semiconductor element according to any one of claims 1 to 3, a semiconductor element mounted on the mounting portion and having an electrode electrically connected to the lead terminal, and a sealing member covering the semiconductor element And a semiconductor device.
JP2004373182A 2004-12-24 2004-12-24 Semiconductor element housing package and semiconductor device Pending JP2006179775A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5368588B2 (en) * 2010-01-27 2013-12-18 三菱電機株式会社 Semiconductor laser module
JP2016532306A (en) * 2013-09-05 2016-10-13 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツングOsram Opto Semiconductors GmbH Optoelectronic component, optoelectronic device, and manufacturing method of optoelectronic device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5368588B2 (en) * 2010-01-27 2013-12-18 三菱電機株式会社 Semiconductor laser module
JP2016532306A (en) * 2013-09-05 2016-10-13 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツングOsram Opto Semiconductors GmbH Optoelectronic component, optoelectronic device, and manufacturing method of optoelectronic device

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