JP2006151398A - Packing tape carrier for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a packaging tape carrier for a semiconductor integrated circuit, which prevents a solder ball terminal from being damaged without increasing a chip size. <P>SOLUTION: A tape 35 is made of a polystyrene resin, and is provided with sprocket holes 11 along the side edge of the tape 35. The tape 35 is also provided with square openings 36 formed at constant intervals, and box-like embossed parts 31, in which an IC chip 2a is stored, are continuously formed respectively at the lower end edges of the openings 36. After the IC chip 2a is stored in the embossed part 31, the upper face of the tape 35 is sealed with a sealing film 13. The embossed part 31 has side faces each sloping inward at a certain angle toward the bottom face of the embossed part 31, and a side shift preventing wall 33 limiting a shift of the IC chip 2a is provided on the side walls of the embossed part 31. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit packaging tape carrier suitable for use in packing and transporting an IC (semiconductor integrated circuit) chip mainly using a microminiature semiconductor integrated circuit package.

  FIG. 7 is a plan view, a side view, and a back view showing the structure of an IC chip using a micro semiconductor integrated circuit package (hereinafter referred to as a CSP (Chip Size Package) package). In this figure, reference numeral 2 denotes an IC chip having a square top surface, and position marks 3 are attached to corners of the top surface. The bottom surface is sealed with a sealing resin 6, and nine solder ball terminals arranged in a square shape are attached to the sealing resin 6.

  FIG. 8 is a plan view and a side view showing a configuration of an embossed tape carrier 9 conventionally used for packing and transporting such an IC chip. The embossed tape carrier 9 has a belt-like shape, and sprocket holes 11 are formed along the side edges, and an embossed portion 14 that houses the IC chips 2 at regular intervals is formed on the back surface. And after an IC chip is accommodated in each embossed part 14, the upper surface is sealed with a sealing film 13. The embossed tape carrier 9 is manufactured by integral molding with polystyrene resin, and the sealing film 13 is attached by thermocompression bonding.

FIG. 9 is a view showing a state in which the embossed tape carrier 9 is wound around the tape reel 17. In the printed circuit board manufacturing process, the tape reel 17 is set in a mounting machine for mounting the IC chip 2 on the printed circuit board. When the mounting machine is operated, the IC chip is automatically mounted on the printed board. The embossed tape carrier 9 is pulled out by rotation of the sprocket gear of the mounting machine engaged with the sprocket hole 11.
Patent Documents 1 to 3 are known as documents related to this type of conventional tape carrier.
JP 2000-33969 A JP 2002-68288 A JP 2003-26229 A

  Incidentally, the embossed tape carrier 9 shown in FIGS. 8 and 9 has the following problems. That is, the IC chip 2 vibrates inside the embossed portion 14 as shown by an arrow in FIG. For this reason, the solder ball terminal 5 of the IC chip 2 is damaged by contact with the bottom surface of the embossed portion 14 and friction, and the height is not uniform as shown in FIG. When the IC chip 2 is soldered to the printed circuit board with the solder ball terminal damaged by friction, contact failure occurs because the height of the solder ball terminal is not uniform as shown in FIG.

  In order to solve the above-described problems, a holding shelf type embossed tape carrier has been developed. FIG. 13A is a plan view of a holding shelf type embossed tape carrier, FIG. 13B is a side view, and FIG. 13C is a view showing the IC chip 2 inserted into the embossed portion 22. As shown in these drawings, the holding shelf type embossed tape carrier 21 is provided with an IC chip holding shelf 26 along the inner wall of the embossed portion 22, and the peripheral portion of the IC chip 2 is held by the holding shelf 26. As a result, the solder ball terminal 5 does not contact the bottom surface of the embossed portion 22, and as a result, damage to the solder ball terminal 5 can be prevented.

  However, in order to hold the IC chip 2 by the holding shelf 26, a space of a certain width around the IC chip 2, specifically, from the center of the solder ball terminal 5 to the outer peripheral line as shown in FIG. The distance SP must be at least 0.5 mm. When this space is taken in the peripheral portion, the pitch interval of the solder ball terminals 5 is determined to be 0.5 mm. Therefore, as shown in the figure, in the case of the IC chip 2 having nine terminals, Both lateral dimensions are 2 mm. Thus, when the holding shelf 26 is provided, the vertical and horizontal sizes increase, and there is a problem that the chip unit price increases due to the increase in size.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a packaging tape carrier for a semiconductor integrated circuit that can prevent damage to a solder ball terminal without increasing the chip size.

  SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. According to the first aspect of the present invention, openings are formed at predetermined intervals in a tape member having a predetermined length, and an IC chip is accommodated in the openings. In the packaging tape carrier for a semiconductor integrated circuit in which the box-shaped storage unit is continuously provided, the side surface of the storage unit is inclined at a certain angle inward toward the bottom surface of the storage unit. A packaging tape carrier for a semiconductor integrated circuit, wherein a lateral misalignment prevention wall for restricting movement of an IC chip is provided.

  According to a second aspect of the present invention, in the packaging tape carrier for a semiconductor integrated circuit according to the first aspect, the lateral blur prevention wall has a triangular prism shape, and the height of the IC chip accommodated in the accommodating portion is It is larger than the length between the upper surface and the opening.

  According to the present invention, it is possible to prevent damage to the solder ball terminal due to friction during transportation of the IC chip. In addition, there is no particular limitation on the peripheral space width of the IC chip, which provides an advantage that the size of the IC chip does not need to be increased in order to prevent damage to the solder ball terminals. Further, since it is not necessary to increase the size of the IC chip, there is an advantage that the cost of the IC chip does not increase.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view and a side view showing a configuration of an embossed tape carrier 30 according to an embodiment of the present invention. In this figure, the code | symbol 35 is a tape by a polystyrene resin, and the sprocket hole 11 is formed along the side edge. The tape 35 has square openings 36 formed at regular intervals, and a box-like embossed portion (storage portion) 31 in which the IC chip 2a is stored is connected to the lower end edge of the opening 36. ing. And after IC chip 2a is accommodated in each embossed part 31, the upper surface is sealed with sealing film 13. The embossed tape carrier 31 is manufactured by integral molding with polystyrene resin, and the sealing film 13 is attached by thermocompression bonding.

In the above configuration, the configuration other than the embossed portion 31 is the same as that of the conventional embossed tape carrier, and the embossed portion 31 will be described in detail below.
FIG. 2 is a side view showing the configuration of the embossed portion 31. As shown in this figure, the embossed portion 31 has four side surfaces 31a inclined at a certain angle inward, and the size of the bottom surface 31b is larger than the opening. It is getting smaller. As a result, when the IC chip 2a is inserted into the embossed portion 31, the peripheral portion of the lower surface of the IC chip 2a abuts on the side surface 31a as shown in the figure (see symbol A), whereby the solder ball terminal 5 is It is possible to prevent contact with the bottom surface 31 b of the 31.

FIG. 3 is a diagram for explaining an angle α formed by the side surface 31 a of the embossed portion 31 and the opening 36. The IC chip 2a used in this embodiment has a length SP from the center of the solder ball terminal 5 to the outer peripheral line = 0.3 mm. Other dimensions are the same as the conventional one (FIG. 14). The diameter D of the solder ball terminal 5 is 0.3 mm, and the height b of the solder ball terminal 5 is 0.24 mm. The length from the outer peripheral portion of the solder ball terminal 5 to the outer peripheral line of the chip is a = 0.15 mm. As shown in the figure, if the side surface 31a is aligned with a straight line connecting the outer peripheral edge of the back surface of the IC chip 2a and the intersection P of the rightmost tangent and the lowest tangent of the solder ball terminal 5, the solder ball Since the terminal 5 does not contact the side surface 31a, the angle α is determined so that the straight line and the side surface 31a coincide with each other.
α = arc (tanb / a)
It is calculated by the following formula. In this equation, a = 0.15
b = 0.24
Substituting
It is calculated as α = 57.9 degrees.

  However, if the side surface 31a is simply inclined, the IC chip 2a is inclined and the solder ball terminal 5 comes into contact with the bottom surface 31b of the embossed portion 31 due to vibration during movement, as shown in FIG. Therefore, in this embodiment, as shown in FIGS. 1 and 5, in addition to the inclined structure of the side surface 31a described above, a lateral displacement prevention wall 33 is further formed on each inner surface of the four side surfaces 31a. The lateral displacement prevention wall 33 has a triangular prism shape, the vertical surface is formed with a slight gap from the side surface of the IC chip 2a, the lateral surface is formed in parallel with the opening 36, and the oblique surface is the embossed portion 31. It corresponds to the side surface 31a. Further, the height H is formed to be longer than the length c between the upper surface of the IC chip 2 a and the opening 36 of the embossed portion 31. By forming the height H to such a length, even if the IC chip 2a is lifted up to the opening 36 by vibration, it is possible to prevent the IC chip 2a from shifting laterally beyond the lateral displacement preventing wall 33.

FIG. 6 is a plan view, a side view, and a back view showing the configuration of the IC chip 2a used in this embodiment. As shown in this figure, according to this embodiment, the length SP from the center of the solder ball terminal 5 of the IC chip 2a to the outer peripheral line can be set to 0.3 mm. As a result, the outer dimensions of the IC chip 2a The
1.6mm x 1.6mm
It can be. Thereby, the area of the IC chip 2a described above can be reduced by 36% compared to the conventional IC chip 2 of 2.0 mm × 2.0 mm. Further, by reducing the chip size, it is possible to improve the yield of non-defective products in the IC manufacturing process and reduce the manufacturing cost.

  The present invention is mainly used in an IC chip manufacturing factory using a CSP package.

It is the top view and side view which show the structure of the embossed tape carrier by one Embodiment of this invention. It is a figure which shows the structure of the embossing part which inclined the side surface. It is a figure for demonstrating the angle (alpha) which the side surface of the embossing part in FIG. 2 and an opening surface make. It is a figure for demonstrating the problem of the embossing part shown in FIG. FIG. 3 is a side sectional view of the embossed portion 31 shown in FIG. 1, further improving the embossed portion shown in FIG. 2. It is the top view, side view, and back view which show the structure of the IC chip accommodated in the embossed tape carrier shown in FIG. It is the top view, side view, and back view which show the structure of the IC chip accommodated in the conventional embossed tape carrier. It is the top view and side view which show the structure of the conventional embossed tape carrier. It is a figure which shows the state by which the embossed tape carrier shown in FIG. 8 was wound around the tape reel. It is a figure for demonstrating the problem of the conventional embossed tape carrier. It is a figure for demonstrating the problem of the conventional embossed tape carrier. It is a figure for demonstrating the problem of the conventional embossed tape carrier. FIG. 9 is a plan view, a side view, and a view showing the IC chip 2 inserted into the embossed portion 22 of a holding shelf type embossed tape carrier improved from the embossed tape carrier shown in FIG. 8. It is the top view and back view which show the dimension of the IC chip accommodated in the conventional embossed tape carrier.

Explanation of symbols

2a ... IC chip, 5 ... solder ball terminal, 11 ... sprocket hole, 30 ... embossed tape carrier, 31 ... embossed portion, 31a ... side surface, 31b ... bottom surface, 33 ... lateral misalignment prevention wall, 35 tape, 36 ... opening,

Claims (2)

In a packing tape carrier for a semiconductor integrated circuit in which openings are formed at predetermined intervals in a tape member of a predetermined length, and a box-shaped storage portion in which an IC chip is stored in the opening is continuously provided.
The side surface of the storage portion is formed so as to be inclined at a certain angle inward toward the bottom surface of the storage portion,
A packaging tape carrier for a semiconductor integrated circuit, characterized in that a lateral displacement prevention wall for restricting movement of the IC chip is provided on the side surface.   2. The horizontal blur preventing member has a triangular prism shape, and a height thereof is larger than a length between an upper surface of an IC chip accommodated in the accommodating portion and the opening portion. Packing tape carrier for semiconductor integrated circuits.

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