JP2006121171A - Clock supplying device with frequency correction function - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock supplying device with a frequency correction function capable of correcting a secular change characteristic of a clock frequency from a VCO and realizing a highly accurate self-running clock even when a reference clock is interrupted. <P>SOLUTION: When the reference clock can be acquired, a CPU 106 predictively calculates phase error information due to the secular change characteristic of the clock frequency from the VCO 104 by each period informed from a time count means 11 in advance on the basis of the phase error information outputted from a phase comparator 2, and stores a control voltage for correcting its phase error to a self-running DA setting memory 109. When the reference clock is interrupted, the CPU 106 reads the control voltage for correcting corresponding phase error information to each period informed by the time count means 110 from the self-running DA setting memory 109 and sets the phase error information to a DA converter 105 in place of using the phase error information from the phase comparator 102 without referring to the phase error information being an output of the phase comparator 102 so as to correct the secular change characteristic of the clock frequency from the VCO 104 thereby being capable of realizing the highly accurate self-running clock. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a clock supply device with a frequency correction function used in a communication device that requires a highly accurate oscillation signal, that is, a clock.

  Conventionally, in a clock supply device of a wireless communication device that requires a high-precision clock, an output oscillation signal of an oscillator provided, that is, an output clock is used as a reference oscillation signal that is extracted from a network line, that is, a host device of the network. Use with synchronized phases. Therefore, a phase locked loop (PLL) capable of frequency correction is used. The PLL includes a reference clock, a voltage-controlled oscillator (VCO) that can correct the oscillation frequency with a control voltage value, a phase comparator that detects a phase error between the output clock and a dependent clock, and a detected phase error. A control voltage value for correcting the phase error is calculated based on the information, and the control means (CPU) is configured to set the calculated value in the VCO. Since the VCO can correct the oscillation frequency with the control voltage value, the phase difference from the reference clock can be corrected by adjusting the control voltage value. That is, if the phase of the VCO is advanced, the oscillation frequency is decreased, and if it is delayed, the oscillation frequency is increased. By this correction, the oscillation frequency error between the reference clock and the VCO finally falls within a certain range, that is, is in a synchronized state.

  The control voltage value for correcting this phase error information is calculated by computer simulation in consideration of the convergence time required until the synchronization state, the sensitivity of the VCO, the stability of the synchronization state, etc., and further adjusted by actual measurement. To be determined.

  In some cases, the PLL adjusts and acquires a control voltage value corresponding to a predetermined oscillation frequency in advance when the power supply of the VCO is turned on, and stores the value in a memory. By setting the initial control voltage value at the time of rising, the phase of the subordinate clock and the phase of the reference clock can be synchronized at high speed.

  By the way, in the above-described conventional method, when the network is disconnected, the reference clock supply is cut off due to the failure of the reference clock extraction processing unit, or the deterioration of the SN ratio or accuracy of the reference clock signal due to the mixing of noise. When the clock is off, the clock supply device must be self-supporting to generate a high-accuracy free-running clock using the dependent clock. In general, the initial control voltage value is used for this free-running clock. However, it is difficult to continue the operation with the accuracy of the fixed control voltage value. That is, the oscillation frequency of the free-running clock fluctuates even if the control voltage value is fixed. The main factors that fluctuate the oscillation frequency of the free-running clock are aging characteristics and temperature characteristics of the oscillation frequency of the VCO. However, since a clock supply device for a communication device that requires a high-accuracy clock is built in the thermostatic chamber, the temperature characteristics have no problem in accuracy.

However, since the aging characteristics depend on time, if the supply of the reference clock is cut off for a long period of time, there arises a problem that the accuracy necessary for realizing the required performance cannot be maintained.
As a solution to the above problem, a clock supply device with a holdover function has been proposed (for example, Patent Document 1).
This conventional clock supply device with a holdover function includes a plurality of reference clocks, which are used by switching them. The phases of the reference clock and the subordinate clock when each of them is used are compared, and phase error information is stored and a control voltage value of the VCO is calculated based on the comparison result. At the same time, the reference clock with the best quality is detected, and the phase information when the reference clock with the best quality is used is the phase information during the free-running operation of the dependent clock when all the reference clocks are disconnected. The control voltage value of the VCO is calculated using the error information. In this way, by calculating and setting the control voltage value of the voltage controlled oscillator from the phase error information when using the reference clock with the best quality, a highly accurate free-running clock even when the reference clock is disconnected Can be obtained.
JP 2002-232407 (FIG. 1) Co-authored by Kozo Ichida and Fuji City Yoshimoto, "Spline functions and their applications", first edition, 8th edition, educational publication, August 8, 1990

  However, since the conventional clock supply device with a holdover function does not take into consideration information on the aging characteristics of the oscillation frequency of the VCO, there is a problem that an accuracy error due to the aging characteristics cannot be corrected. That is, when all the reference clocks are cut off, refer to the phase error information when using the reference clock with the best quality for the error due to the aging characteristics until the start of free-running operation of the VCO oscillation frequency. It is solved with. However, since the secular change characteristic of the oscillation frequency of the VCO changes with time, a phase error due to the secular change characteristic of the oscillation frequency occurs after the start of the free-running operation. In other words, the conventional clock supply device with a holdover function is controlled so as to eliminate error information due to aging characteristics from the start of the free-running operation to the start of the free-running operation. As long as the aging characteristic information does not match, a phase error occurs.

  Next, the problem of the conventional clock supply apparatus will be described with reference to FIG. FIG. 2A shows the aging characteristics of the oscillation frequency of the VCO. The horizontal axis is time, and the vertical axis is the amount of frequency fluctuation. At the start of operation, the target frequency is adjusted in advance. As shown in FIG. 2A, the oscillation frequency of the VCO monotonously increases with time. There may be a monotonous decrease. Since this characteristic is different for each VCO, it is necessary to obtain a correction value individually.

  FIG. 2B shows the secular change characteristic of the dependent clock frequency of the VCO when the conventional control voltage value fixed type clock supply apparatus is used. Since the initial control voltage value of the VCO, that is, the control voltage value corresponding to a predetermined frequency is set in advance at the time when the reference clock indicated by the broken line is cut off, the frequency from the start of operation to the time when the reference clock is cut off An error corresponding to the secular change characteristic occurs. Thereafter, a phase error according to the aging characteristics of the VCO frequency occurs.

  FIG. 2C shows the aging characteristics of the VCO dependent clock frequency when a conventional clock supply device with a holdover function is used. At the time when the reference clock indicated by the broken line is cut, a control voltage value corresponding to the frequency of the dependent clock of the VCO synchronized with the reference clock is set. Therefore, a frequency error due to aging characteristics does not occur. However, thereafter, control is performed so as to correct the aging characteristics before the time when the reference clock is cut off, so that a phase error due to the aging characteristics of the frequency occurs.

  The present invention has been made to solve such a conventional problem, and the phase error information of the reference clock and the dependent clock of the VCO when the reference clock is extracted from the host device of the network is stored in the storage means. The trend of the aging characteristics of the clock frequency of the VCO is calculated from the stored phase error information, and the aging characteristics information at the time of setting the future control voltage value notified by the time measuring means is predicted. By calculating the control voltage value for correcting the phase error information based on the predicted aging characteristics, the aging characteristics of the VCO are corrected even when the reference clock is cut off, thereby realizing a highly accurate clock. As a result, an object of the present invention is to provide an excellent clock supply device with a frequency correction function capable of obtaining the characteristics shown in FIG.

  In order to solve the above-mentioned conventional problems, the present invention provides a reference oscillation signal monitoring means for detecting the presence or absence or abnormality of a reference oscillation signal extracted from a network line, and a voltage controlled oscillator capable of adjusting the oscillation frequency with a control voltage value Phase comparison means for comparing the phase of the oscillation signal output from the voltage controlled oscillator and the reference oscillation signal to detect phase error information, control means for setting the control voltage value of the voltage controlled oscillator, and time measurement And a storage means for storing a control voltage value for correcting the phase error based on the phase error information based on the aging characteristics of the frequency of the oscillation signal of the voltage controlled oscillator. And when the reference oscillation signal monitoring means does not detect an abnormality or disappearance of the reference oscillation signal, the control means is based on the phase error information notified from the phase comparison means. When the control voltage value of the voltage controlled oscillator is set so as to correct the phase error, and when the reference oscillation signal monitoring means detects an abnormality or disappearance of the reference oscillation signal, the control means is in a specific cycle notified by the time measuring means. The control voltage value stored in the storage means is set in the voltage controlled oscillator.

  Further, the storage means not only stores the control voltage value for correcting the phase error, but also stores an initial control voltage value set in advance so that the frequency of the oscillation signal of the voltage controlled oscillator becomes a specified reference frequency, When the reference oscillation signal monitoring means does not detect abnormality or disappearance of the reference oscillation signal, the error between the control voltage value of the oscillation signal of the voltage controlled oscillator and the initial control voltage value or the control voltage value for correcting the phase error is a constant value. When the above is true, the control voltage value of the oscillation signal of the voltage controlled oscillator is used as the initial control voltage value.

  Further, the control means stores in the storage means the phase error information based on the aging characteristics of the frequency of the oscillation signal of the voltage controlled oscillator, and when the reference oscillation signal monitoring means detects an abnormality or disappearance of the reference oscillation signal, the timing means When notified of the cycle for setting the control voltage value, the control voltage value for correcting the phase error is calculated based on the stored phase error information, and the control voltage value is set in the voltage controlled oscillator. Uses a characteristic configuration.

  Further, the control means extracts the phase error information notified from the phase comparison means when the reference oscillation signal monitoring means does not detect an abnormality or disappearance of the reference oscillation signal, and extracts the phase error information in the period notified by the time measuring means to the storage means. The phase error information by the aging characteristics corresponding to the period for setting the future control voltage value notified by the time measuring means is calculated by storing and determining the tendency of the phase error information by the aging characteristics from the stored phase error information. When the control voltage value for predicting and correcting the phase error information due to the predicted aging characteristic is calculated and stored, and the period for setting the control voltage value is notified from the time measuring means, the corresponding control voltage value Is set as a voltage controlled oscillator.

  The phase error information notified from the phase comparison means stored in the storage means is phase error information obtained by averaging the phase error information notified from the phase comparison means.

  With the above configuration, the phase error information between the reference clock and the VCO dependent clock when the reference clock is extracted from the host device of the network is stored in the storage means, and the clock frequency of the VCO is calculated from the stored phase error information. Determine trends in phase error information due to aging characteristics. Further, if the phase error information is averaged and stored by performing a moving average process or an integral calculation process, noise can be removed, so that the accuracy of the error information can be improved. Then, the period for setting the control voltage value for correcting the phase error due to the aging characteristics of the clock frequency of the VCO is set in the time measuring means. Predicts aging characteristics information when setting future control voltage values from the determined trend of aging characteristics and control voltage value setting cycle, and corrects phase error information due to the predicted aging characteristics By calculating the control voltage value and setting the control means to the VCO, even if the reference clock is cut off, it is possible to correct the phase error information due to the aging characteristics of the VCO and realize a highly accurate clock.

  According to the clock supply device with a frequency correction function of the present invention, even if the reference clock is cut off, it is possible to predict and correct the phase error information due to the aging characteristics of the oscillation frequency of the VCO. Accordingly, even when a VCO self-running operation for a long period of time is required, the phase error can be automatically corrected, so that maintenance-free operation can be realized.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

(Embodiment 1)
The configuration and operation of the clock supply device with a frequency correction function according to the first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 shows the overall configuration of a clock supply device with a frequency correction function according to the first embodiment of the present invention. In FIG. 1, reference numeral 101 is a reference clock monitoring means for monitoring a reference oscillation signal, that is, a reference clock extracted from a host device on the network and detecting the presence / absence and abnormality, and 104 is a clock supply apparatus with a frequency correction function of the present invention. A VCO serving as a clock source to output, 103 is a frequency divider 103 that divides the output clock of the VCO 104, and 102 is a phase comparison that detects a phase error between the output clock of the frequency-divided VCO 104 and the reference clock. , 105 is a DA converter that converts the control voltage value of the VCO 104 from a digital signal to an analog signal, and 108 is set to the DA converter 105 during the initial operation of the VCO 104, so that the output clock of the VCO 104 has a specific frequency in advance. Initial self-running that maintains the initial control voltage value of the VCO 104 adjusted to The A setting memory 109 is a self-holding unit for holding the control voltage value of the VCO 104 periodically set in the DA converter 105 in order to maintain the accuracy of the free-running frequency of the clock output from the VCO 104 when the reference clock is cut off. The running DA setting memory 110 is a time measuring means for notifying the period for acquiring the phase error information output from the phase comparator 102 and the period for setting the control voltage value stored in the free running DA setting memory 109 in the DA converter 105. , 106 calculates the control voltage value stored in the free-running DA setting memory 109 from the control of the entire clock supply device with frequency correction function according to the first embodiment of the present invention and the phase error information, and free-running DA Control voltage stored in the setting memory 109 and calculated to the DA converter 105 at a period notified from the time measuring means 110 during the self-running operation of the VCO 104 Setting the CPU, 107 is a WORK memory for CPU106 is used in arithmetic processes and control processes.

  The operation of the clock supply apparatus with a frequency correction function according to the first embodiment of the present invention configured as described above will be described in detail. When the clock supply device with a frequency correction function of the present invention starts operation, first, in order to adjust the output clock of the VCO 104 to a specific frequency, the CPU 106 DA converts the initial control voltage value stored in the initial free-running DA setting memory. Set to the device 105. The VCO 104 outputs a clock at a frequency corresponding to the set control voltage value. Hereinafter, a state where the reference clock extracted from the host device on the network is detected by the reference clock monitoring unit 101 (subordinate mode) and a state where the reference clock is not detected (self-running mode) will be described in order.

  First, in the subordinate mode, the clock supply device with a frequency correction function of the present invention operates as a PLL. That is, the output clock of the VCO 104 is frequency-divided by the frequency divider 103 and then operated as a subordinate clock whose phase is compared with the reference clock by the phase comparator 102 and the clock frequency is adjusted to synchronize with the reference clock. First, the phase error information of the dependent clock and the reference clock is extracted by the phase comparator 102 at the period notified by the time measuring means 110, and the control voltage value for correcting the phase error information is calculated and set in the DA converter 105. Is done. Then, the phase error between the reference clock and the subordinate clock is eliminated by adjusting the output clock frequency of the VCO 104. That is, since the phase error information is obtained by integrating the frequency error for a fixed time, the frequency error information can be obtained from the phase error information extracted at a fixed period, that is, differential information of the phase error. A control voltage value for correcting the frequency error information corresponding to the phase error information is set in the DA converter 105 to correct the frequency error. When the frequency error information is eliminated, the phase error is eliminated by setting a control voltage value for correcting the extracted phase error information in the DA converter 105, and the reference clock and the subordinate clock are synchronized.

  In this subordinate mode, the CPU 106 stores phase error information in the WORK memory 107 over a long period, and determines the tendency of the aging characteristics of the clock frequency of the VCO 104. Then, the control voltage value set in the DA converter 105 is calculated and stored in the free-running DA setting memory 109 at the period notified by the time measuring means 110 for use during the free-running mode operation. In this embodiment, since it is generally difficult to realize a calculation means for calculating the control voltage value for correcting the phase error information, the control voltage value for the phase error information is calculated in advance, and the calculation result is stored in the WORK memory 107. This is realized by the method of storing in the above nonvolatile memory. When the CPU 106 calculates the control voltage value of the VCO 104 from the phase error information, the CPU 106 refers to the calculation result information stored in the nonvolatile memory.

  Next, a method for calculating the control voltage value stored in the free-running DA setting memory 109 by the CPU 106 will be described with reference to FIG. The CPU 106 uses the phase error information stored in the WORK memory 107 to calculate a function (spline function F (X)) that approximates the tendency of the phase error information corresponding to the aging characteristics of the clock frequency of the VCO 104. In this embodiment, this function is calculated using a cubic spline interpolation method. The cubic spline interpolation method is disclosed in detail in Non-Patent Document 1, for example.

  In FIG. 3A, P1, P2, and P3 are phase error information sampled at periods Ai, Aj, and Ak notified from the time measuring unit 110, respectively. The latest phase error information is P3. Hereinafter, B0 to BN + 1 are future sampling periods notified from the time measuring means 10, and P3 to PN + 1 are phase error information sampled corresponding to each sampling period B0 to BN + 1. The CPU 6 calculates the spline function Fj (X) in the sections Aj to Ak using the phase error information P1, P2, and P3. From the calculated spline function Fj (X), phase error information (P4 to PN, respectively) of the sections B0 to BN is calculated, and the control voltage value to be corrected is read from the nonvolatile memory on the WORK memory 107. Then, the control voltage value stored in the free-running DA memory 109 is updated. When the next period is notified from the time measuring means 110, the latest phase error information becomes P4. Therefore, the CPU 106 uses the phase error information P2, P3, and P4 to calculate the spline function Fk (X) from the section Ak to B0. calculate. Thereafter, similarly, phase error information (P5 to PN + 1, respectively) for the sections B1 to BN + 1 is calculated, and the control voltage value stored in the free-running DA memory 109 is updated.

  In this method, high-accuracy phase error information is required to accurately determine the tendency of the phase error information due to the aging characteristics of the clock frequency of the VCO 106. Since the phase error information output from the phase comparator 102 fluctuates due to noise or the like, the CPU 106 performs an averaging process when it is necessary to acquire highly accurate phase error information. A process of acquiring phase error information of the CPU 106 when performing the averaging process will be described with reference to FIG. The CPU 106 controls the cycle of the time measuring means 110 and switches between two types of cycles, T1 and T2, as shown in FIG. T1 is a period of the time measuring means 110, and T2 is a sampling period of the phase error information necessary for averaging the phase error information necessary for calculating the voltage value set in the DA conversion circuit 105. The CPU 106 can set the number of times of averaging for each acquisition period of the phase error information by switching between the periods T1 and T2 of the time measuring means 110. For example, as shown in FIG. 2 (A), when the operation of the VCO 104 is started, the amount of change with respect to the unit time of the frequency aging characteristic is large, so the number of averaging is reduced, and the number of averaging is increased when sufficient time has passed. This improves the accuracy of the phase error information.

  By the way, even in the subordinate mode, the synchronization state may be lost due to noise or the like. This can be detected by the CPU 106 detecting a state in which the phase error information between the dependent clock and the reference clock is equal to or greater than a preset threshold value. In this case, if the predicted phase error can be calculated in advance, the operation is the same as the self-running mode described below. If not, the CPU 106 can set the initial control voltage value stored in the initial free-running DA setting memory 109 to DA Set in the converter 105.

  Next, the operation in the free-running mode will be described. In the free-running mode, the control voltage value stored in the free-running DA setting memory 109 is used to correct the phase error due to the aging characteristics of the clock frequency of the VCO 104. As a result, even when the self-running operation of the VCO 104 is required for a long time, the phase error can be automatically corrected, so that a highly accurate free-running clock can be realized. When the CPU 106 is notified by the reference clock monitoring means 101 that the reference clock has been cut off, the CPU 106 stops the operation of the phase comparator 102. Therefore, the phase error information of the phase comparator 102 is not used until the reference clock monitoring unit 101 detects the reference clock next time. Instead, the free-running frequency of the VCO 104 is controlled using the control voltage value stored in the free-running DA setting memory 109.

  Next, a method in which the CPU 106 corrects the phase error due to the aging characteristics of the clock frequency of the VCO 104 using the control voltage value stored in the free-running DA setting memory 109 will be described with reference to FIG. In this example, it is assumed that the reference clock is cut off immediately after the period Ak in FIG. When the clock means 110 notifies the DA converter 5 of the cycle for setting the control voltage value (B0 in FIG. 3A in this example), the CPU 106 receives the phase error information corresponding to that cycle (in this example, FIG. 3). The control voltage value for P4) is read from the free-running DA setting memory 109 and set in the DA converter 105. Then, a control voltage value is determined for the next read cycle (B1 in FIG. 3A in this example) and the phase error information corresponding to the cycle (P5 in FIG. 3A in this example). When the next set cycle (B 1) is notified, a predetermined control voltage value is read from the free-running DA setting memory 109 and the value is set in the DA converter 105. In this way, since the free-running frequency of the VCO 104 is corrected by the control voltage value calculated in advance, the VCO 104 can be operated at a highly accurate free-running frequency even in the free-running mode.

  In this embodiment, in order to accurately determine the tendency of the aging characteristics of the clock frequency, phase error information between the reference clock and the dependent clock in the dependent mode is detected, and a cubic spline function is calculated from the phase error information. However, it can be realized by using other spline functions.

  In this embodiment, the control voltage value for correcting the phase error information is stored in the free-running DA setting memory 109. However, instead of the control voltage value, the phase error information is stored in the free-running DA setting memory 109. Also realized when the CPU 106 sets the control voltage value in the DA converter 105 by reading the phase error information from the free-running DA setting memory 109 and calculating the corresponding control voltage value and setting it in the free-running DA setting memory 109 Is possible.

  Further, in this embodiment, three memories, ie, the WORK memory 107, the initial free-running DA setting memory 108, and the free-running DA setting memory 109 are used. It can be realized as a configuration in which the information stored in each memory is specified on the memory map of the WORK memory 107.

  As described above, according to this embodiment, it is possible to predict and correct the phase error due to the aging characteristics of the oscillation frequency of the VCO 104 even if the reference clock is cut off. Therefore, even when the self-running operation of the VCO 104 is required for a long time, the phase error can be automatically corrected.

  The clock supply device with a frequency correction function according to the present invention predicts and corrects the phase error due to the aging characteristics of the oscillation frequency of the VCO even when the reference clock supplied from the host device on the network is cut off, Even when the VCO needs to run for a long time, the phase error can be automatically corrected.

  As described above, since a highly accurate VCO free-running clock can be generated even if the reference clock is cut off, it is mounted on a cellular phone base station, a communication line switching station, etc., and supplied from a host device on the network. This is useful as a clock supply device with a frequency correction function that requires a highly accurate clock even when the reference clock is cut off.

1 is an overall configuration diagram of a clock supply device with a frequency correction function according to a first embodiment of the present invention. The figure which shows the subject of the conventional clock supply apparatus The figure which shows the method of calculating the phase error information of the clock supply apparatus with a frequency correction function concerning 1st embodiment of this invention.

Explanation of symbols

101 Reference clock monitoring means 102 Phase comparator 103 Divider 104 VCO
105 DA converter 106 CPU
107 memory for WORK 108 initial free running DA setting memory 109 free running DA setting memory 110 clocking means

Claims (5)

A reference oscillation signal monitoring means for detecting the presence or absence of a reference oscillation signal extracted from a network line; and
A voltage-controlled oscillator whose oscillation frequency can be adjusted by the control voltage value;
Phase comparison means for performing phase comparison between the oscillation signal output from the voltage controlled oscillator and the reference oscillation signal and detecting phase error information thereof;
Control means for setting a control voltage value of the voltage controlled oscillator;
A time measuring means for detecting a specific cycle that can be changed by measuring the time;
Storage means for storing a control voltage value for correcting the phase error based on the phase error information based on the aging characteristics of the frequency of the oscillation signal of the voltage controlled oscillator,
When the reference oscillation signal monitoring unit does not detect abnormality or disappearance of the reference oscillation signal, the control unit corrects the phase error based on the phase error information notified from the phase comparison unit. Set the control voltage value of the controlled oscillator,
When the reference oscillation signal monitoring unit detects an abnormality or disappearance of the reference oscillation signal, the control unit sets the control voltage value stored in the storage unit to the voltage at a specific period notified from the time measuring unit. A clock supply device with a frequency correction function, wherein the clock supply device is set to a controlled oscillator. The storage means not only stores the control voltage value for correcting the phase error, but also stores an initial control voltage value set in advance so that the frequency of the oscillation signal of the voltage controlled oscillator becomes a specified reference frequency. And
When the reference oscillation signal monitoring means does not detect abnormality or disappearance of the reference oscillation signal,
When the error between the control voltage value of the oscillation signal of the voltage controlled oscillator and the initial control voltage value or the control voltage value for correcting the phase error is a certain value or more,
2. The clock supply device with a frequency correction function according to claim 1, wherein a control voltage value of an oscillation signal of the voltage controlled oscillator is the initial control voltage value. The control means stores in the storage means phase error information due to the aging characteristics of the frequency of the oscillation signal of the voltage controlled oscillator, and when the reference oscillation signal monitoring means detects an abnormality or disappearance of the reference oscillation signal. ,
When the period for setting the control voltage value is notified by the time measuring means, a control voltage value for correcting the phase error is calculated based on the stored phase error information, and the control voltage value is calculated by the voltage control. 3. The clock supply device with a frequency correction function according to claim 2, wherein the clock supply device is set to an oscillator. The control means extracts the phase error information notified from the phase comparison means when the reference oscillation signal monitoring means does not detect abnormality or disappearance of the reference oscillation signal at a period notified by the time measuring means. Stored in the storage means,
By determining the tendency of the phase error information due to the aging characteristics from the stored phase error information, the phase error due to the aging characteristics corresponding to a period for setting the future control voltage value notified by the time measuring means Predicting information, calculating and storing the control voltage value for correcting phase error information due to the predicted aging characteristics,
3. The clock supply device with a frequency correction function according to claim 2, wherein when the period for setting the control voltage value is notified from the time measuring means, the corresponding control voltage value is set in the voltage controlled oscillator.   5. The phase error information notified from the phase comparison means stored in the storage means is phase error information obtained by averaging the phase error information notified from the phase comparison means. The clock supply apparatus with a frequency correction function as described.