JP4824801B2 - Digital phase synchronization circuit - Google Patents

Description

  The present invention relates to a digital phase locked loop (hereinafter abbreviated as DPLL) for realizing synchronization between base stations in a mobile communication system, and in particular, a GPS receiver synchronized with a GPS (G1oba1 Positioning System) satellite. The present invention relates to a DPLL using 1 PPS (Pulse Per Second) to be output as a reference signal.

  In mobile communication systems, high frequency stability is required from the viewpoint of effective use of frequencies. In particular, when OFDMA (Orthogonal Frequency Division Multiple Access) is used for the radio multiplexing scheme, the interval between subcarriers is narrow and high frequency stability is required as compared with other radio schemes. Also, frame synchronization accuracy between base stations is required to realize high-speed handover.

  In order to satisfy these requirements, a DPLL is mounted on the base station, and 1PPS output from a GPS receiver synchronized with a GPS satellite is used as a reference signal for the DPLL, and the synchronization clock obtained by the DPLL is used as a standard for the base station. Inter-base station synchronization is realized using the clock. However, if a GPS-related failure such as bad weather or a GPS receiver failure occurs, synchronization between base stations will not function. In order to avoid this, some systems have a function to hold a synchronization state between base stations for a certain period after a failure occurs by implementing a holdover function in the DPLL.

  In order to reduce the influence on temperature at the time of holdover, an OCXO (Oven Contro 11ed Osci 11ator) having a good temperature characteristic is mounted on the oscillator.

  The GPS receiver receives radio waves from GPS satellites through a GPS antenna. While synchronized with the GPS satellite, the GPS receiver outputs 1 PPS synchronized with the GPS satellite. The phase detector detects the phase difference between the divided clocks obtained by dividing the output clocks of 1PPS and OCXO by the divider. The digital filter is a low-pass filter that attenuates high-frequency components of the phase difference. The digital filter output passes through the holdover circuit, is converted into an analog signal by the D / A converter, and is input to the OCXO. The frequency of the OCXO output clock can be controlled in accordance with the input voltage. With the above operation, an OCXO output clock synchronized with a GPS satellite can be obtained.

  When a GPS-related failure occurs, the GPS receiver stops outputting 1 PPS. This is detected by reference signal disconnection detection and a reference signal disconnection signal is output. In response to this, the holdover circuit holds the previous digital filter output, converts it to an analog signal by the D / A converter, and inputs it to the OCXO. With the above operation, a stable OCXO output clock can be obtained while maintaining the state when synchronized with the GPS satellite during the holdover period.

However, the frequency stability of the OCXO during the holdover period depends on the characteristics of the OCXO. As an example, the characteristics of OCXO are introduced. The frequency temperature characteristic is a maximum of ± 10 × 10 ⁻⁹ (−10 ° C. to + 70 ° C.), and the secular change is a maximum of ± 2 × 10 ⁻⁹ (/ Day).

  Here, as a method of improving the frequency temperature characteristic during the holdover period, during the synchronization, the temperature around the VCO (Voage Control 11ed Osci11ator) is measured, and the VCO control voltage value corresponding to the measured VCO ambient temperature is recorded in the memory. . During the holdover period, the VCO control voltage value corresponding to the measured VCO ambient temperature is read from the memory, and the read VCO control voltage is input to the VCO to improve the frequency stability of the VCO with respect to the frequency temperature characteristics ( For example, see Patent Document 1).

  Further, as a method for improving the secular change during the holdover period, the phase difference of the phase detector output is read for each period notified by the clock means during synchronization, and the level of the VCO with respect to the secular change is read from the read phase difference information. The phase difference information is predicted, and the VCO control voltage value for correcting the phase difference with respect to the secular change is recorded in the memory. During the holdover period, the VCO control voltage value corresponding to the period is read from the memory for each period notified by the time measuring means, the read VCO control voltage is input to the VCO, and the frequency of the VCO with respect to secular change is obtained. Stability is improved (for example, refer patent document 2).

  Although not an example of DPLL, as a method for improving the frequency temperature characteristics and aging of the oscillation circuit, the oscillation frequency of the crystal oscillator is expressed as a function of aging and temperature, and the nominal frequency and aging which are parameters of this function are expressed. The coefficient related to change and the coefficient related to temperature are obtained from the crystal oscillator manufacturer and recorded in the nonvolatile memory. During the holdover period, the oscillation frequency of the crystal oscillator is predicted using the previous function, and the predicted frequency is compared with the standard frequency, and then the fractional processing is performed on the output clock of the crystal oscillator based on the compared error. That is, a desired vibration signal is obtained by adding or deleting cycles to the output clock of the crystal oscillator. During synchronization, the reference signal and the oscillation frequency of the crystal oscillator are compared, and the parameters of the previous function are re-evaluated based on the history of the error information thus compared (see, for example, Patent Document 3).

JP 2002-217722 A JP 2006-121171 A Special table 2004-516740 gazette

However, the invention described in Patent Document 1 cannot improve the secular change during the holdover period. Therefore, the frequency stability is deteriorated with respect to aging.
Further, the invention described in Patent Document 2 cannot improve the frequency temperature characteristics during the holdover period. Therefore, the frequency stability is deteriorated with respect to the temperature characteristics.
Moreover, since the invention described in Patent Document 3 is rounded, the obtained vibration signal includes a large jitter. In addition, since the means for recording the parameter of the function for predicting the oscillation frequency of the crystal oscillator in the nonvolatile memory is performed at the time of adjustment before shipment from the factory, adjustment costs are increased.

  The present invention has been made to solve the above-described problems, suppresses the influence on the temperature characteristics and aging during the holdover period, and does not require adjustment before shipment from the factory. An object of the present invention is to obtain a digital phase synchronization circuit having a holdover function for maintaining stability.

  The digital phase synchronization circuit according to the present invention comprises a reference signal extraction means for outputting a reference signal when a signal from a signal source to be synchronized is detected, a reference signal disconnection detection means for detecting a non-output state of the reference signal, Voltage-controlled clock oscillating means in which the frequency of the output clock is controlled by voltage, frequency dividing means for dividing the clock output from the voltage controlled clock oscillating means, and the frequency divided by the frequency dividing means A holdover function having phase detection means for comparing the phase difference between the peripheral clock and the reference signal from the reference signal extraction means, and digital filter means for removing high-frequency components of the phase difference detected by the phase detection means In the digital phase synchronization circuit comprising: the temperature measurement means for measuring the temperature around the voltage controlled clock oscillation means; and the synchronization target The voltage control type clock oscillation means is controlled by the output from the digital filter means, the output from the digital filter means, the temperature around the voltage control type clock oscillation means, the elapsed time from the history of elapsed time, and the above The temperature around the voltage controlled clock oscillating means and the binary polynomial in the term are obtained, and from the elapsed time not synchronized and the temperature around the voltage controlled clock oscillating means while not synchronized with the synchronization target. A voltage for controlling the voltage-controlled clock oscillation means with the binary polynomial, and a holdover means for controlling the voltage-controlled clock oscillation means with the estimated voltage.

  In another digital phase synchronization circuit according to the present invention, the digital filter output history output from the digital filter means and the temperature while the holdover means outputs the reference signal from the reference signal extraction means. The storage means for storing the temperature history measured by the measuring means, and the digital filter output using time and temperature as variables are approximated from the history of the digital filter output and the temperature history stored in the storage means 2 While obtaining the element polynomial, and while the reference signal is not output from the reference signal extracting means, the binary signal is used by using the elapsed time from the time when the output of the reference signal is cut off and the temperature measured by the temperature measuring means. The reference signal is output from the arithmetic means for obtaining a control signal for controlling the voltage-controlled clock oscillation means from the polynomial and the reference signal extraction means. The digital filter output outputted from the digital filter means is outputted to the D / A conversion means while the reference signal is not outputted, and the voltage controlled clock oscillation obtained by the arithmetic means is outputted. Switching means for outputting a control signal for controlling the means to the D / A conversion means.

  Further, in another digital phase synchronization circuit according to the present invention, while the arithmetic unit is synchronized with the synchronization target, an output history and a temperature history stored in the storage unit are stored in the storage unit. The binary having the smallest error between the control signal for controlling the voltage-controlled clock oscillation means obtained by each binary polynomial and the output from the actual digital filter means is obtained with reference to FIG. While a polynomial is selected and not synchronized with the synchronization target, a control signal for controlling the voltage-controlled clock oscillation means is obtained with the previously selected binary polynomial.

  In another digital phase synchronization circuit according to the present invention, the arithmetic means refers to the history of the digital filter output and the temperature history recorded in the storage means while synchronizing with the synchronization target. Are prepared, and a plurality of binary polynomials corresponding one-to-one with the history of the plurality of ranges is obtained.

  According to the digital phase synchronization circuit of the present invention, the reference signal extraction means for outputting the reference signal when the signal from the signal source to be synchronized is detected, and the reference signal disconnection detection means for detecting the non-output state of the reference signal Voltage-controlled clock oscillation means in which the frequency of the output clock is controlled by voltage, frequency dividing means for dividing the clock output from the voltage-controlled clock oscillation means, and frequency division by the frequency dividing means A phase detection means for comparing the phase difference between the divided clock and the reference signal from the reference signal extraction means, and a digital filter means for removing a high frequency component of the phase difference detected by the phase detection means. In the digital phase synchronization circuit having an over function, the temperature measurement means for measuring the temperature around the voltage controlled clock oscillation means, and the synchronization target are synchronized. While the voltage control type clock oscillation means is controlled by the output from the digital filter means, the output from the digital filter means and the temperature around the voltage control type clock oscillation means, the elapsed time from the history of elapsed time, And the temperature around the voltage-controlled clock oscillating means and the binary polynomial in the term, while not synchronized with the synchronization target, the elapsed time not synchronized and the surroundings of the voltage-controlled clock oscillating means And a holdover means for controlling the voltage-controlled clock oscillation means with the estimated voltage and estimating the voltage for controlling the voltage-controlled clock oscillation means with the binary polynomial from the temperature. The effect of suppressing the deterioration of the frequency stability during the holdover period can be obtained.

  According to another digital phase synchronization circuit of the present invention, the digital filter output history recorded in the storage means and the temperature around the voltage controlled clock oscillation means while synchronizing with the target signal source. Since the binary polynomial is obtained from the above history by the calculation means, since the parameters of the voltage controlled clock oscillation means are not required in advance, the adjustment cost before shipment from the factory can be omitted, and the cost of the apparatus can be reduced. The effect of suppressing can be obtained.

  Further, according to another digital phase synchronization circuit according to the present invention, the arithmetic unit is configured to store the output history and temperature of the output from the digital filter unit stored in the storage unit while synchronizing with the synchronization target. A plurality of binary polynomials are obtained by referring to the history, and the error between the control signal for controlling the voltage controlled clock oscillation means obtained by each binary polynomial and the output from the actual digital filter means is the smallest. While the binary polynomial is selected and not synchronized with the synchronization target, a control signal for controlling the voltage-controlled clock oscillation means is obtained with the previously selected binary polynomial, so that the frequency stability during the holdover period is increased. A highly stabilizing effect can be obtained.

  According to another digital phase synchronization circuit of the present invention, the arithmetic means refers to the history of the digital filter output and the temperature history recorded in the storage means while synchronizing with the synchronization target. A plurality of ranges are prepared, and a plurality of binary polynomials corresponding one-to-one are obtained from the history of the plurality of ranges, so that the effect of highly stabilizing the frequency stability during the holdover period can be obtained.

1 is a block diagram showing a digital phase locked loop circuit having a holdover function according to Embodiment 1 of the present invention. FIG. It is the graph which illustrated the temperature around the filtered phase difference signal from the digital filter measured while synchronizing with a GPS satellite, and OCXO. It is the graph which illustrated the filtered phase difference signal and OCXO control voltage estimated value of the digital filter during synchronizing with a GPS satellite. It is a standard deviation of the OCXO control voltage estimated value obtained by a binary polynomial.

Hereinafter, preferred embodiments of a digital phase locked loop (DPLL) of the present invention will be described with reference to the drawings.
Embodiment 1 FIG.
1 is a block diagram showing a digital phase locked loop circuit (DPLL) having a holdover function according to Embodiment 1 of the present invention.
The DPLL having a holdover function according to the first embodiment of the present invention includes a GPS antenna 2, a GPS receiver 3 as a reference signal extraction means, a phase detector 4, a digital filter 5, a reference signal break detection circuit 6, and a holdover circuit. 7, a D / A converter 8, an OCXO 9, a frequency divider 11, and a temperature sensor 12.

The GPS antenna 2 receives radio waves from a GPS satellite (not shown).
The GPS receiver 3 outputs 1 PPS as a reference signal synchronized with the GPS satellite while receiving a signal emitted from the GPS satellite to be synchronized from the radio wave received by the GPS antenna 2.
The phase detector 4 detects a phase difference between 1PPS output from the GPS receiver 3 and the divided clock output from the frequency divider 11 and outputs a signal corresponding to the phase difference.
The digital filter 5 is a low-pass filter, attenuates the high-frequency component of the signal corresponding to the phase difference output from the phase detector 4 and outputs a filtered phase difference signal.
The reference signal disconnection detection circuit 6 detects that 1 PPS is not output from the GPS receiver 3 and outputs a reference signal disconnection signal.

The holdover circuit 7 outputs the filtered phase difference signal from the digital filter 5 as it is when the reference signal disconnection signal is not input, and receives the reference signal disconnection signal when the reference signal disconnection signal is input. The estimated value estimated from the history of the filtered phase difference signal and the temperature history from the temperature sensor 12 when not being output is output.
The D / A converter 8 converts the signal output from the holdover circuit 7 into an analog signal.
The OCXO 9 outputs a clock having a frequency controlled according to the voltage of the analog signal output from the D / A converter 8.
The frequency divider 11 outputs a divided clock obtained by dividing the clock output from the OCXO 9.
The temperature sensor 12 measures the temperature near the OCXO 9 and inputs it to the holdover circuit 7.

The holdover circuit 7 according to the first embodiment of the present invention includes a calculator 15, a memory 16, and a switch 17.
Calculator 15, while synchronized with the GPS satellites, that is, between the reference signal loss signal outputted from the reference signal-off detection circuit 6 is inactive, the filtered phase difference signal v _c and the temperature from the digital filter 5 The temperature T _m around the OCXO 9 measured by the sensor 12 is stored in the memory 16 at a predetermined cycle. Further, from the history of the temperature T _m of a periphery of the history and OCXO9 of the filtered phase difference signal v _c output from the digital filter 5 and is stored in the memory 16, obtains the binary approximation formula that approximates the voltage for controlling the OCXO9.
Further, the arithmetic unit 15 is configured to detect the holdover elapsed time t and the temperature T around the OCXO 9 while the GPS-related failure occurs, that is, while the reference signal disconnection signal output from the reference signal disconnection detection circuit 6 is active. _An OCXO control voltage estimated value is obtained from _m by a binary polynomial.

Switch 17, while synchronized with the GPS satellites, that is, the reference signal-off between the reference signal-off signal output from the detection circuit 6 is inactive, the filtered phase difference signals output from the digital filter 5 v _c Is output. On the other hand, when a GPS-related failure occurs, that is, while the reference signal disconnection signal output from the reference signal disconnection detection circuit 6 is active, the OCXO control voltage estimated value output from the calculator 15 is output.
A signal output from the switch 17 is input to the D / A converter 8.

Next, an example will be described focusing on the holdover circuit 7 according to the first embodiment of the present invention.
Calculator 15, while synchronized with the GPS satellites, that is, the reference signal-off between the reference signal-off signal output from the detection circuit 6 is inactive, the filtered phase difference signals output from the digital filter 5 v _c and storing the ambient temperature _{T m} of a OCXO9 measured by the temperature sensor 12 in the memory 16 at a predetermined cycle. As an example, the predetermined period is one hour interval.
Calculator 15, from the history of the temperature _{T m} of a periphery of the history and OCXO9 of the filtered phase difference signal _{v c} output from the digital filter 5, which is stored in the memory 16, the OCXO control voltage estimate value for controlling the OCXO9 2 Estimate using the original polynomial.
Switch 17, switches between the filtered phase difference signal v _c output from the digital filter 5 and OCXO control voltage estimate value outputted from the arithmetic unit 15. A signal output from the switch 17 is input to the D / A converter 8.

If a failure related to GPS has occurred, that is, between the reference signal loss signal outputted from the reference signal-off detection circuit 6 is active, arithmetic unit 15, 2-way from the temperature T _m of a periphery of the holdover time elapsed t and OCXO9 An OCXO control voltage estimated value is obtained by a polynomial.

Next, a binary polynomial for estimating the OCXO control voltage will be described.
A DPLL using an OCXO 9 having a nominal frequency of 10 MHz and a frequency control characteristic ± 1 × 10 ⁻⁶ (control voltage 0 V to 4.0 V) and a D / A converter 8 having a resolution of 18 bits and an output voltage range of 0 V to +4.0 V is provided. Take an example.
FIG. 2 is a graph showing data obtained by actually measuring the output from the digital filter 5 and the temperature around the OCXO 9 with respect to the synchronization elapsed time when synchronized with a GPS satellite.
From FIG. 2, it can be seen that the GPS synchronization elapsed time and the temperature around the OCXO 9 affect the output of the digital filter 5. Further, the output of the digital filter 5 from FIG. 2, that is, the OCXO control voltage v _C (t, T _m ) is an equation (1) that is a binary polynomial whose terms are the elapsed time t and the temperature T _m around the OCXO 9. It is known that it can be expressed by the following formula (2). However, the equations (1) and (2) shown here are not applicable to all voltage controlled oscillators, and are different for each voltage controlled oscillator. Ask.

As a method for obtaining the coefficients A, B, C, and D in the equations (1) and (2), it is known that they are generally obtained by the least square method. While in synchronism with the GPS satellites, and obtain a history indicating the temperature T _m of a periphery of the filtered phase difference signal v _c and OCXO9 from the digital filter 5 stored in the memory 16 in the formula (3).

Here, the elapsed time history _{(t 1, t 2, ···} , t n) is not stored in the memory 16, the periphery of the filtered phase difference signal _{v c} and OCXO9 from the digital filter 5 in the memory 16 take the temperature _{T m} of the time of last recording at the origin, when the recording period was set to 1 hour interval, elapsed time history _{(t 1, t 2, ···} , t n) becomes equation (4) .

Coefficients A, B, C in equation (1) or coefficients A, B, C, D in equation (2) are respectively the filtered phase difference signal v _c from digital filter 5 and the temperature T _m around OCXO 9. From the history (t ₁ , t ₂ ,..., T _n ) of the elapsed time represented by the equation (4), it can be obtained by the equation (5) or the equation (6).

As an example, OCXO control voltage estimated value calculated by the filtered phase difference signal _{v c} and equation from the digital filter 5 while being synchronized to the GPS satellite _{(2) v c (t,} T m) to 3 . As can be seen from FIG. 3, is the filtered phase difference signal v _c from the digital filter 5, and can be approximated by a binary polynomial comprising the temperature T _m of a periphery of the elapsed time t and OCXO9 the section during holdover time In addition, the OCXO control voltage estimated value can be obtained by this binary polynomial.

  FIG. 4 shows the output accuracy of the digital filter 5, the temperature around the OCXO 9, the number of elapsed times and the binary polynomial, and the approximate accuracy of the OCXO control voltage estimated value 210 for the history update time while synchronizing with the GPS satellite. 4 is a table showing the standard deviation of the OCXO control voltage estimated value 210 obtained by a binary polynomial with the digital filter output 112 as an expected value.

The standard deviation sigma, the temperature T _m of a periphery of the filtered phase difference signal v _c and OCXO9 from the digital filter _5, using 24 samples of the history of the elapsed time t, given by Equation (7).

  As can be seen from FIG. 4, the binary polynomial and the number of histories influence the approximation accuracy of the OCXO control voltage estimated value as time passes. That is, a higher frequency stability can be obtained by selecting a binary polynomial having the smallest standard deviation of the OCXO control voltage estimated value and the number of histories and obtaining the OCXO control voltage estimated value during the holdover period.

  The above-described DPLL according to the first embodiment of the present invention controls the OCXO 9 with the output from the digital filter 5 while synchronizing with the temperature sensor 12 for measuring the temperature around the OCXO 9 and the GPS satellite, and the digital filter. 5 and the temperature around the OCXO9, the elapsed time, the temperature around the OCXO9 and the binary polynomial in the term are obtained from the history of the elapsed time, and while not synchronizing with the GPS satellite, it becomes out of sync with the GPS satellite And a holdover circuit 7 for controlling the OCXO 9 with the estimated control signal and estimating the control signal to control the OCXO 9 with a binary polynomial from the elapsed time and the ambient temperature of the OCXO 9. The effect of suppressing the deterioration of the frequency stability during the holdover period can be obtained.

  Therefore, the base station apparatus in which the DPLL according to the first embodiment of the present invention is mounted can maintain the synchronization between base stations even if the synchronization with the GPS satellite becomes impossible.

  The DPLL according to the first embodiment of the present invention uses 1 PPS output from the GPS receiver 3 synchronized with the GPS satellite as a reference signal, but it is not necessary to specify this reference signal. For example, the DPLL reference The signal can be replaced with a reference clock extracted from the communication network. Even when the reference clock cannot be extracted due to a communication network failure, the frequency stability during the holdover period can be highly stabilized.

  In addition, the DPLL according to Embodiment 1 of the present invention is implemented in a base station of a mobile communication system and applied to maintain synchronization between base stations during a holdover period. For example, the DPLL can be mounted on a transmission device in a communication system and used for a transmission device that requires high frequency stability during a holdover period.

Further, the DPLL according to the first embodiment of the present invention uses the binary polynomial represented by the expression (1) or (2) from the output from the digital filter 5, the temperature around the OCXO 9, and the history of elapsed time. The binary polynomial represented by the equations (1) and (2) is obtained, and the OCXO control is performed during the holdover period by using the binary polynomial with the smaller error from the output from the digital filter 5. An estimated voltage value may be obtained.
Also, instead of two binary polynomials, three or more binary polynomials are obtained from the output from the digital filter 5, the temperature around the OCXO 9, and the history of the passage of time. The OCXO control voltage estimated value may be obtained during the holdover period using a small number of binary polynomials.

  Further, the DPLL according to the first embodiment of the present invention described above obtains a binary polynomial from the output from the digital filter 5, the temperature around the OCXO 9, and the history of elapsed time with one history of elapsed time as one. However, the history of elapsed time may be divided into a plurality of ranges, and a binary polynomial may be obtained from the output from the digital filter 5 in each range, the temperature around the OCXO 9, and the history of elapsed time.

  In this way, by using a plurality of binary polynomials or using a binary polynomial in a plurality of ranges, it is possible to obtain an effect of further stabilizing the frequency stability during the holdover period.

  2 GPS antenna, 3 GPS receiver, 4 phase detector, 5 digital filter, 6 reference signal disconnection detection circuit, 7 holdover circuit, 8 D / A converter, 11 frequency divider, 12 temperature sensor, 15 calculator, 16 Memory, 17 switcher.

Claims (4)

Reference signal extraction means for outputting a reference signal when a signal from a signal source to be synchronized is detected;
A reference signal disconnection detecting means for detecting a non-output state of the reference signal;
Voltage-controlled clock oscillation means in which the frequency of the output clock is controlled by voltage;
Frequency dividing means for dividing the clock output from the voltage controlled clock oscillation means;
Phase detection means for comparing the phase difference between the frequency-divided clock divided by the frequency dividing means and the reference signal from the reference signal extraction means;
Digital filter means for removing high-frequency components of the phase difference detected by the phase detection means;
In a digital phase synchronization circuit having a holdover function,
Temperature measuring means for measuring the temperature around the voltage controlled clock oscillating means;
While synchronizing with the object to be synchronized, the voltage-controlled clock oscillation means is controlled by the output from the digital filter means, and the output from the digital filter means and the temperature around the voltage-controlled clock oscillation means, the progress The elapsed time, the temperature around the voltage-controlled clock oscillation means, and the binary polynomial in the term are obtained from the history of the time, and the time since the synchronization object is not synchronized while not synchronized with the synchronization object A control signal for controlling the voltage controlled clock oscillating means is estimated from the time and the temperature around the voltage controlled clock oscillating means by the binary polynomial, and the voltage controlled clock oscillating means is controlled by the estimated control signal. Holdover means;
A digital phase locked loop circuit comprising: The holdover means is
Storage means for storing the output history from the digital filter means and the temperature history measured by the temperature measurement means while the reference signal is being output from the reference signal extraction means;
Obtaining a binary polynomial that approximates the output from the digital filter means having elapsed time and temperature as variables from the history of the output from the digital filter means and the temperature history stored in the storage means, and the reference signal extraction means While the reference signal is not output from the control circuit, the voltage-controlled clock oscillation means is controlled from the binary polynomial using the elapsed time from when the output of the reference signal is cut off and the temperature measured by the temperature measurement means. Computing means for obtaining a control signal to be
While the reference signal is output from the reference signal extraction means, the output from the digital filter means is output to the voltage controlled clock oscillation means, and is estimated by the arithmetic means while the reference signal is not output. Switching means for outputting a control signal for controlling the voltage controlled clock oscillation means to the voltage controlled clock oscillation means;
The digital phase locked loop circuit according to claim 1, comprising:   The arithmetic means obtains a plurality of binary polynomials while referring to the output history and the temperature history from the digital filter means stored in the storage means while synchronizing with the synchronization target, The binary polynomial having the smallest error between the control signal for controlling the voltage-controlled clock oscillation means obtained by the binary polynomial and the output from the actual digital filter means is selected, and is not synchronized with the synchronization target. 3. The digital phase locked loop circuit according to claim 2, wherein a control signal for controlling the voltage-controlled clock oscillation means is obtained by a previously selected binary polynomial.   The arithmetic means prepares a plurality of ranges for referring to the digital filter output history and the temperature history recorded in the storage means while synchronizing with the synchronization target, and sets one pair to the history of the plurality of ranges. 4. The digital phase locked loop circuit according to claim 3, wherein a plurality of binary polynomials corresponding to 1 are obtained.

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